CN113655736A - System consisting of electrically isolated, data-coupled microcontrollers - Google Patents

Abstract

Translated fromChinese

由电隔离的、数据耦合的微控制器组成的系统。本发明涉及一种由微控制器组成的系统，该系统具有第一微控制器（100）和第二微控制器（200），其中第一微控制器（100）和第二微控制器（200）彼此电隔离（400），其中第一微控制器（100）具有第一处理器单元（110）和连接至第一处理器单元（110）的第一通信接口（120），第一通信接口被设立为能够实现对第一处理器单元的存储单元（140、141、142）的直接存储器访问，其中第二微控制器（200）具有第二处理器单元（210）和连接至第二处理器单元（210）的第二通信接口（220），第二通信接口被设立为能够实现对第二处理器单元的存储单元（240、241、242）的直接存储器访问，而且其中第一通信接口（120）和第二通信接口（220）彼此耦合（300）。

A system consisting of electrically isolated, data-coupled microcontrollers. The invention relates to a system consisting of microcontrollers, the system having a first microcontroller (100) and a second microcontroller (200), wherein the first microcontroller (100) and the second microcontroller ( 200) are electrically isolated (400) from each other, wherein the first microcontroller (100) has a first processor unit (110) and a first communication interface (120) connected to the first processor unit (110), the first communication The interface is set up to enable direct memory access to the memory units (140, 141, 142) of the first processor unit, wherein the second microcontroller (200) has the second processor unit (210) and is connected to the second a second communication interface (220) of the processor unit (210), the second communication interface being set up to enable direct memory access to the memory units (240, 241, 242) of the second processor unit, and wherein the first communication The interface (120) and the second communication interface (220) are coupled (300) to each other.

Description

System consisting of electrically isolated, data-coupled microcontrollers

Technical Field

The invention relates to a system consisting of electrically isolated microcontrollers.

Background

Modern microcontrollers used, for example, in (motor) vehicles, in addition to a processor unit or microprocessor and a memory unit (flash memory, EEPROM memory, RAM memory, etc.), mostly comprise additional peripheral devices, for example network interfaces, ADCs, DACs, timers, CANs, I/O, etc., which are connected to one another and are connected in communication with one another by an internal communication system, for example an internal bus.

Such processor units or microprocessors are usually configured as multicore processors having a plurality of (at least two) processor Cores (Cores). A processor Core or Core includes an Arithmetic Logic Unit (ALU), which is an actual electronic operator for executing tasks, programs, calculation instructions, and the like; and also includes one or more local memories. Such a local memory can be implemented, for example, as a Cache memory (Cache) or as a register bank of one or more registers or as a RAM memory.

In technical applications, such as in the (motor) vehicle sector, a large number of different microcontrollers are often used, which can often also be arranged in different voltage domains. In this way, for example, different onboard electrical systems can be provided in the vehicle, which have different supply or onboard electrical system voltages, for example: a low-voltage vehicle electrical system having a low vehicle electrical system voltage of, for example, 12V or 24V; and a high-voltage vehicle electrical system having a high supply voltage of, for example, 48V or even 800V. For safety reasons, for example to prevent feedback in the event of a fault and to avoid crosstalk and voltage peaks, such vehicle electrical systems with different voltage levels are mostly electrically isolated and there is no common reference potential. The microcontrollers provided in these onboard electrical systems are therefore also electrically isolated from one another. Exchanging data or signals between such electrically isolated microcontrollers can often prove complex and expensive. Exemplary implementations in which different microcontrollers are coupled via a vehicle bus system (e.g., CAN) are thus limited with respect to data rate and latency.

Disclosure of Invention

According to the invention, a system of electrically isolated microcontrollers is proposed with the features of patent claim 1. Advantageous embodiments are the subject matter of the dependent claims and the subsequent description.

The system has a first microcontroller and a second microcontroller, the first and second microcontrollers being electrically isolated from each other. Therefore, there is no common reference potential between the two microcontrollers. The first microcontroller is in particular designed to be connected to a first supply voltage source, and the second microcontroller is in particular designed to be connected to a second supply voltage source, wherein the first supply voltage source and the second supply voltage source are electrically isolated. Furthermore, the first supply voltage source and the second supply voltage source each expediently provide a different level of supply voltage. The first and second microcontrollers are each arranged in particular in different voltage domains, and there is no common reference potential for the two voltage domains. It is easy to understand that: in these voltage domains, further components can be provided in addition to the respective microcontroller. It is also easy to understand that: the system may also have other microcontrollers and other components.

Now, the invention offers the following possibilities: these electrically isolated microcontrollers or their processor units are coupled to one another in a data-transmitting manner, so that the microcontrollers or their processor units can communicate directly with one another.

The first microcontroller has a first processor unit and a first communication interface connected to the first processor unit, which is set up to enable Direct Memory Access (DMA) to a memory unit of the first processor unit, in particular a working memory such as a RAM or a register. Correspondingly, the second microcontroller has a second processor unit and a second communication interface connected to the second processor unit, which is set up to enable direct memory access to a memory unit of the second processor unit, in particular a working memory such as a RAM or a register. The first communication interface and the second communication interface are connected in a data-transmitting manner by means of an isolating coupler, for example via an opto-coupler, a magnetic coupler or a capacitive coupler.

The first and second processor units may each be configured, for example, as single-core processors having one processor core or, where appropriate, also as multi-core processors having a plurality of processor Cores (Cores). In particular, the first processor unit and the first communication interface are connected to a first microcontroller internal communication or connection system, for example to an internal bus of the first microcontroller or to an internal Crossbar (Crossbar) connection. Correspondingly, the second processor unit and the second communication interface are also connected to a corresponding second microcontroller internal communication or connection system of the second microcontroller. In addition, in the first or second microcontroller, further components CAN be connected to the respective processor unit and the respective communication interface, in particular a memory unit, for example a flash memory, an EEPROM memory, a RAM memory, etc., and additional peripherals, for example a network interface, ADC, DAC, timer, CAN, I/O, etc., respectively, via a respective communication or connection system.

By means of the coupling between the first communication interface and the second communication interface, a virtual connection can be established particularly advantageously between the communication or connection systems of the first and second microcontroller. In particular, in this way a virtual communication or connection system can be generated across the microcontroller, via which the first and second processor units can communicate directly with one another.

Furthermore, the processor units can particularly advantageously access components of the respective other microcontroller directly via the coupled communication interface, in particular directly access components which are connected to the microcontroller internal communication or connection system of the respective other microcontroller. Thus, for example, a processor unit of one of the two microcontrollers may directly access a memory or a peripheral of the other microcontroller via the coupling.

The present invention provides a tightly coupled multi-core processor system in which the individual processor units are arranged in different electrically isolated voltage domains. By coupling the two microcontrollers via the communication interfaces, the number of signals which have to cross the voltage domains of the microcontrollers can be significantly reduced in particular. For example, fast signals or regulation loops can be processed locally.

In an implementation of an overall system with microcontrollers from the same processor family, the program code portions can be allocated most reasonably from the point of view of resource allocation, run-time characteristics and access to the interfaces of the corresponding voltage domains, for example. This allocation of program code sections can be specified in particular once during the initial programming.

Due to the high performance of the communication interface, in particular due to the high data rate and low latency, the code portions may be bundled on a microcontroller and only certain portions may be implemented in another microcontroller, as appropriate. Thus, a flexible allocation of homogeneous software code portions can be achieved.

Furthermore, for example, a greater choice of resources or peripherals can be achieved in that the processor unit of one of the microcontrollers can access the peripherals of the other microcontroller via the coupled communication interface.

These communication interfaces are used in particular for coupling microcontroller internal communication systems and thus processor units. It is particularly advantageous that the processor units maintain a bidirectional or full-duplex communication connection via the communication interfaces. In particular, data can be transmitted between the two processor units in both directions simultaneously. Thus, each of the processor units may particularly suitably simultaneously transmit data to and receive data from another processor unit.

Preferably, the first communication interface and the second communication interface are optically coupled. Signals are optically transmitted between these communication interfaces. In particular, electrical and optical signals are converted for this purpose. For the transmission of data, the electrical signals are expediently converted into optical signals on the respective transmitting communication interface, and these optical signals are transmitted via a coupling to the other receiving communication interface. Where the optical signal is suitably reconverted into an electrical signal. In order to transmit data or signals between these microcontrollers, therefore, it is particularly expedient not to require an electrical connection between these microcontrollers.

Particularly preferably, the first communication interface and the second communication interface are coupled by at least one optocoupler. In particular, the different transmitting and receiving units (transceivers) of the two communication interfaces are each coupled to one another by an optocoupler. The optoelectronic coupler is in particular a coupling mechanism or an optoelectronic device element for optically transmitting signals between electrically isolated elements. For this purpose, the optocoupler has, in particular: an optical transmitter, such as a Light Emitting Diode (LED) or a Laser Diode (LD); and an optical receiver, such as a photodiode, phototransistor, Triac, etc., wherein the transmitter and the receiver are optically coupled and connected, such as by an optical conductor.

The first communication interface and the second communication interface are each preferably designed as a full-duplex interface, in particular as a full-duplex high-speed interface, and are preferably set up for simultaneous bidirectional transmission. Thus, in particular a simultaneous data transmission between the first and the second processor unit may be achieved. Suitably, the two processor units may transmit and receive data simultaneously, respectively.

Advantageously, the first communication interface and the second communication interface are each designed as an LVDS interface (Low Voltage Differential signaling, LVDS). LVDS is an interface standard for high speed data transmission standardized according to ANSI/TIA/EIA-644 and 1995. Such LVDS interfaces have, in particular, a Low Voltage level ("Low Voltage") and also a Differential Voltage level ("Differential signaling"). Furthermore, the signal is generated, in particular, with a constant current source. Such an LVDS Interface can be designed, for example, as a so-called LFAST/SIPI Interface ("LVDS Fast Asynchronous Transmission Interface"), LFAST, or "Serial Interface-Processor Interface," SIPI) or, for example, as a so-called HSCT/HSSL Interface ("High Speed Serial Link"), HSSL.

According to a preferred embodiment, at least five signal connections of the first communication interface and at least five signal connections of the second communication interface are coupled to one another. In particular, the signal connections are preferably coupled optically, in particular by one or more optocouplers. These signal connections are used in particular for coupling in or out signals.

Particularly preferably, the at least five signal connections of the first communication interface and the at least five signal connections of the second communication interface each comprise: at least one signal connection for transmitting time or clock signals; at least two signal connections for outputting data signals; and at least two signal connections for receiving data signals. In this case, two of the signal connections of one communication interface are expediently used as output connections for transmitting data signals to the other communication interface. Correspondingly, two of these signal connections serve as input connections for receiving data signals from the other communication interface. Clock signals are used in particular for synchronizing microcontrollers or their internal clock generation. In particular, one of the microcontrollers is provided as a master, which presets a time base for the other microcontroller provided as a slave.

Particularly preferably, the signal connections of the two communication interfaces for the clock signal are coupled via a first optocoupler. The at least two input connections of the first communication interface are coupled to the at least two output connections of the second communication interface, in particular via a second optocoupler. Correspondingly, at least two output connections of the first communication interface, in particular at least two input connections of the second communication interface, are coupled via a third optocoupler.

The first processor unit is preferably set up to: the memory unit connected to the second processor unit is accessed during Direct Memory Access (DMA) via a coupled communication interface. Correspondingly, the second processor unit is preferably set up to: a memory unit connected to the first processor unit is accessed during Direct Memory Access (DMA) via a coupled communication interface. In particular, these memory units are connected to the respective processor units via respective microcontroller internal communication systems. These memory units may be, for example, flash memories, EEPROM memories or RAM memories, respectively. The processor units can therefore particularly advantageously communicate with each other via DMA accesses via the coupled communication interface. By means of such Direct Memory Access (DMA), it is possible to make these processor units suitably implement direct access to a memory unit connected to the respective other processor unit without communicating with the other processor unit here.

According to a particularly advantageous embodiment, the system consisting of the microcontroller is used in a (motor) vehicle. These microcontrollers can be used in particular in control devices of a vehicle which are electrically isolated from one another.

The first microcontroller is particularly advantageously arranged in a first vehicle electrical system, in which the first supply voltage source supplies a first vehicle electrical system voltage. The second microcontroller is advantageously arranged in a second onboard electrical system, in which the second supply voltage source supplies a second onboard electrical system voltage. The two onboard electrical systems are expediently electrically isolated from one another and have no common reference potential. Expediently, the two on-board electrical systems differ in voltage. One of the two onboard electrical systems is in particular provided as a low-voltage onboard electrical system, which has a low onboard electrical system voltage of, for example, 12V. The further onboard electrical system is expediently configured as a high-voltage onboard electrical system, which has a high onboard electrical system voltage of, for example, between 48V and 800V. In particular, communication of these electrically isolated onboard electrical systems or their control devices can be carried out without the signals having a common reference potential for this purpose.

Further advantages and embodiments of the invention emerge from the description and the accompanying drawings.

The invention is schematically illustrated in the drawings and will be described below with reference to the drawings according to embodiments.

Drawings

Fig. 1 schematically shows a preferred embodiment of a system according to the invention, which is composed of a microcontroller.

Fig. 2 schematically shows a section of a preferred embodiment of the system according to the invention, which is composed of a microcontroller.

Detailed Description

Fig. 1 schematically shows a preferred embodiment of a system according to the invention, which is composed of afirst microcontroller 100 and asecond microcontroller 200.

Themicrocontrollers 100, 200 are each provided, for example, in a control device of the vehicle and also in different onboardelectrical systems 410, 420 of the vehicle.

For example, thefirst microcontroller 100 is arranged in a first onboardpower supply system 410, in which the firstsupply voltage source 411 supplies a first onboard power supply system voltage, and thesecond microcontroller 200 is arranged in a second onboardpower supply system 420, in which the secondsupply voltage source 421 supplies a second onboard power supply system voltage. For example, first onboardelectrical system 410 is a low-voltage onboard electrical system having an onboard electrical system voltage of 12V, and onboardelectrical system 420 is a high-voltage onboard electrical system having an onboard electrical system voltage of 48V. For safety reasons, for example to prevent feedback in the event of a fault and to avoid crosstalk and voltage peaks, the onboardelectrical systems 410, 420 and therefore themicrocontrollers 100, 200 are electrically isolated and have no common reference potential. Each of the onboardelectrical systems 410, 420 has its own,independent reference potential 412 or 422. The electrical isolation between themicrocontrollers 100, 200 is also schematically outlined in fig. 1 by the dashedline 400.

Thefirst microcontroller 100 has afirst processor unit 110 with twoprocessor cores 111, 112. For example, therespective processor cores 111 and 112 may have an arithmetic logic unit and an internal RAM memory, respectively, and an interface to connect theprocessor cores 111, 112 to the microcontrollerinternal communication system 101 of thefirst microcontroller 100. The microcontrollerinternal communication system 101 can be designed, for example, as a crossbar connection.

Thecommunication system 101 is in particular provided as a processor core communication system in order to connect other components of themicrocontroller 100 directly to theprocessor cores 111, 112. In particular, different memory units are connected to thecrossbar connection 101, such as aflash memory 140, anEEPROM memory 141 and aRAM memory 142.

Furthermore, a second microcontrollerinternal communication system 102, for example afurther crossbar connection 102, is provided in themicrocontroller 100. Thefurther crossbar connection 102 may be provided in particular for peripheral units. For example, a plurality ofdifferent interfaces 150, 151, 152, 153, 154, 155 can be provided in order to connect themicrocontroller 100 to components of the vehicle, such as sensors, actuators, field buses, etc. For example, a message buffer orbuffer 160 is also connected to thefurther crossbar connection 102, which message buffer or buffer CAN be connected via twoconnections 161, 162 to a field bus (for example CAN or the like) of the vehicle for receiving or transmitting messages. In addition, an analog-to-digital converter 170 is connected to thecrossbar connection 102.

The twocrossbar connections 101, 102 of thefirst microcontroller 100 are also connected to each other by aunit 103 for Direct Memory Access ("DMA"). In this manner, the respective peripheral units may suitably directly accessmemory units 140, 141, 142 without communicating withprocessor cores 111, 112.

Thefirst microcontroller 100 also has afirst communication interface 120 which is connected to theprocessor unit 110 or to theprocessor cores 111, 112 via thecrossbar connection 102. Furthermore, thefirst microcontroller 100 may also havefurther communication interfaces 130, 131, which may be designed, for example, in correspondence with thecommunication interface 120.

Thecommunication interface 120 is arranged to couple thefirst microcontroller 100 or a processor unit thereof with thesecond microcontroller 200.

Thesecond microcontroller 200 is, for example, of the same design as thefirst microcontroller 100. The elements of thesecond microcontroller 200, which are identical or structurally identical to the elements of thefirst microcontroller 100, are characterized by reference numerals increased by thevalue 100.

Thefirst communication interface 120 and thesecond communication interface 220 are coupled to one another in a data transmission manner by means of an isolating coupler, particularly suitably optically by means of acoupling mechanism 300 for optically transmitting signals between electrically isolated elements.

By means of thiscoupling 300 of the communication interfaces 120, 220, thefirst processor unit 110 or theprocessor cores 111, 112 and thesecond processor unit 210 or itsprocessor cores 211, 212 are kept in direct communication with each other.

By means of thecoupling 300 between the communication interfaces 120, 220, a virtual connection can be established particularly suitably between the processor core communication systems orcrossbar connections 101 and 201 of the first andsecond microcontrollers 100, 200. Particularly advantageously, a virtual, cross-microcontroller communication system is generated in this way for theprocessor cores 111, 112, 211, 212 of the twomicrocontrollers 100, 200, via which communication system the first andsecond processor units 110, 210 can communicate directly with one another.

Furthermore, by means of the virtual, cross-microcontroller communication system, direct memory access of the processor unit of one of the microcontrollers to the memory unit of the respective other microcontroller can be achieved. For example, thefirst processor unit 110 or itscores 111, 112 may directly access thememory units 240, 241, 242 of thesecond microcontroller 200 during a direct memory access via the coupled communication interfaces 120, 220. Correspondingly, thesecond processor unit 210 or itscores 211, 212 can directly access thememory units 140, 141, 142 of thefirst microcontroller 100 during a direct memory access via the coupled communication interfaces 120, 220.

The communication interfaces 130, 230 are each designed, for example, as a full-duplex interface for simultaneous bidirectional data transmission, so that the two processor units of themicrocontrollers 110, 120 can exchange data with one another at the same time. In addition, the communication interfaces 130, 230 are each designed, for example, as an LVDS interface ("Low Voltage Differential signaling") with a Low Differential Voltage level.

In particular, the communication is realized by the communication interfaces 130, 230 in accordance with the HSSL protocol (High Speed Serial Link). However, the invention is not so limited and may be applied in connection with any other type of suitable interface.

Fig. 2 schematically shows a section of a preferred embodiment of the system according to the invention, which is composed of a microcontroller. In fig. 2, the communication interfaces 120, 220 of themicrocontrollers 110, 210 and thecoupling mechanism 300 are schematically shown. Here, the same reference numerals in fig. 1 and 2 denote the same or structurally identical elements.

Thefirst communication interface 120 has a first signal connection 121 for transmitting a time signal. Correspondingly, thesecond communication interface 220 has a signal connection 221 for receiving a time signal. For example, thefirst microcontroller 100 may act as a master and thesecond microcontroller 200 may act as a slave, wherein themaster microcontroller 100 sends a corresponding time signal to theslave microcontroller 200 in order to establish a common time base.

Thesecond communication interface 220 further comprises two signal connections 222, 223 for outputting data signals, in particular a positive connection 222 and a negative connection 223. Correspondingly, thefirst communication interface 120 also comprises apositive signal connection 124 and a negative signal connection 125 for outputting a data signal.

Thefirst communication interface 120 also has positive andnegative signal connections 122 or 123 for receiving data signals, and thesecond communication interface 220 correspondingly has a positive signal connection 224 and a negative signal connection 225 for receiving data signals.

Thesignal connection terminals 121, 122, 123, 124, 125 of thefirst communication interface 120 are connected to correspondingtransceivers 126, 127, 128, and correspondingly the signal connection terminals 221, 222, 223, 224, 225 of thesecond communication interface 220 are also connected to correspondingtransceivers 226, 227, 228.

By means of these different connections for transmitting and receiving data signals, a bidirectional full-duplex data transmission, i.e. the simultaneous transmission and reception of data, can be achieved.

The coupling mechanism has three photocouplers by which the signal connection terminals 121 to 125 and 221 to 225 of the communication interfaces 120, 220 are optically coupled to each other.

For example, afirst optocoupler 310 having an optical transmitter 311 and an optical receiver 312 is provided in order to couple the signal connections 121 and 221 for the time signals.

Asecond optocoupler 320 having an optical transmitter 321 and an optical receiver 322 is provided in order to optically couple the signal connections 222 and 223 for transmitting data signals of thesecond communication interface 220 with thesignal connections 122 and 123 for receiving data signals of thefirst communication interface 120.

Athird optocoupler 330 with an optical transmitter 331 and an optical receiver 332 is also provided, via which thesignal connections 124 and 125 for transmitting data signals of thefirst communication interface 120 are optically coupled to the signal connections 224 and 225 for receiving data signals of thesecond communication interface 220.

For example, the respective optical transmitters 311, 321, 331 of thephotocouplers 310, 320, 330 may be respectively configured as Light Emitting Diodes (LEDs) or Laser Diodes (LDs). The optical receivers 312, 322, 332 may be configured, for example, as photodiodes, phototransistors, triacs, and the like, respectively.

Claims (9)

1. A system of microcontrollers, having a first microcontroller (100) and a second microcontroller (200),

wherein the first microcontroller (100) and the second microcontroller (200) are electrically isolated (400) from each other,

wherein the first microcontroller (100) has a first processor unit (110) and a first communication interface (120) connected to the first processor unit (110) which is set up to enable direct memory access to a memory unit (140, 141, 142) of the first processor unit,

wherein the second microcontroller (200) has a second processor unit (210) and a second communication interface (220) connected to the second processor unit (210), which is set up to enable direct memory access to a memory unit (240, 241, 242) of the second processor unit, and

wherein the first communication interface (120) and the second communication interface (220) are coupled in a data transmission manner by means of isolating couplers (300, 310, 320, 330).

2. The system according to claim 1, wherein the first communication interface (120) and the second communication interface (220) are each constructed as a full-duplex interface and are set up for simultaneous bidirectional transmission.

3. The system according to claim 1 or 2, wherein the first communication interface (120) and the second communication interface (220) are each configured as an LVDS interface.

4. The system of any of the preceding claims, wherein the first communication interface (120) and the second communication interface (220) are optically coupled (300).

5. The system according to any one of the preceding claims, wherein at least five signal connection terminals (121, 122, 123, 124, 125) of the first communication interface (120) and at least five signal connection terminals (221, 222, 223, 224, 225) of the second communication interface (220) are coupled to each other.

6. The system of claim 5, wherein the at least five signal connection terminals (121, 122, 123, 124, 125) of the first communication interface (120) and the at least five signal connection terminals (221, 222, 223, 224, 225) of the second communication interface (220) respectively comprise: at least one signal connection (121, 221) for transmitting a clock signal; at least two signal connections (124, 125, 222, 223) for outputting data signals; and at least two signal connections (122, 123, 224, 225) for receiving data signals.

7. The system according to any of the preceding claims, wherein the first processor unit (110) is set up to: accessing a memory unit (240, 241, 242) connected to the second processor unit (210) during a direct memory access through a coupled communication interface (110, 220, 300), and wherein the second processor unit (210) is set up to: a memory unit (140, 141, 142) connected to the first processor unit (110) is accessed during a direct memory access via the coupled communication interface (110, 220, 300).

8. A system according to any preceding claim, for use in a vehicle.

9. The system according to claim 8, wherein the first microcontroller (100) is arranged in a first onboard electrical system (410) in which a first supply voltage source (411) supplies a first onboard electrical system voltage, and wherein the second microcontroller (200) is arranged in a second onboard electrical system (420) in which a second supply voltage source (421) supplies a second onboard electrical system voltage.

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