Background
Power transistors, such as High Electron Mobility Transistors (HEMTs), are widely used in high frequency and high power applications such as wireless communication base stations, radar, and automotive electronics. Gallium nitride is used as an emerging semiconductor material, has the characteristics of wide forbidden band, high electron mobility and the like, and is particularly suitable for being applied to the field of power semiconductor devices such as HEMTs. Gallium nitride field effect transistors exhibit much lower on-resistance and capacitance than silicon like products. Gallium nitride field effect transistors have been demonstrated to greatly reduce the size, increase operating frequency, and increase efficiency of power conversion systems.
However, in practical use, the on-resistance of the power transistor inevitably exists. Even though the on-resistance of power transistors based on gallium nitride materials is smaller than that of similar products of silicon, it will not be zero. The presence of this on-resistance causes the power transistor to heat up and heat up when current flows. And an increase in temperature in turn increases the on-resistance. Therefore, if the heat dissipation of the power transistor is insufficient, the cycle may be a vicious cycle of temperature rise, resistance rise, temperature re-rise, and resistance re-rise until the power transistor is burned. Fig. 1 shows a graph of on-resistance of a gallium nitride power transistor with increasing temperature. It can be seen that the on-resistance and the rate of change of the power transistor increase significantly after the temperature rises to 55 degrees celsius.
The prior art approach to solving the above problems is to incorporate an overheat protection element or module in the circuit, as disclosed in US20020171405A1, by using a zener diode and a radiator to achieve heat dissipation while ensuring that the power transistor conducts a large current.
However, the power transistor is usually large in area, the temperature of each position is uneven, and when the transistor is burnt out due to overhigh temperature, the whole position of the transistor is often not burnt out at the same time, but a certain point is firstly hot spot-formed and burnt out. Such a situation results in limited utilization potential of power transistors such as HEMTs.
Disclosure of Invention
Aiming at the technical problems in the prior art, the application provides a power transistor which at least comprises a substrate, a buffer layer, a barrier layer, a grid electrode, a source electrode and a drain electrode, wherein the grid electrode, the source electrode and the drain electrode are positioned above the barrier layer, and one or more insulating isolation structures are arranged in a conductive channel below the grid electrode and between the source electrode and the drain electrode.
In particular, the isolation structure is formed in the barrier layer or in one or more layers of the barrier layer and below.
In particular, the isolation structure includes an insulating region formed by ion implantation.
In particular, the isolation structure comprises a hollowed-out area formed by etching.
In particular, the spacing between the isolation structures increases gradually from the center to the edge of the power transistor.
In particular, the ion implantation material forming the isolation structure is hydrogen or helium.
In particular, the width of the isolation structure is equal to the width of the gate.
In particular, the width of the isolation structure is greater than or less than the width of the gate.
In particular, the power transistor is a HEMT.
The application also provides an electronic device comprising one or more power transistors as described in any of the preceding.
According to the application, the isolation structure is arranged in the conducting channel of the power transistor, and the conducting path is optimized by reducing the part of conducting path with poor heat dissipation, so that the temperature distribution of the whole power transistor is more uniform, the possibility of hot spot generation is reduced, and the working stability of the power transistor is improved.
Drawings
Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
FIG. 1 is a graph showing the relationship between resistance and temperature of a conventional GaN power transistor;
fig. 2 is a cross-sectional view of a conventional HEMT power transistor;
FIG. 3A is a schematic diagram showing a partial amplification of a conventional HEMT power transistor;
FIG. 3B illustrates an exemplary layout of a conventional HEMT power transistor;
FIG. 4 shows a schematic layout of a HEMT power transistor according to one embodiment of the application;
fig. 5 shows a schematic layout of a HEMT power transistor according to another embodiment of the application;
FIGS. 6A-6C illustrate partial exemplary layouts of HEMT power transistors according to various embodiments of the application;
Fig. 7 is a schematic diagram showing a partial structure of a HEMT power transistor according to an embodiment of the present application, and
Fig. 8 is a schematic partial schematic perspective view of a HEMT power transistor according to another embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments of the application. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to embodiments of the present application.
The HEMT will be described and explained below as an example. Fig. 2 is a schematic cross-sectional view of a conventional HEMT. As shown, the HEMT includes, from bottom to top, at least a substrate 110, a buffer layer 120, and a barrier layer 140. Wherein the substrate material can be gallium nitride, silicon, sapphire, silicon carbide, aluminum nitride, diamond, the buffer layer material can be gallium nitride, aluminum nitride and mixtures thereof, and the barrier layer can be aluminum gallium nitride, aluminum nitride and the like. According to one embodiment, a source 150, a drain 170, and a gate 160 between the source and drain may also be provided over the barrier layer 140. Wherein each electrode material may be metal or polysilicon. An electron potential well is formed at the HEMT heterojunction interface, in which a two-dimensional electron gas is formed, thereby forming a conductive channel 130 between the buffer layer 120 and the barrier layer 140 that directs electrons to migrate from the source to the drain.
Fig. 3A is a partial enlarged view of a conventional HEMT power transistor. As shown in fig. 3A, one HEMT power transistor may include a plurality of sources 150 connected to each other, a plurality of drains 170 connected to each other, and a plurality of gates (not shown) distributed between the sources 150 and the drains 170.
Fig. 3B shows an exemplary layout of a conventional HEMT power transistor. A corresponding gate (not shown) and a channel region between the source and drain are distributed between each set of source 150 and drain 170 lines. The region 130 between the dashed lines in fig. 3B represents the conductive channel region under the gate. During operation of the power transistor, the temperature of the channel region may increase due to the presence of the on-resistance. In particular, at a relatively large distance from the transistor edge, the temperature may be higher due to insufficient heat dissipation.
Fig. 4 shows a schematic layout of a HEMT power transistor according to one embodiment of the application. As shown, one or more insulating isolation structures 180 may be disposed in the channel region between the source 150 and the drain 170. Current may still be conductively formed in the channel region where isolation structures 180 are not formed. In some embodiments, the plurality of isolation structures 180 may be uniformly distributed in the channel region, for example, as shown in fig. 4, the distance between the isolation structures 180 in the channel region between a set of sources and drains may be the same.
Fig. 5 shows a schematic layout of a HEMT power transistor according to another embodiment of the application. Since power transistors tend to have a certain area, the higher temperature points tend to be located near the center region of the transistor, while the edge regions of the transistor are relatively cooler than the center region because they can exchange heat with the environment more fully. In view of this, as shown, in this embodiment, the spacing between the isolation structures 180 may gradually increase from the center to the edge of the power transistor. In other embodiments, the isolation structure 180 may not be provided at the power transistor edge location.
The distance between the isolation structures 180 or the distribution density of the isolation structures 180 may be designed and adjusted according to the actual needs according to various embodiments.
Fig. 6A-6C illustrate partial exemplary layouts of HEMT power transistors according to various embodiments of the present application. As shown, the region 130 between the dashed lines represents the channel region under the gate, which is simply the middle portion of the entire channel region between the source and drain. As shown in fig. 6A, the isolation structures 180 may have a width that is substantially the same as the channel region or gate width dimension under the gate. As shown in fig. 6B, the width of the isolation structure 180 therein may be smaller than the gate width. As shown in fig. 6C, the width of the isolation structure 180 may be greater than the gate width, and the widest case of the isolation structure 180 may be up to the size between the source and the drain.
Fig. 7 is a schematic partial schematic perspective view of a HEMT power transistor according to an embodiment of the present application. According to one embodiment, the isolation structure 180 may be an insulating region formed by ion implantation. Ion implantation can accurately control the concentration distribution and implantation depth of ions, and has small lateral diffusion of ions and easy control of process conditions. According to one embodiment of the application, the implanted ions may be hydrogen or helium. According to one embodiment, the upper surface of the isolation structure 180 is the upper surface of the barrier layer 140, and the depth of the isolation structure 180, i.e., the depth of implantation, may relate to a portion or all of the thickness of the barrier layer, e.g., the isolation structure may extend down from the upper surface of the barrier layer 140 to 10-50nm at the deepest depth of the barrier layer 140. According to one embodiment of the present application, the depth of the isolation structure 180 may be such that, in addition to the barrier layer 140, the implant may also penetrate into part or all of the buffer layer 120, e.g., the isolation structure 180 may be as deep as 10-50nm extending downward from the lower surface of the barrier layer 140 in the buffer layer 120. According to other embodiments, other layer structures may be included in the HEMT, and the isolation structure 180 may be at least partially or fully involved in or deep into the barrier layer 140, or involved in or deep into one or more layers of the barrier layer 140 and below.
Fig. 8 is a schematic partial schematic perspective view of a HEMT power transistor according to another embodiment of the present application. As shown, the isolation structure 180 may be a hollowed-out area formed by etching, wherein the hollowed-out area is not conductive. The etching means may be dry etching, wet etching, or a combination of both.
In some embodiments, the width of the etched hollowed-out area may be smaller, equal to, or greater than the width of the gate. The depth of the etch may relate to part or all of the barrier layer 140, part or all of the buffer layer 120, or even part or all of the substrate 110 or other layer structure.
It will be appreciated by those skilled in the art that the above structure is not limited to gallium nitride or any particular material. Nor is it limited to the specific structure of the HEMT device.
The device structure provided by the application can effectively relieve the condition that the device is burnt out due to the heating of the power device caused by the on-resistance. Through effectual regulation isolation structure shape, distribution density, can reduce the heating problem of device under the prerequisite of guaranteeing power device electrical property to improve the practical life of device.
The above embodiments are provided for illustrating the present application and not for limiting the present application, and various changes and modifications may be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.