CN113411093A - Signal receiving device and method with anti-radio frequency interference mechanism - Google Patents
Signal receiving device and method with anti-radio frequency interference mechanismDownload PDFInfo
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- CN113411093A CN113411093ACN202010186576.7ACN202010186576ACN113411093ACN 113411093 ACN113411093 ACN 113411093ACN 202010186576 ACN202010186576 ACN 202010186576ACN 113411093 ACN113411093 ACN 113411093A
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- 238000006243chemical reactionMethods0.000claimsabstractdescription17
- 238000000605extractionMethods0.000claimsdescription14
- 238000001514detection methodMethods0.000claimsdescription12
- 230000005540biological transmissionEffects0.000description6
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- 238000010586diagramMethods0.000description4
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/1027—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal
- H04B1/1036—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/12—Neutralising, balancing, or compensation arrangements
- H04B1/123—Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means
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Abstract
Translated fromChinese
Description
Technical Field
The present invention relates to signal receiving technologies, and in particular, to a signal receiving apparatus and method with an anti-radio frequency interference mechanism.
Background
In some communication systems, data reception is required through clock recovery techniques. More specifically, the clock recovery technique is to extract the frequency information of the signal transmitter from the data stream by the signal receiver, so as to decode the received data according to the information.
The transmission channel between the signal transmitting end and the signal receiving end is subject to, for example, but not limited to, temperature, and additional delay is continuously generated, so that the clock recovery technique needs to continuously correct the extracted frequency information. However, in some usage scenarios, the signal receiving end may experience transient radio frequency interference due to nearby electronic devices that may emit radio frequency signals. In such a situation, if there is no effective coping mechanism, the frequency information extracted by the signal receiving end will greatly fluctuate due to the radio frequency interference, and the received signal cannot be correctly decoded.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a signal receiving apparatus and method with an anti-rfi mechanism, so as to improve the prior art.
The present invention includes a signal receiving apparatus with Radio Frequency Interference (RFI) immunity mechanism, wherein an embodiment of the signal receiving apparatus includes an analog-to-digital conversion circuit, an equalization circuit, and a clock recovery circuit. The analog-to-digital conversion circuit is configured to perform analog-to-digital conversion on an input analog signal according to an internal clock signal to generate an input digital signal. The equalization circuit is configured to equalize an input digital signal to produce an equalized input signal. The clock recovery circuit is configured to operate on the equalized input signal to adjust a phase of the internal clock signal, and count phase offset information in units of time windows to perform frequency extraction on the equalized input signal, wherein the phase offset information includes a plurality of phase offsets, the time windows include a plurality of sub-time windows, and the plurality of phase offsets correspond to the plurality of sub-time windows. The clock recovery circuit is further configured to determine a signal interference parameter for one of the sub-time windows and discard phase offsets corresponding to the corresponding plurality of sub-time windows from the plurality of phase offset amounts when the signal interference parameter is greater than a threshold value to generate updated phase offset information. The clock recovery circuit generates an adjustment signal according to the updated phase offset information to adjust the frequency of the internal clock signal.
The invention further provides a signal receiving method with an anti-radio frequency interference mechanism, which is applied to a signal receiving device, and one embodiment of the invention comprises the following steps: enabling the analog-to-digital conversion circuit to perform analog-to-digital conversion on the input analog signal according to the internal clock signal so as to generate an input digital signal; equalizing the input digital signal by an equalizing circuit to generate an equalized input signal; the clock recovery circuit is used for calculating the equalized input signal to adjust the phase of the internal clock signal, and counting phase offset information by taking a time window as a unit to extract the frequency of the equalized input signal, wherein the phase offset information comprises a plurality of phase offsets, the time window comprises a plurality of sub-time windows, and the phase offsets correspond to the sub-time windows; enabling the clock recovery circuit to judge a signal interference parameter of one of the sub-time windows, and abandoning corresponding phase offset quantities of the corresponding sub-time windows from the multiple phase offset quantities to generate updated phase offset quantity information when the signal interference parameter is larger than a threshold value; and enabling the clock recovery circuit to generate an adjusting signal according to the updated phase offset information so as to adjust the frequency of the internal clock signal.
The features, practical operation and efficacy of the present invention will be described in detail with reference to the accompanying drawings in which preferred embodiments are shown and described.
Drawings
FIG. 1 is a block diagram of a signal receiving apparatus with an anti-RF interference mechanism according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a time window in an embodiment of the invention; and
fig. 3 shows a flow chart of a signal receiving method in an embodiment of the invention.
Detailed Description
An object of the present invention is to provide a signal receiving apparatus and method with an anti-radio frequency interference mechanism, which can avoid a large frequency offset caused by misjudgment due to radio frequency interference.
Refer to fig. 1. Fig. 1 is a block diagram of asignal receiving apparatus 100 with an anti-Radio Frequency Interference (RFI) mechanism according to an embodiment of the present invention. Thesignal receiving apparatus 100 is configured to communicate with a signal transmitting terminal (not shown) via a transmission channel. In more detail, the signal transmitter generates a signal according to an internal clock signal, and the signal transmitter is transmitted through the transmission channel and then received by thesignal receiver 100 as the input analog signal IAS.
Thesignal receiving apparatus 100 includes: an analog-to-digital conversion circuit 110, anequalization circuit 120, and aclock recovery circuit 130.
The analog-to-digital conversion circuit 110 is configured to sample the input analog signal IAS according to the internal clock signal CLK to perform analog-to-digital conversion and generate an input digital signal IDS. In one embodiment, the internal clock signal CLK may be generated by aclock generation circuit 140 also included in thesignal receiving device 100.
Theequalization circuit 120 is configured to equalize an input digital signal IDS and to generate an equalized input signal EIS. In one embodiment, the equalization process performed by theequalization circuit 120 is configured to eliminate inter-symbol interference (ISI) caused by the transmission channel.
In an embodiment, the equalizingcircuit 120 further transmits the equalized input signal EIS to thedata processing circuit 150 included in thesignal receiving apparatus 100 for processing. In an embodiment, the signal transmitting end encodes the signal to be transmitted by a pulse-amplitude modulation (PAM) technique. Therefore, thedata processing circuit 150 may include a module (not shown) such as, but not limited to, a data slicer (data slicer), a data decision (data decision) circuit, etc. to determine the amplitude of the equalized input signal EIS to decide the content of the data.
Theclock recovery circuit 130 is configured to perform clock recovery according to the equalized input signal EIS, thereby reconstructing a clock signal used by the signal transmitting end to transmit the signal. In an embodiment, theclock recovery circuit 130 performs frequency extraction (frequency extraction) on the equalized input signal EIS in units of time windows based on the Mueller-muller clock recovery technique, and determines a phase difference between the equalized input signal EIS and the clock signal at the transmitting end to generate the adjustment signal CON to theclock generation circuit 140 to adjust the internal clock signal CLK, so that the frequency of the internal clock signal CLK approaches the frequency of the clock signal at the transmitting end.
In addition, in some embodiments, theclock recovery circuit 130 accumulates at least one phase offset amount of the phase detection unit, and when an absolute value of the accumulated phase offset amount is greater than a predetermined value, theclock recovery circuit 130 sends the adjustment signal CON to theclock generation circuit 140 to adjust the phase of the internal clock signal CLK.
Refer to fig. 2. Fig. 2 is a diagram of a time window TW according to an embodiment of the invention.
As shown in FIG. 2, time window TW includes a plurality of sub-time windows SW1～SWn. In one embodiment, the sub-time windows SW1～SWnEach having a time duration of at least one hundred times the unit time of phase detection of the Mueller-muller clock recovery technique. In one example, the phase detection unit time of the Mueller-muller clock recovery technique is, for example, but not limited to, 5 nanoseconds (nsecond) in length, so that the phase detection is performed in each phase detection unit time and the phase is adjusted accordingly.
It should be noted that the above values are only examples. In other embodiments, the sub-time windows SW1～SWnIt can be any value more than one hundred times the unit time of phase detection. Thus, in one embodiment, the sub-time windows SW1～SWnEach having a length of, for example, but not limited to, 5 microseconds (microsecond), which is one thousand times the phase detection unit time of the Mueller-muller clock recovery technique.
In one embodiment, time window TW contains, for example, but not limited to, 8 sub-time windows SW1～SWn(i.e., n is 8), so time window TW is, for example, but not limited to, 40 microseconds in length.
In one embodiment, theclock recovery circuit 130 operates on the equalized input signal EIS to adjust the phase of the internal clock signal CLK, and the phase difference of the zero-order term and the one-order term can be observed from the phase change of the equalized input signal EIS with time. The zero-order term is a phase term, such as, but not limited to, a phase difference generated by the transmission channel being affected by temperature. The first term is a frequency term, such as, but not limited to, a frequency difference between clock signals respectively operated by thesignal receiving apparatus 100 and the corresponding signal transmitting terminals.
In one embodiment, the frequency offset caused by the frequency term (primary term) requires a long time to extract the frequency term actually belonging between thesignal receiving apparatus 100 and the corresponding signal transmitting end. Therefore, theclock recovery circuit 130 is configured to count all sub-time windows SW for the equalized input signal EIS in units of a longer time window TW1～SWnThe respective phase offsets (referred to as phase offset information) are extracted by frequency extraction, and then an adjustment signal CON is generated to theclock generation circuit 140, so as to adjust the frequency of the internal clock signal CLK, thereby eliminating the difference of the first term.
On the other hand, the phase shift caused by the phase term (zero-order term) needs to be counted in a shorter time for real-time adjustment, for example, theclock recovery circuit 130 accumulates the phase shift of at least one phase detection unit, and when the absolute value of the accumulated phase shift is greater than a predetermined value, theclock recovery circuit 130 sends the adjustment signal CON to theclock generation circuit 140 to adjust the phase of the internal clock signal CLK.
Thus, theclock recovery circuit 130 is configured to recover the clock during the sub-time window SW1～SWnAnd judging the signal interference parameter of any sub-time window. In some embodiments, for the purpose of rf interference rejection, thephase calculation circuit 135A generates the adjustment signal CON to adjust the phase of the internal clock signal CLK according to the phase offset within the sub-time window only when the signal interference parameter is smaller than the threshold value, so as to eliminate the difference of the zero-order term. The phase offset is also counted by thefrequency extraction circuit 135B, and theclock recovery circuit 130 further generates the adjustment signal CON to adjust the internal circuitThe frequency of the clock signal CLK. In some embodiments, the phase is based on instantaneous changes and then caused to be included in the statistics, so that in practice, theclock recovery circuit 130 can selectively return the adjusted phase to the previous time point.
In practical operation, in one embodiment, theclock recovery circuit 130 may include different circuit blocks to implement thephase calculation circuit 135A and thefrequency extraction circuit 135B. Thephase calculation circuit 135A is configured to calculate the equalized input signal EIS to pick up the phase IP, and thefrequency extraction circuit 135B counts phase offset information in units of time windows according to the phase IP, and performs frequency extraction on the equalized input signal EIS, where the phase offset information includes a plurality of phase offsets, and the plurality of phase offsets correspond to the plurality of sub-time windows, respectively.
Further, thefrequency extraction circuit 135B determines the signal interference parameter for each sub-time window and generates the adjustment signal CON to adjust the frequency of the internal clock signal CLK. In one embodiment, the amount of phase shift has directivity and may be represented by positive or negative values, one of which represents phase lead and the other phase lag.
In one embodiment, the sir parameter for a sub-time window may be a difference between a phase offset of the sub-time window and a phase offset of a previous or subsequent sub-time window. In an embodiment, the signal interference parameter of a sub-time window may be a difference between a signal-to-noise ratio of the sub-time window and a preset signal-to-noise ratio, where the preset signal-to-noise ratio may be a signal-to-noise ratio of a previous sub-time window, a signal-to-noise ratio of a next sub-time window, or an average signal-to-noise ratio of the time window.
In an operation scenario, when thesignal receiving apparatus 100 is in operation, an intercom or other device may emit radio frequency interference through the intercom or other device, which may cause instantaneous large amplitude oscillation of the equalized input signal EIS, so that theclock recovery circuit 130 may detect a large phase offset in the corresponding sub-time window. Without an effective coping mechanism, theclock recovery circuit 130 cannot obtain the true frequency offset between thesignal receiving apparatus 100 and the corresponding signal transmitting end, and may cause a system crash.
Therefore, when the signal interference parameter is greater than the threshold, theclock recovery circuit 130 determines that the radio frequency interference phenomenon is detected in the sub-time window at the time. Theclock recovery circuit 130 further discards the phase offset in the sub-time window where the radio frequency interference occurs, rather than adjusting the frequency of the internal clock signal CLK, so as to eliminate the erroneous determination caused by the radio frequency interference.
In some embodiments, the phase is changed before the statistics are included, so that in actual operation, when the radio frequency interference phenomenon occurs in one sub-time window, theclock recovery circuit 130 can selectively return the adjusted phase to the previous time point, for example, theclock recovery circuit 130 can adjust the phase back according to the phase adjustment amount of the sub-time window in the next sub-time window.
On the other hand, when the radio frequency interference phenomenon is not detected, theclock recovery circuit 130 may generate the adjustment signal CON according to the magnitude and the directionality of the phase offset to adjust the phase of the internal clock signal CLK, so as to achieve the effect of clock recovery.
In some techniques, since the clock recovery technique employed by the signal receiving apparatus determines the phase shift information according to each minute phase detection unit time and adjusts the information at any time, the error determination is likely to occur when the radio frequency interference phenomenon occurs, which deviates from the actual clock frequency of the signal transmitting end, and even causes system breakdown due to chain reaction.
In contrast, the signal receiving apparatus of the present invention can pick up the phase offset information in a longer time window, thereby reducing frequent and susceptible phase detection, and by determining the signal interference parameter, the corresponding phase offset is discarded when the radio frequency interference occurs, and the phase of the clock signal is not adjusted accordingly. Not only does not affect frequency extraction because only discarding the phase offset of part of the sub-time windows in a longer time window, but also can avoid misjudgment caused by radio frequency interference.
Refer to fig. 3. Fig. 3 is a flowchart of asignal receiving method 300 according to an embodiment of the present invention.
In addition to the foregoing devices, the present invention further provides asignal receiving method 300, which is applied to, for example, but not limited to, thesignal receiving device 100 of fig. 1. One embodiment of asignal receiving method 300 is shown in fig. 3, comprising the following steps:
step S310: the analog-to-digital conversion circuit 110 is caused to perform analog-to-digital conversion on the input analog signal IAS from the transmission channel in accordance with the internal clock signal CLK to generate an input digital signal IDS.
Step S320: the equalizingcircuit 120 is caused to equalize the input digital signal IDS to produce an equalized input signal EIS.
Step S330: theclock recovery circuit 130 is caused to operate on the equalized input signal EIS to adjust the phase of the internal clock signal CLK.
Step S340: causing theclock recovery circuit 130 to count the phase offset information in units of a time window (e.g., the time window TW shown in fig. 2) to perform frequency extraction on the equalized input signal EIS; the phase offset information comprises a plurality of phase offsets, the time window comprises a plurality of sub-time windows, and the phase offsets respectively correspond to the sub-time windows.
Step S350: cause theclock recovery circuit 130 to determine the sub-time window (e.g., the sub-time window SW shown in FIG. 2)1～SWn) A signal interference parameter of one of the plurality of signal interference parameters.
Step S360: causing theclock recovery circuit 130 to determine whether the signal interference parameter is greater than a threshold; if so, the process proceeds to step S370, otherwise, the process proceeds to step S380.
Step S370: and when the signal interference parameter is larger than the threshold value, enabling the clock recovery circuit to discard the corresponding phase offset from the plurality of phase offsets so as to generate updated phase offset information.
Step S380: when the signal interference parameter is smaller than the threshold, theclock recovery circuit 130 generates the adjustment signal CON according to the phase offset information or the updated phase offset information to adjust the frequency of the internal clock signal CLK.
The steps of the receivingmethod 300 are merely exemplary, and need not be executed in the order in this example. The various operations of the receivingmethod 300 may be added, substituted, omitted, or performed in a different order, as appropriate, without departing from the manner of operation and scope of various embodiments of the present invention. It should be noted that the above-mentioned embodiment is only an example. In other embodiments, modifications can be made by one of ordinary skill in the art without departing from the spirit of the invention.
In summary, the signal receiving apparatus and method with an anti-radio frequency interference mechanism of the present invention can perform phase offset information pickup in a longer time window, reduce frequent and easily affected phase detection, and discard the corresponding phase offset information when the radio frequency interference phenomenon occurs by determining the signal interference parameters, thereby avoiding misjudgment caused by radio frequency interference.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply changes to the technical features of the present invention according to the explicit or implicit contents of the present invention, and these changes may all fall into the scope of the present invention, in other words, the scope of the present invention should be limited by the claims of the present specification.
[ description of reference ]
100 signal receiving apparatus
110A/D converter circuit
120 equalization circuit
130 clock recovery circuit
135A phase calculation circuit
135B frequency extraction circuit
140 clock generation circuit
150 data signal processing circuit
300 signal receiving method
S310 to S380 steps
CLK internal clock signal
CON adjustment signal
EIS equalized input signal
IAS input analog signal
IDS input digital signal
SW1～SWnSub-time windows
TW time window
Claims (10)
1. A signal receiving apparatus with an anti-radio frequency interference mechanism, comprising:
an analog-to-digital conversion circuit configured to perform analog-to-digital conversion on an input analog signal according to an internal clock signal to generate an input digital signal;
an equalization circuit configured to equalize the input digital signal to produce an equalized input signal; and
a clock recovery circuit configured to operate on the equalized input signal to adjust a phase of the internal clock signal, and count a phase offset information in units of a time window to perform frequency extraction on the equalized input signal, wherein the phase offset information includes a plurality of phase offsets, the time window includes a plurality of sub-time windows, and the plurality of phase offsets correspond to the plurality of sub-time windows;
wherein the clock recovery circuit is further configured to determine a signal interference parameter of one of the plurality of sub-time windows, and discard phase offsets corresponding to the plurality of sub-time windows from the plurality of phase offsets when the signal interference parameter is greater than a threshold value to generate updated phase offset information;
the clock recovery circuit generates an adjusting signal according to the updated phase offset information to adjust the frequency of the internal clock signal.
2. The signal receiving apparatus of claim 1, wherein the sir parameter is a difference between a phase offset of one of the plurality of sub-time windows and a phase offset of a previous or a subsequent sub-time window.
3. The signal receiving apparatus of claim 1, wherein the signal interference parameter is a difference between a signal-to-noise ratio of one of the sub-time windows and a predetermined signal-to-noise ratio.
4. The signal receiving apparatus of claim 3, wherein the predetermined SNR is an SNR of a previous sub-time window, an SNR of a next sub-time window, or an average SNR of the time windows.
5. The signal receiving device of claim 1, wherein each of the plurality of sub-time windows has a time duration at least one hundred times a phase detection unit time of a Mueller-muller clock recovery technique.
6. The signal receiving apparatus of claim 1, wherein the clock recovery circuit generates the adjustment signal to adjust the frequency of the internal clock signal according to the phase offset information when the signal interference parameter of each of the plurality of sub-time windows is smaller than the threshold value.
7. A signal receiving method with anti-radio frequency interference mechanism is applied to a signal receiving device and comprises the following steps:
an analog-to-digital conversion circuit performs analog-to-digital conversion on an input analog signal according to an internal clock signal to generate an input digital signal;
equalizing the input digital signal by an equalizing circuit to generate an equalized input signal;
enabling a clock recovery circuit to operate on the equalized input signal to adjust a phase of the internal clock signal, and counting phase offset information in units of a time window to perform frequency extraction on the equalized input signal, wherein the phase offset information includes a plurality of phase offsets, the time window includes a plurality of sub-time windows, and the plurality of phase offsets correspond to the plurality of sub-time windows;
enabling the clock recovery circuit to judge a signal interference parameter of one of the plurality of sub-time windows, and when the signal interference parameter is greater than a threshold value, discarding the corresponding phase offset of the plurality of corresponding sub-time windows from the plurality of phase offsets to generate updated phase offset information; and
and enabling the clock recovery circuit to generate an adjusting signal according to the updated phase offset information so as to adjust the frequency of the internal clock signal.
8. The signal receiving method of claim 7, wherein the sir parameter is a difference between a phase offset of one of the sub-time windows and a phase offset of a previous or a subsequent sub-time window.
9. The signal receiving method as claimed in claim 7, wherein the signal interference parameter is a difference between the signal-to-noise ratio of one of the sub-time windows and a predetermined signal-to-noise ratio.
10. The signal receiving method according to claim 7, further comprising:
and when each signal interference parameter of the plurality of sub-time windows is smaller than the threshold value, the clock recovery circuit generates the adjusting signal according to the phase offset information so as to adjust the frequency of the internal clock signal.
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