CN113394964A - Control circuit and PFC circuit applying same - Google Patents
Control circuit and PFC circuit applying sameDownload PDFInfo
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- CN113394964A CN113394964ACN202110659531.1ACN202110659531ACN113394964ACN 113394964 ACN113394964 ACN 113394964ACN 202110659531 ACN202110659531 ACN 202110659531ACN 113394964 ACN113394964 ACN 113394964A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
- H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
- H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
Technical Field
The present invention relates to power electronics technologies, and in particular, to a control circuit and a PFC circuit using the same.
Background
Among various drivers, PF (power factor) is an important energy saving index, which not only affects the conversion efficiency of the driver, but also pollutes the power grid of the whole power supply system when the power factor is low, and thus, the demand for a PFC circuit (power factor correction circuit) is higher and higher.
FIG. 1 is a waveform diagram illustrating the operation of a conventional PFC circuit, in which the PFC circuit operates in a manner such that an output voltage V is providedBUSSet value V ofBUS,REFVery high, no matter input voltage VINThe amplitude is high and low, the PFC circuit is continuously operated, and the operation mode causes low system efficiency, especially at the input voltage VINWhen the voltage is lower, the loss is very obvious because the boosting ratio of the power level circuit is too high and the duty ratio is very large; and in order to reduce the output voltage VBUSThe ripple of the output capacitor is also larger, which results in an oversized system.
Disclosure of Invention
In view of this, the present invention provides a control circuit and a PFC circuit using the same, so as to solve the problems of large loss and large volume of the conventional PFC circuit system.
In a first aspect, a control circuit is provided, which is applied in a PFC circuit, the PFC circuit further includes a power stage circuit, the PFC circuit converts an ac input voltage into a dc bus voltage and outputs the dc bus voltage,
the control circuit controls the enabling state of the power stage circuit in a power frequency period according to the amplitude of the alternating current input voltage, so that the efficiency of the PFC circuit is improved.
Preferably, the control circuit controls the power stage circuit to be enabled to be in an operating state when the amplitude of the alternating input voltage is low; is not enabled to be in a rest state when the amplitude of the ac input voltage is high.
Preferably, the control circuit controls the power stage circuit to be always in a working state in a power frequency cycle when the peak value of the alternating current input voltage is in the first state so that the direct current bus voltage is always smaller than the overvoltage threshold value.
Preferably, the control circuit controls the power stage circuit to be always in a stop state in one power frequency cycle when the peak value of the ac input voltage is in the second state so that the dc bus voltage is always greater than the expected value of the dc bus voltage.
Preferably, the control circuit controls the power stage circuit to be in an alternately working state and a working stop state in a power frequency period when the peak value of the alternating input voltage is between a first state and a second state.
Preferably, the control circuit detects the magnitude of the input ac voltage by obtaining the magnitude of the dc bus voltage.
Preferably, the control circuit determines the enabling state of the power stage circuit in a power frequency cycle according to a comparison result between the dc bus voltage and an overvoltage threshold value representing overvoltage of the dc bus voltage and/or an expected value of the dc bus voltage.
Preferably, the control circuit controls the power stage circuit not to be enabled to be in a stop working state when the direct current bus voltage is greater than the overvoltage threshold value; and the power stage circuit is enabled to be in an operating state when the dc bus voltage is less than the desired value.
Preferably, the dc bus voltage is enabled to be in an operating state when the dc bus voltage is greater than the desired value and not greater than the overvoltage threshold, and the dc bus voltage is brought into a shutdown state when the dc bus voltage is greater than the overvoltage threshold until the dc bus voltage is less than the desired value.
Preferably, the desired value is not greater than a peak value at which the ac input voltage is at a maximum.
Preferably, the output end of the power stage circuit is provided with a direct current bus capacitor, and the capacitance value of the direct current bus capacitor is set to enable the direct current bus voltage to be still larger than the requirement of the expected value when the load is fully loaded.
Preferably, the control circuit comprises an enable circuit, the enable circuit comprising:
a first comparator, wherein a non-inverting input end of the first comparator receives the expected value, an inverting input end of the first comparator receives the direct current bus voltage or a sampling signal representing the direct current bus voltage, and an output end of the first comparator outputs a first comparison signal;
a second comparator, wherein a non-inverting input end of the second comparator receives the direct-current bus voltage or a sampling signal representing the direct-current bus voltage, an inverting input end of the second comparator receives the overvoltage threshold, and an output end of the second comparator outputs a second comparison signal;
a logic circuit that sets an enable signal when the first comparison signal is active; and resetting the enable signal when the second comparison signal is valid, wherein the enable signal is used for controlling the enable state of the power stage circuit.
Preferably, the control circuit further includes a driving circuit, the driving circuit is configured to convert a switch control signal for controlling a power switch in the power stage circuit into a driving signal, and the enable signal controls an enable state of the power stage circuit by controlling an enable state of the driving circuit.
Preferably, the control circuit further includes a switch control signal generating circuit, the switch control signal generating circuit generates a switch control signal according to the dc bus voltage, the desired value and a switch current sampling signal in the power stage circuit, and the switch control signal is used to control the switching state of the power switch in the power stage circuit, so that the dc bus voltage is maintained at the desired value and the power factor of the PFC circuit meets the operating requirement.
Preferably, the power stage circuit operates in a constant peak current mode.
Preferably, when the power stage circuit is in the stop operation state, the power stage circuit provides a through path, and the dc input voltage obtained by filtering the ac input voltage is directly transmitted to the output terminal of the power stage circuit to be used as the dc bus voltage.
Preferably, when the power stage circuit is in the operating state, a power switch in the power stage circuit is controlled to switch the state of the switch, and the dc input voltage obtained after the ac input voltage filtering is boosted to obtain the desired dc bus voltage.
Preferably, the capacitance value of the dc bus capacitor is set such that the power stage circuit is always in a stop state in a power frequency cycle when the amplitude of the ac input voltage is greater than a predetermined value.
In a second aspect, a PFC circuit is provided, including:
a power stage circuit, and,
the control circuit is described above.
The technology of the invention enables the power level circuit in the PFC circuit to be in a working state when the amplitude of the alternating current input voltage is lower; when the amplitude of the alternating-current input voltage is high, the alternating-current input voltage is not enabled to be in a stop working state, so that the PFC circuit can improve the overall efficiency of a system, and the capacity of an output capacitor is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a waveform diagram illustrating the operation of a conventional PFC circuit;
fig. 2 is a circuit configuration diagram of a PFC circuit according to a first embodiment of the present invention;
fig. 3 is a circuit configuration diagram of a PFC circuit according to a second embodiment of the present invention;
fig. 4a is a waveform diagram of the operation of the PFC circuit according to the second embodiment;
fig. 4b is another waveform diagram illustrating the operation of the PFC circuit according to the second embodiment;
fig. 4c is a diagram of another operating waveform of the PFC circuit according to the second embodiment.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
Fig. 2 is a circuit diagram of a PFC circuit according to a first embodiment of the present invention. As shown in fig. 2, the PFC circuit includes arectifier circuit 21, apower stage circuit 22, and acontrol circuit 23.
Specifically, the rectifyingcircuit 21 receives an AC input voltage AC, rectifies it, and outputs a dc input voltage VIN. Therectifier circuit 21 may be a full bridge type rectifier bridge or a half bridge type rectifier bridge. The output of therectifier circuit 21 may be equivalent to a dc voltage source.
Thepower stage circuit 22 includes an inductor (or a transformer), a power switch, a diode, and the like, and directly receives the dc input voltage V output by the rectifying circuitINAnd the input current and the input voltage waveform of the power stage circuit are basically consistent and the output voltage is basically constant through the control of the conducting state of the power switch. Here, thepower stage circuit 22 is a boost topology, and thepower stage circuit 22 includes an inductor L1 connected at an input terminal thereof, a main power switch Q1 coupled to the inductor L1, a diode D coupled to a common terminal of the inductor L1 and the main power switch Q1, and a dc bus capacitor C connected at an output terminal thereofBUSTo the DC bus capacitor CBUSGenerates a DC bus voltage V at both endsBUS. DC bus voltage VBUSAsThe input voltage of the subsequent converter to provide energy to the load.
Thecontrol circuit 23 generates a switch control signal to control the on/off state of the power switch in thepower stage circuit 22 according to the feedback signals of the voltage and the current in thepower stage circuit 22, so that the dc bus voltage V is obtainedBUSIs maintained at the desired value VBUS,REGIn addition, thecontrol circuit 23 controls whether the switch control signal acts on the power switch in thepower stage circuit 22 according to the amplitude of the AC input voltage AC, so as to control the enabling state of thepower stage circuit 22 in a power frequency cycle, and improve the efficiency of the PFC circuit.
Specifically, thecontrol circuit 23 controls thepower stage circuit 22 to be enabled to be in an operating state when the amplitude of the alternating input voltage AC is low; is not enabled to be in a deactivated state when the amplitude of the alternating input voltage AC is high.
Further, thecontrol circuit 23 is based on the DC bus voltage VBUSAnd an overvoltage threshold V for representing overvoltage of direct current bus voltageBUS,OVPAnd the desired value V of the DC bus voltageBUS,REGDetermines the enable state of thepower stage circuit 22 during a power frequency cycle. Further, thecontrol circuit 23 controls thepower stage circuit 22 to control the DC bus voltage VBUSGreater than the overvoltage threshold VBUS,OVPIs not enabled to be in a stop working state; and at thepower stage circuit 22 at the DC bus voltage VBUSLess than desired value VBUS,REGIs enabled to be in an operating state.
In addition, in the present invention, since thepower stage circuit 22 is not operated at all periods in one power frequency cycle, but is operated only when the amplitude of the AC input voltage AC is low, the dc bus voltage V is set to be lower than the AC input voltage ACBUSIs expected value VBUS,REGNot necessarily higher than the maximum value of the peak value of the AC input voltage AC, but may be chosen to have a lower desired value V than in the prior artBUS,REG。
It should be noted that thecontrol circuit 23 can directly obtain the dc bus voltage VBUSCan also obtain the real value of the characterization direct current bus voltage VBUSBy comparing the actual value or sampled value with an overvoltage threshold value VBUS,OVPAnd an expected value VBUS,REGAnd determining the enabling state of the power stage circuit in a power frequency period.
It should be noted that when thepower stage circuit 22 is not enabled and is in the off state, it means that thepower stage circuit 22 provides a through path in a through state to supply the dc input voltage VINIs directly transmitted to the output end of thepower stage circuit 22 to be used as a direct current bus voltage VBUS(ii) a When thepower stage circuit 22 is enabled and thus in the working state, it means that thepower stage circuit 22 is in the PWM state, and the power switch is controlled by the switch control signal to switch the switch state, so as to input the dc input voltage VINBoosting to obtain a DC bus voltage VBUSAnd make the DC bus voltage VBUSIs maintained at the desired value VBUS,REGNearby.
It should be noted that the circuit of the PFC circuit of the first embodiment is described by taking a conventional PFC circuit structure with therectifier circuit 21 as an example, however, in some bridgeless PFC circuits, the structures of the rectifier bridge and the converter are combined together, and the power stage circuit in the PFC circuit can directly process the AC input voltage AC, and in this case, a separate rectifier circuit is not needed.
To this end, the technology of the present invention enables a power stage circuit in a PFC circuit to be in a working state when the amplitude of an alternating input voltage AC is low; is not enabled to be in a stop working state when the amplitude of the AC input voltage AC is high, thereby leading the DC bus voltage VBUSIs expected value VBUS,REGA lower value can be chosen. In this operating mode, on the one hand, the power stage circuit is enabled to be in operation when the amplitude of the alternating input voltage AC is low, due to the desired value VBUS,REGThe duty ratio of the power level circuit is correspondingly reduced due to the fact that the duty ratio is relatively low, and therefore the working efficiency of the power level circuit is improved; on the other hand, when the amplitude of the AC input voltage AC is high, the AC input voltage AC is not enabled to be in a stop working state, and the power stage circuit provides a through path to supply the DC input voltage VINIs transmitted to the output end of the power stage circuit to be used as a direct current bus voltage VBUSIn this process, since there is no switching operation in the power stage circuit, the switching loss is reduced, and the PFC circuit according to the present invention can improve the overall system efficiency by combining the above two reasons.
Fig. 3 is a circuit diagram of a PFC circuit according to a second embodiment of the invention. The difference between the first embodiment and the second embodiment is that a specific structure of thecontrol circuit 33 is disclosed, and other parts of the circuit, such as the rectifyingcircuit 31 and thepower stage circuit 32, are the same as the circuit structures and operating principles of the rectifyingcircuit 21 and thepower stage circuit 22 in the first embodiment, and are not described herein again.
Thecontrol circuit 33 is arranged to control the peak value of the AC input voltage AC to be substantially lower than the desired value V of the dc bus voltageBUS,REGIn the first state, thepower stage circuit 32 is controlled to be in a working state all the time in a power frequency period; thecontrol circuit 33 is arranged to control the peak value of the AC input voltage AC to be significantly higher than the desired value V of the dc bus voltageBUS,REGIn the second state, thepower stage circuit 32 is controlled to be in a work-stop state all the time in a power frequency period; thecontrol circuit 33 controls thepower stage circuit 32 to alternately operate and stop operating in one power frequency cycle when the peak value of the AC input voltage AC is between the first state and the second state.
Preferably, thecontrol circuit 33 includes an enablecircuit 331, a switch controlsignal generation circuit 332, and adrive circuit 333.
Specifically, the enablingcircuit 331 obtains the dc bus voltage VBUSTo detect the amplitude of the input AC voltage AC and further to convert the DC bus voltage VBUSOr its sampled value and expected value VBUS,REGAnd an overvoltage threshold VBUS,OVPThe comparison results in the enable signal EN to control the enable state of thepower stage circuit 32.
In the embodiment of the present invention, the enablecircuit 331 includes: a first comparator CMP1, the non-inverting input of which receives the desired value VBUS,REGAnd the inverting input terminal receives the DC bus voltage VBUSOr to characterize the DC bus voltage VBUSIs sampled signal VSAMIn the embodiment of the invention, the direct-current bus voltage V is selected to be representedBUSIs sampled signal VSAMThe sampling signal V is connected into the inverting input terminal of the first comparator CMP1SAMThe DC bus voltage V is divided by a voltage dividing circuit formed by two resistors connected in seriesBUSObtained after a certain proportion of voltage division to match with other parameters in the circuit, and the switch controlsignal generating circuit 332 in thecontrol circuit 33 also needs to generate the voltage V according to the DC busBUSOr to characterize the DC bus voltage VBUSIs sampled signal VSAMGenerating a switching control signal, so that here the sampling signal VSAMCan be provided for multiplexing in a two-part circuit module. The output terminal of the first comparator CMP1 outputs a first comparison signal V1; a second comparator CMP2 having a non-inverting input receiving the DC bus voltage VBUSOr to characterize the DC bus voltage VBUSIs also chosen here to be characteristic of the dc bus voltage VBUSIs sampled signal VSAMA non-inverting input of a second comparator CMP2 is connected, the inverting input of which receives the overvoltage threshold VBUS,OVPThe output end outputs a second comparison signal V2; the logic circuit, here an SR flip-flop, has a set terminal S receiving the first comparison signal V1, sets the enable signal EN when the first comparison signal V1 is active, has a reset terminal R receiving the second comparison signal V2, resets the enable signal EN when the second comparison signal V2 is active, outputs the enable signal EN at an output terminal Q of the SR flip-flop, and the enable signal EN is used to control the enable state of thepower stage circuit 32.
Thecontrol circuit 33 further includes a switch controlsignal generating circuit 332, and the switch controlsignal generating circuit 332 generates the switch control signal according to the dc bus voltage VBUSExpected value VBUS,REGAnd a switching current sampling signal V in thepower stage circuit 32IGenerating a switch control signal VQTo control the switching state of the power switch in thepower stage circuit 32, here, since the rectifying power switch in the boost converter is the diode D, the main power switch Q1 is specifically controlled to make the dc bus voltage VBUSMaintained at the characteristic DC bus voltage VBUSIs expected to be of the amplitude VBUS,REGAnd the input current and the input voltage waveform of thepower stage circuit 32 are made to be substantially consistent, that is, the power factor PF of the PFC circuit meets the operating requirement. In the present embodiment, the current through the main power switch Q1 is sampled using a resistor connected between the main power switch Q1 and ground reference to obtain a switch current sample signal VI。
In an embodiment of the present invention, thepower stage circuit 32 operates in a constant peak current mode. The switch controlsignal generating circuit 332 includes an error amplifier EA having an input representing the DC bus voltage VBUSIs sampled signal VSAMAnd an expected value VBUS,REGOutput error compensation signal VCWherein the output terminal of the error amplifier EA has a compensation capacitor VC. In the present embodiment, the sampling signal VSAMInput to the inverting input of the error amplifier EA at a desired value VBUS,REGTo the non-inverting input of the error amplifier EA. The switch controlsignal generating circuit 332 further includes a comparator CMP3 for comparing the error compensation signal VCAnd a switching current sampling signal VIAnd outputs a switch control signal VQReset signal V of resetRIn the present embodiment, the error compensation signal VCThe switching current sampling signal V is input to the inverting input terminal of the comparator CMP3ITo the non-inverting input of comparator CMP 3. The circuit structure can enable the switch current to sample the signal VITo achieve an error compensation signal VCWhen this occurs, the main power switch Q1 is turned off, thereby maintaining the peak value of the switch current near the error compensation signal. So that the switch control signal VQSet signal V of settingSMay be a clock signal or a set signal V generated by other control methods for settingSSet signal VSAnd a reset signal VRRespectively connected to the set terminal S and the reset terminal R of the SR flip-flop to generate a switch control signal V at the output terminal Q thereofQ. Of course, it will be appreciated by those skilled in the art that in other embodiments, the switching current may be variedMay be sinusoidal in form.
Thecontrol circuit 33 further includes adriving circuit 333, the drivingcircuit 333 is used to control the switch control signal V for controlling the power switch of thepower stage circuit 32QConverted into a drive signal VQ1The enable signal EN generated by theenable circuit 331 controls the enable state of thepower stage circuit 32 by controlling the enable state of the drivingcircuit 333. That is, when the enable signal EN is active, thedrive circuit 333 is enabled and outputs the drive signal VQ1(ii) a When the enable signal EN is inactive, thedrive circuit 333 is not enabled and does not output the drive signal VQ1Thereby enabling the PFC circuit to control the signal V by controlling the switch according to the amplitude of the input voltage ACQWhether to act on the main power switch Q1 in thepower stage circuit 32 to control the enabling state of thepower stage circuit 32 during a power frequency cycle, so that the efficiency of the PFC circuit is improved. It should be understood that the control switch control signal VQThe enable signal EN may be applied to the control switch control signal V, instead of applying it to the main power switch Q1 in thepower stage circuit 32 in more than one wayQI.e. when the enable signal EN is active, the switch control signal VQNormally passes to thedrive circuit 333, and makes the switch control signal V inactive when the enable signal EN is inactiveQAre all disabled so that the drivingcircuit 333 outputs the disabled driving signal VQ1The power switches in thepower stage circuit 32 are also made inoperative.
Further, a DC bus capacitor C is arranged at the output end of thepower stage circuit 32BUSDC bus capacitor CBUSThe setting of the capacitance value needs to meet the requirement of the DC bus voltage V when the load is fully loadedBUSIs still greater than the desired value VBUS,REGAnd at a predetermined input voltage VACRNext, the PFC circuit is completely inoperative, where the input voltage V isACRIs an effective value of the AC input voltage AC, TACIs the power frequency cycle.
In a toolIn bulk applications, the output power is assumed to be 120W, VBUS,REGIs 250V and has an effective value V of the AC input voltage ACACRIn order to make the power stage circuit not work when the voltage is more than 210V, in the scheme of the invention, the direct current bus capacitor CBUSHas a capacitance value of 19uF, whereas in the prior art solution the dc bus capacitance C isBUSThe capacity of (A) is approximately between 100uF and 120 uF. Therefore, the technical scheme of the invention not only can improve the overall efficiency of the PFC circuit, but also can reduce the capacity of the output capacitor.
Fig. 4a is a waveform diagram illustrating the operation of the PFC circuit according to the second embodiment when the AC input voltage AC is low; FIG. 4b shows the PFC circuit of the second embodiment when the AC input voltage AC approaches the DC bus voltage VBUSA working waveform map at a desired amplitude; fig. 4c is a waveform diagram of the operation of the PFC circuit according to the second embodiment when the AC input voltage AC is high. The working principle of the PFC circuit of the present invention is explained below with reference to the working waveform diagram:
as shown in fig. 4a, when the peak value of the AC input voltage AC is lower than the desired value VBUS,REGTime, i.e. the DC input voltage VINIs lower than the desired value VBUS,REGTime, DC bus voltage VBUSNot higher than the overvoltage threshold VBUS,OVPTherefore, thepower stage circuit 32 is always enabled during a power frequency cycle. At the moment, the boost converter works continuously, works in a constant peak current control mode, and also can work in a sinusoidal current envelope mode of the traditional PFC. Voltage threshold V of the output voltage of a simultaneous boost converterBUS,REGI.e. the desired value VBUS,REGThe setting is low, the peak value higher than the highest alternating input voltage AC does not need to be considered, so that the boost ratio of the boost converter is much lower than that of the boost converter in the common PFC circuit, and the boost converter has higher efficiency when the alternating input voltage AC is low;
as shown in fig. 4b, when the peak value of the AC input voltage AC approaches the desired value VBUS,REGTime, i.e. the DC input voltage VINIs close to the desired value VBUS,REGTime, DC bus voltage VBUSWill be between the expected values VBUS,REGAnd an overvoltage threshold VBUS,OVPAnd thus thepower stage circuit 32 is in an intermittent operation during a power frequency cycle. When the DC input voltage VINWhen near the valley, the boost converter is always working when the DC input voltage VINWhen rising, the DC bus capacitor CBUSSmall and slow control loop, dc bus voltage VBUSWill also continue to rise above the desired value VBUS,REG. Furthermore, if the DC bus voltage VBUSExceeding the overvoltage threshold VBUS,OVPWhen the boost converter stops the switch operation until the DC bus voltage VBUSIs again lower than the desired value VBUS,REGUntil now.
When the peak value of the AC input voltage AC is higher than the desired value V, as shown in fig. 4cBUS,REGAt a certain threshold, i.e. DC input voltage VINIs higher than the desired value VBUS,REGTime and DC bus voltage VBUSIs also higher than the desired value VBUS,REGTime, i.e. dc bus voltage VBUSNot lower than desired value VBUS,REGTherefore, thepower stage circuit 32 is always in the disabled state during a power frequency cycle, i.e. the entire power frequency cycle boost converter does not work. Therefore, automatic transition to a non-working state is realized, high efficiency is realized when the alternating input voltage AC is high, and the output end of the power stage circuit is allowed to have large ripple waves, so that compared with the traditional PFC circuit, the capacitance value of an output capacitor required by the PFC circuit is smaller, and the capacity and the volume of the output capacitor of the power stage circuit are also reduced.
In summary, the present invention enables the power stage circuit in the PFC circuit to be in the working state when the amplitude of the AC input voltage AC is low; when the amplitude of the alternating input voltage AC is high, the alternating input voltage AC is not enabled to be in a stop working state, so that the PFC circuit can improve the overall efficiency of a system and reduce the capacity of an output capacitor.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (19)
1. A control circuit is applied to a PFC circuit, the PFC circuit also comprises a power stage circuit, the PFC circuit converts an alternating current input voltage into a direct current bus voltage and outputs the direct current bus voltage,
the control circuit controls the enabling state of the power stage circuit in a power frequency period according to the amplitude of the alternating current input voltage, so that the efficiency of the PFC circuit is improved.
2. The control circuit of claim 1, wherein the control circuit controls the power stage circuit to be enabled to be in an operating state when the amplitude of the ac input voltage is low; is not enabled to be in a rest state when the amplitude of the ac input voltage is high.
3. The control circuit of claim 1, wherein the control circuit controls the power stage circuit to be in an operating state for a power frequency cycle when a peak value of the ac input voltage is in a first state such that the dc bus voltage is always less than the over-voltage threshold.
4. The control circuit of claim 1, wherein the control circuit controls the power stage circuit to remain inactive for a power frequency cycle when the peak value of the ac input voltage is in the second state such that the dc bus voltage is always greater than the desired value of the dc bus voltage.
5. The control circuit of claim 1, wherein the control circuit controls the power stage circuit to alternately operate and deactivate during a power frequency cycle when a peak value of the ac input voltage is between a first state and a second state.
6. The control circuit of claim 5, wherein the control circuit detects the magnitude of the input AC voltage by obtaining the magnitude of the DC bus voltage.
7. The control circuit of claim 1, wherein the control circuit determines the enable state of the power stage circuit during a power frequency cycle based on a comparison of the dc bus voltage to an over-voltage threshold indicative of an over-voltage of the dc bus voltage and/or a desired value of the dc bus voltage.
8. The control circuit of claim 7, wherein the control circuit controls the power stage circuit to be disabled when the dc bus voltage is greater than the over-voltage threshold; and the power stage circuit is enabled to be in an operating state when the dc bus voltage is less than the desired value.
9. The control circuit of claim 7, wherein the dc bus voltage is enabled to be in the on state when the dc bus voltage is greater than the desired value and not greater than the over-voltage threshold, and wherein the off state is entered when the dc bus voltage is greater than the over-voltage threshold until the dc bus voltage is less than the desired value.
10. The control circuit of claim 7, wherein the desired value is not greater than a peak value at which the AC input voltage is at a maximum.
11. The control circuit of claim 7, wherein the output of the power stage circuit is provided with a dc bus capacitance, and the capacitance value of the dc bus capacitance is set such that the dc bus voltage is still greater than the desired value when the load is fully loaded.
12. The control circuit of claim 7, wherein the control circuit comprises an enable circuit, the enable circuit comprising:
a first comparator, wherein a non-inverting input end of the first comparator receives the expected value, an inverting input end of the first comparator receives the direct current bus voltage or a sampling signal representing the direct current bus voltage, and an output end of the first comparator outputs a first comparison signal;
a second comparator, wherein a non-inverting input end of the second comparator receives the direct-current bus voltage or a sampling signal representing the direct-current bus voltage, an inverting input end of the second comparator receives the overvoltage threshold, and an output end of the second comparator outputs a second comparison signal;
a logic circuit that sets an enable signal when the first comparison signal is active; and resetting the enable signal when the second comparison signal is valid, wherein the enable signal is used for controlling the enable state of the power stage circuit.
13. The control circuit of claim 12, further comprising a driver circuit, wherein the driver circuit is configured to convert a switch control signal for controlling a power switch in the power stage circuit into a driving signal, and the enable signal controls the enable state of the power stage circuit by controlling the enable state of the driver circuit.
14. The control circuit of claim 7 further comprising a switch control signal generating circuit, wherein the switch control signal generating circuit generates a switch control signal according to the dc bus voltage, the desired value and a switch current sampling signal in the power stage circuit, and the switch control signal is used to control the switching state of the power switch in the power stage circuit, so that the dc bus voltage is maintained at the desired value and the power factor of the PFC circuit meets the operating requirement.
15. The control circuit of claim 1 wherein the power stage circuit operates in a constant peak current mode.
16. The control circuit of claim 2, wherein when the power stage circuit is in the shutdown state, the power stage circuit provides a pass-through path to pass the filtered ac input voltage directly to the output of the power stage circuit as the dc bus voltage.
17. The control circuit of claim 2, wherein when the power stage circuit is in the operating state, a power switch in the power stage circuit is controlled to switch a switch state, and the dc input voltage obtained after the ac input voltage filtering is boosted to obtain a desired dc bus voltage.
18. The control circuit of claim 11, wherein the capacitance of the dc bus capacitor is set such that the power stage circuit is always off during a power frequency cycle when the amplitude of the ac input voltage is greater than a predetermined value.
19. A PFC circuit, comprising:
a power stage circuit, and,
the control circuit of any of claims 1-18.
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| CN202110659531.1ACN113394964B (en) | 2021-06-15 | 2021-06-15 | Control circuit and PFC circuit applying same |
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| CN202110659531.1ACN113394964B (en) | 2021-06-15 | 2021-06-15 | Control circuit and PFC circuit applying same |
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