技术领域technical field
本发明涉及一种升压转换器，特别涉及一种高输出效率的升压转换器。The invention relates to a boost converter, in particular to a boost converter with high output efficiency.
背景技术Background technique
在传统升压转换器中，各切换器往往具有非理想的寄生电容，故当切换器由禁能状态转为致能状态时，其通常无法实现完美的零电压切换(Zero Voltage Switching，ZVS)操作，并导致升压转换器的输出效率变低。有鉴于此，势必要提出一种全新的解决方案，以克服现有技术所面临的困境。In a conventional boost converter, each switch often has non-ideal parasitic capacitance, so when the switch switches from a disabled state to an enabled state, it usually cannot achieve a perfect Zero Voltage Switching (ZVS) operation, resulting in low output efficiency of the boost converter. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the existing technologies.
发明内容Contents of the invention
在优选实施例中，本发明提出一种升压转换器，包括：一第一电感器，用于接收一输入电位；一第一切换器，内建一第一寄生电容器，其中该第一切换器是根据一第一控制电位来选择性地将该第一电感器耦接至一接地电位；一输出级电路，用于产生一输出电位；一第二切换器，内建一第二寄生电容器，其中该第二切换器是根据一第二控制电位来选择性地将该第一电感器耦接至该输出级电路；以及一调整电路，包括一第二电感器、一第三电感器，以及一放电路径，其中该第一寄生电容器与该第二电感器共振再经由该放电路径耦接至该接地电位，或是该第二寄生电容器与该第三电感器共振再经由该放电路径耦接至该接地电位。In a preferred embodiment, the present invention provides a boost converter, comprising: a first inductor for receiving an input potential; a first switch built with a first parasitic capacitor, wherein the first switch selectively couples the first inductor to a ground potential according to a first control potential; an output stage circuit for generating an output potential; a second switch built with a second parasitic capacitor, wherein the second switch selectively couples the first inductor to the output stage circuit according to a second control potential; A second inductor, a third inductor, and a discharge path, wherein the first parasitic capacitor resonates with the second inductor and is coupled to the ground potential through the discharge path, or the second parasitic capacitor resonates with the third inductor and is coupled to the ground potential through the discharge path.
在一些实施例中，该第一电感器具有一第一端和一第二端，该第一电感器的该第一端是耦接至一输入节点以接收该输入电位，而该第一电感器的该第二端是耦接至一第一节点。In some embodiments, the first inductor has a first terminal and a second terminal, the first terminal of the first inductor is coupled to an input node to receive the input potential, and the second terminal of the first inductor is coupled to a first node.
在一些实施例中，该第一切换器包括：一第一晶体管，具有一控制端、一第一端，以及一第二端，其中该第一晶体管的该控制端用于接收该第一控制电位，该第一晶体管的该第一端是耦接至该接地电位，而该第一晶体管的该第二端是耦接至该第一节点。In some embodiments, the first switch includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the first control potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the first node.
在一些实施例中，该第一寄生电容器具有一第一端和一第二端，该第一寄生电容器的该第一端是耦接至该第一节点，而该第一寄生电容器的该第二端是耦接至该接地电位。In some embodiments, the first parasitic capacitor has a first terminal and a second terminal, the first terminal of the first parasitic capacitor is coupled to the first node, and the second terminal of the first parasitic capacitor is coupled to the ground potential.
在一些实施例中，该输出级电路包括：一电容器，具有一第一端和一第二端，其中该电容器的该第一端是耦接至一输出节点以输出该输出电位，而该电容器的该第二端是耦接至该接地电位。In some embodiments, the output stage circuit includes: a capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is coupled to an output node to output the output potential, and the second terminal of the capacitor is coupled to the ground potential.
在一些实施例中，该第二切换器包括：一第二晶体管，具有一控制端、一第一端，以及一第二端，其中该第二晶体管的该控制端用于接收该第二控制电位，该第二晶体管的该第一端是耦接至该输出节点，而该第二晶体管的该第二端是耦接至该第一节点。In some embodiments, the second switch includes: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive the second control potential, the first terminal of the second transistor is coupled to the output node, and the second terminal of the second transistor is coupled to the first node.
在一些实施例中，该第二寄生电容器具有一第一端和一第二端，该第二寄生电容器的该第一端是耦接至该第一节点，而该第二寄生电容器的该第二端是耦接至该输出节点。In some embodiments, the second parasitic capacitor has a first terminal and a second terminal, the first terminal of the second parasitic capacitor is coupled to the first node, and the second terminal of the second parasitic capacitor is coupled to the output node.
在一些实施例中，该第二电感器具有一第一端和一第二端，该第二电感器的该第一端是耦接至该第一节点，该第二电感器的该第二端是耦接至一第二节点，该第三电感器具有一第一端和一第二端，该第三电感器的该第一端是耦接至该第一节点，而该第三电感器的该第二端是耦接至该第二节点。In some embodiments, the second inductor has a first terminal and a second terminal, the first terminal of the second inductor is coupled to the first node, the second terminal of the second inductor is coupled to a second node, the third inductor has a first terminal and a second terminal, the first terminal of the third inductor is coupled to the first node, and the second terminal of the third inductor is coupled to the second node.
在一些实施例中，当该该第一晶体管致能且该第二晶体管禁能时，该第二寄生电容器是与该第三电感器共振再通过该放电路径进行完全放电，而当该第一晶体管禁能且该第二晶体管致能时，该第一寄生电容器是与该第二电感器共振再通过该放电路径进行完全放电。In some embodiments, when the first transistor is enabled and the second transistor is disabled, the second parasitic capacitor resonates with the third inductor and is fully discharged through the discharge path, and when the first transistor is disabled and the second transistor is enabled, the first parasitic capacitor resonates with the second inductor and is fully discharged through the discharge path.
在一些实施例中，该放电路径包括：一二极管，具有一阳极和一阴极，其中该二极管的该阳极是耦接至该第二节点，而该二极管的该阴极是耦接至一第三节点；以及一电阻器，具有一第一端和一第二端，其中该电阻器的该第一端是耦接至该第三节点，而该电阻器的该第二端是耦接至该接地电位。In some embodiments, the discharge path includes: a diode having an anode and a cathode, wherein the anode of the diode is coupled to the second node, and the cathode of the diode is coupled to a third node; and a resistor has a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the third node, and the second terminal of the resistor is coupled to the ground potential.
附图说明Description of drawings
图1是显示根据本发明一实施例所述的升压转换器的示意图。FIG. 1 is a schematic diagram showing a boost converter according to an embodiment of the invention.
图2是显示根据本发明一实施例所述的升压转换器的示意图。FIG. 2 is a schematic diagram showing a boost converter according to an embodiment of the invention.
图3A是显示升压转换器未使用调整电路时的电位波形图。FIG. 3A is a graph showing potential waveforms of the boost converter when no adjustment circuit is used.
图3B是显示根据本发明一实施例所述的升压转换器(已使用调整电路)的电位波形图。FIG. 3B is a diagram showing potential waveforms of a boost converter (using a regulating circuit) according to an embodiment of the invention.
图4A是显示升压转换器未使用调整电路时的电位波形图。FIG. 4A is a graph showing potential waveforms of the boost converter when no adjustment circuit is used.
图4B是显示根据本发明一实施例所述的升压转换器(已使用调整电路)的电位波形图。FIG. 4B is a diagram showing potential waveforms of a boost converter (using a regulating circuit) according to an embodiment of the invention.
附图标记说明：Explanation of reference signs:
100、200～升压转换器；100, 200 ~ boost converter;
110、210～第一切换器；110, 210～the first switcher;
120、220～第二切换器；120, 220 ~ the second switcher;
130、230～调整电路；130, 230～adjustment circuit;
140、240～放电路径；140, 240 ~ discharge path;
150、250～输出级电路；150, 250 ~ output stage circuit;
C1～电容器；C1～capacitor;
CP1～第一寄生电容器；CP1～the first parasitic capacitor;
CP2～第二寄生电容器；CP2～the second parasitic capacitor;
D1～二极管；D1～diode;
ID1～第一电流；ID1 ~ the first current;
ID2～第二电流；ID2～the second current;
L1～第一电感器；L1～the first inductor;
L2～第二电感器；L2～the second inductor;
L3～第三电感器；L3～the third inductor;
M1～第一晶体管；M1～the first transistor;
M2～第二晶体管；M2～second transistor;
N1～第一节点；N1～the first node;
N2～第二节点；N2～the second node;
N3～第三节点；N3～the third node;
NIN～输入节点；NIN～input node;
NOUT～输出节点；NOUT～output node;
PA1～第一电流路径；PA1～the first current path;
PA2～第二电流路径；PA2～the second current path;
R1～电阻器；R1～resistor;
VC1～第一控制电位；VC1～the first control potential;
VC2～第二控制电位；VC2～the second control potential;
VD1～第一电压；VD1～the first voltage;
VD2～第二电压；VD2～the second voltage;
VIN～输入电位；VIN～input potential;
VOUT～输出电位；VOUT～output potential;
VSS～接地电位。VSS ~ ground potential.
具体实施方式Detailed ways
为让本发明的目的、特征和优点能更明显易懂，下文特举出本发明的具体实施例，并配合说明书附图，作详细说明如下。In order to make the purpose, features and advantages of the present invention more comprehensible, the specific embodiments of the present invention are listed below, together with the accompanying drawings, which are described in detail as follows.
在说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的准则。在通篇说明书及权利要求当中所提及的“包含”及“包括”一词为开放式的用语，故应解释成“包含但不仅限定于”。“大致”一词则是指在可接受的误差范围内，本领域技术人员能够在一定误差范围内解决所述技术问题，达到所述基本的技术效果。此外，“耦接”一词在本说明书中包含任何直接及间接的电性连接手段。因此，若文中描述一第一装置耦接至一第二装置，则代表该第一装置可直接电性连接至该第二装置，或经由其它装置或连接手段而间接地电性连接至该第二装置。Certain terms are used in the description and claims to refer to particular elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The words "comprising" and "comprising" mentioned throughout the specification and claims are open-ended terms, so they should be interpreted as "including but not limited to". The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.
图1是显示根据本发明一实施例所述的升压转换器100的示意图。升压转换器100可应用于一移动装置，例如：台式电脑、笔记本电脑，或一体成形电脑。如图1所示，升压转换器100包括：一第一电感器L1、一第一切换器110、一第二切换器120、一调整电路130，以及一输出级电路150，其中第一切换器110内建一第一寄生电容器CP1，第二切换器120内建一第二寄生电容器CP2，而调整电路130包括一第二电感器L2、一第三电感器L3，以及一放电路径140。必须注意的是，虽然未显示于图1中，但升压转换器100还可包括其他元件，例如：一稳压器或(且)一负反馈电路。FIG. 1 is a schematic diagram showing a boost converter 100 according to an embodiment of the invention. The boost converter 100 can be applied to a mobile device, such as a desktop computer, a notebook computer, or an all-in-one computer. As shown in FIG. 1 , the boost converter 100 includes: a first inductor L1 , a first switch 110 , a second switch 120 , an adjustment circuit 130 , and an output stage circuit 150 , wherein the first switch 110 has a built-in first parasitic capacitor CP1 , the second switch 120 has a built-in second parasitic capacitor CP2 , and the adjustment circuit 130 includes a second inductor L2 , a third inductor L3 , and a discharge path 140 . It should be noted that although not shown in FIG. 1 , the boost converter 100 may also include other components, such as a voltage regulator and/or a negative feedback circuit.
第一电感器L1可视为升压转换器100的一升压电感器。第一电感器L1用于接收一输入电位VIN。输入电位VIN可来自一外部电源，其中输入电位VIN可为具有任意频率和任意振幅的一交流电位。例如，交流电位的频率可约为50Hz或60Hz，而交流电位的方均根值可约为110V或220V，但亦不仅限于此。第一切换器110可根据一第一控制电位VC1来选择性地将第一电感器L1耦接至一接地电位VSS(例如：0V)。例如，若第一控制电位VC1为高逻辑电平(例如：逻辑“1”)，则第一切换器110即将第一电感器L1耦接至接地电位VSS(亦即，第一切换器110可近似于一短路路径)；反之，若第一控制电位VC1为低逻辑电平(例如：逻辑“0”)，则第一切换器110不会将第一电感器L1耦接至接地电位VSS(亦即，第一切换器110可近似于一开路路径)。第一切换器110的二端之间的总寄生电容可模拟为前述的第一寄生电容器CP1，其并非一外部独立元件。第一控制电位VC1于升压转换器100初始化时可维持于一固定电位，而在升压转换器100进入正常使用阶段后则可提供周期性的时脉波形。相似地，第二切换器120可根据一第二控制电位VC2来选择性地将第一电感器L1耦接至输出级电路150。例如，若第二控制电位VC1为高逻辑电平，则第二切换器120即将第一电感器L1耦接至输出级电路150(亦即，第二切换器120可近似于一短路路径)；反之，若第二控制电位VC2为低逻辑电平，则第二切换器120不会将第一电感器L1耦接至输出级电路150(亦即，第二切换器120可近似于一开路路径)。第二切换器120的二端之间的总寄生电容可模拟为前述的第二寄生电容器CP2，其并非一外部独立元件。第二控制电位VC2可与第一控制电位VC1具有相同的波形，但两者间的相位差可大致等于180度。调整电路130是耦接至第一切换器110和第二切换器120，其可用于补偿第一寄生电容器CP1和第二寄生电容器CP2。输出级电路150用于产生一输出电位VOUT。输出电位VOUT可为一直流电位，其中输出电位VOUT的电位电平是高于输入电位VIN的最大值。整体而言，升压转换器100可操作于一第一模式或一第二模式。在第一模式中，第一寄生电容器CP1是与第二电感器L2发生共振，再经由放电路径140耦接至接地电位VSS。在第二模式中，第二寄生电容器CP2是与第三电感器L3发生共振，再经由放电路径140耦接至接地电位VSS。根据实际测量结果，这种电路设计方式可抑制第一寄生电容器CP1和第二寄生电容器CP2的非理想特性，并使第一切换器110和第二切换器120可实现几乎无损耗的零电压切换操作，故能有效提高升压转换器100的输出效率。The first inductor L1 can be regarded as a boost inductor of the boost converter 100 . The first inductor L1 is used for receiving an input potential VIN. The input potential VIN can come from an external power source, wherein the input potential VIN can be an AC potential with any frequency and any amplitude. For example, the frequency of the AC potential may be about 50 Hz or 60 Hz, and the RMS value of the AC potential may be about 110 V or 220 V, but not limited thereto. The first switch 110 can selectively couple the first inductor L1 to a ground potential VSS (eg, 0V) according to a first control potential VC1 . For example, if the first control potential VC1 is at a high logic level (eg, logic “1”), the first switch 110 will couple the first inductor L1 to the ground potential VSS (that is, the first switch 110 can be approximated as a short-circuit path); otherwise, if the first control potential VC1 is at a low logic level (eg, logic “0”), the first switch 110 will not couple the first inductor L1 to the ground potential VSS (ie, the first switch 110 can be approximated as an open path). The total parasitic capacitance between the two terminals of the first switch 110 can be modeled as the aforementioned first parasitic capacitor CP1, which is not an external independent component. The first control potential VC1 can be maintained at a fixed potential when the boost converter 100 is initialized, and can provide a periodic clock waveform after the boost converter 100 enters a normal use stage. Similarly, the second switch 120 can selectively couple the first inductor L1 to the output stage circuit 150 according to a second control potential VC2 . For example, if the second control potential VC1 is at a high logic level, the second switch 120 will couple the first inductor L1 to the output-stage circuit 150 (that is, the second switch 120 can be approximated as a short-circuit path); otherwise, if the second control potential VC2 is at a low logic level, the second switch 120 will not couple the first inductor L1 to the output-stage circuit 150 (that is, the second switch 120 can approximate an open-circuit path). The total parasitic capacitance between the two terminals of the second switch 120 can be modeled as the aforementioned second parasitic capacitor CP2, which is not an external independent component. The second control potential VC2 can have the same waveform as the first control potential VC1 , but the phase difference between them can be roughly equal to 180 degrees. The adjustment circuit 130 is coupled to the first switch 110 and the second switch 120 , and can be used to compensate the first parasitic capacitor CP1 and the second parasitic capacitor CP2 . The output stage circuit 150 is used to generate an output potential VOUT. The output potential VOUT can be a DC potential, wherein the potential level of the output potential VOUT is higher than the maximum value of the input potential VIN. Overall, the boost converter 100 can operate in a first mode or a second mode. In the first mode, the first parasitic capacitor CP1 resonates with the second inductor L2 and is coupled to the ground potential VSS through the discharge path 140 . In the second mode, the second parasitic capacitor CP2 resonates with the third inductor L3 and is coupled to the ground potential VSS through the discharge path 140 . According to actual measurement results, this circuit design method can suppress the non-ideal characteristics of the first parasitic capacitor CP1 and the second parasitic capacitor CP2, and enable the first switcher 110 and the second switcher 120 to achieve zero-voltage switching operation with almost no loss, so the output efficiency of the boost converter 100 can be effectively improved.
以下实施例将介绍升压转换器100的详细结构及操作方式。必须理解的是，这些附图和叙述仅为举例，而非用于限制本发明的范围。The following embodiments will introduce the detailed structure and operation of the boost converter 100 . It must be understood that these drawings and descriptions are only examples and not intended to limit the scope of the present invention.
图2是显示根据本发明一实施例所述的升压转换器200的示意图。在图2的实施例中，升压转换器200具有一输入节点NIN和一输出节点NOUT，并包括一第一电感器L1、一第一切换器210、一第二切换器220、一调整电路230，以及一输出级电路250，其中第一切换器210内建一第一寄生电容器CP1，第二切换器220内建一第二寄生电容器CP2，而调整电路230包括一第二电感器L2、一第三电感器L3，以及一放电路径240。升压转换器200的输入节点NIN可由一外部电源处接收一输入电位VIN，而升压转换器200的输出节点NOUT可用于输出一输出电位VOUT，其中输出电位VOUT的电位电平是高于输入电位VIN的最大值。在一些实施例中，第一切换器210可视为升压转换器200的一主功率开关，而第二切换器220可视为升压转换器200的一同步整流开关，但亦不仅限于此。FIG. 2 is a schematic diagram showing a boost converter 200 according to an embodiment of the invention. In the embodiment of FIG. 2, the boost converter 200 has an input node NIN and an output node NOUT, and includes a first inductor L1, a first switch 210, a second switch 220, an adjustment circuit 230, and an output stage circuit 250, wherein the first switch 210 has a built-in first parasitic capacitor CP1, the second switch 220 has a built-in second parasitic capacitor CP2, and the adjustment circuit 230 includes a second inductor L2 and a third inductor L3. and a discharge path 240 . The input node NIN of the boost converter 200 can receive an input potential VIN from an external power source, and the output node NOUT of the boost converter 200 can be used to output an output potential VOUT, wherein the potential level of the output potential VOUT is higher than the maximum value of the input potential VIN. In some embodiments, the first switch 210 can be regarded as a main power switch of the boost converter 200 , and the second switch 220 can be regarded as a synchronous rectification switch of the boost converter 200 , but it is not limited thereto.
第一电感器L1具有一第一端和一第二端，其中第一电感器L1的第一端是耦接至输入节点NIN，而第一电感器L1的第二端是耦接至一第一节点N1。The first inductor L1 has a first terminal and a second terminal, wherein the first terminal of the first inductor L1 is coupled to the input node NIN, and the second terminal of the first inductor L1 is coupled to a first node N1.
第一切换器210包括一第一晶体管M1。第一晶体管M1可为一N型金属氧化物半导体场效晶体管。第一晶体管M1具有一控制端、一第一端，以及一第二端，其中第一晶体管M1的控制端用于接收一第一控制电位VC1，第一晶体管M1的第一端是耦接至一接地电位VSS，而第一晶体管M1的第二端是耦接至第一节点N1。例如，第一控制电位VC1于升压转换器200初始化时可维持于一固定电位(例如：接地电位VSS)，而在升压转换器200进入正常使用阶段后则可提供周期性的时脉波形。第一晶体管M1的第一端和第二端之间的总寄生电容可模拟为前述的第一寄生电容器CP1，其并非一外部独立元件。第一寄生电容器CP1具有一第一端和一第二端，其中第一寄生电容器CP1的第一端是耦接至第一节点N1，而第一寄生电容器CP1的第二端是耦接至接地电位VSS。The first switch 210 includes a first transistor M1. The first transistor M1 can be an NMOS field effect transistor. The first transistor M1 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor M1 is used to receive a first control potential VC1, the first terminal of the first transistor M1 is coupled to a ground potential VSS, and the second terminal of the first transistor M1 is coupled to the first node N1. For example, the first control potential VC1 can be maintained at a fixed potential (such as the ground potential VSS) when the boost converter 200 is initialized, and can provide a periodic clock waveform after the boost converter 200 enters a normal use stage. The total parasitic capacitance between the first terminal and the second terminal of the first transistor M1 can be modeled as the aforementioned first parasitic capacitor CP1, which is not an external independent component. The first parasitic capacitor CP1 has a first terminal and a second terminal, wherein the first terminal of the first parasitic capacitor CP1 is coupled to the first node N1, and the second terminal of the first parasitic capacitor CP1 is coupled to the ground potential VSS.
第二切换器220包括一第二晶体管M2。第二晶体管M2可为一N型金属氧化物半导体场效晶体管。第二晶体管M2具有一控制端、一第一端，以及一第二端，其中第二晶体管M2的控制端用于接收一第二控制电位VC2，第二晶体管M2的第一端是耦接至输出节点NOUT，而第二晶体管M2的第二端是耦接至第一节点N1。例如，第二控制电位VC2可与第一控制电位VC1具有相同的波形，但两者间的相位差可大致等于180度。第二晶体管M2的第一端和第二端之间的总寄生电容可模拟为前述的第二寄生电容器CP2，其并非一外部独立元件。第二寄生电容器CP2具有一第一端和一第二端，其中第二寄生电容器CP2的第一端是耦接至第一节点N1，而第二寄生电容器CP2的第二端是耦接至输出节点NOUT。The second switch 220 includes a second transistor M2. The second transistor M2 can be an NMOS field effect transistor. The second transistor M2 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor M2 is used to receive a second control potential VC2, the first terminal of the second transistor M2 is coupled to the output node NOUT, and the second terminal of the second transistor M2 is coupled to the first node N1. For example, the second control potential VC2 may have the same waveform as the first control potential VC1 , but the phase difference between them may be substantially equal to 180 degrees. The total parasitic capacitance between the first terminal and the second terminal of the second transistor M2 can be modeled as the aforementioned second parasitic capacitor CP2, which is not an external independent component. The second parasitic capacitor CP2 has a first terminal and a second terminal, wherein the first terminal of the second parasitic capacitor CP2 is coupled to the first node N1, and the second terminal of the second parasitic capacitor CP2 is coupled to the output node NOUT.
输出级电路250包括一电容器C1。电容器C1具有一第一端和一第二端，其中电容器C1的第一端是耦接至输出节点NOUT，而电容器C1的第二端是耦接至接地电位VSS。The output stage circuit 250 includes a capacitor C1. The capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the capacitor C1 is coupled to the output node NOUT, and the second terminal of the capacitor C1 is coupled to the ground potential VSS.
在调整电路230中，第二电感器L2和第三电感器L3两者并联耦接。详细而言，第二电感器L2具有一第一端和一第二端，其中第二电感器L2的第一端是耦接至第一节点N1，而第二电感器L2的第二端是耦接至一第二节点N2。第三电感器L3具有一第一端和一第二端，其中第三电感器L3的第一端是耦接至第一节点N1，而第三电感器L3的第二端是耦接至第二节点N2。In the adjustment circuit 230, both the second inductor L2 and the third inductor L3 are coupled in parallel. In detail, the second inductor L2 has a first terminal and a second terminal, wherein the first terminal of the second inductor L2 is coupled to the first node N1, and the second terminal of the second inductor L2 is coupled to a second node N2. The third inductor L3 has a first terminal and a second terminal, wherein the first terminal of the third inductor L3 is coupled to the first node N1, and the second terminal of the third inductor L3 is coupled to the second node N2.
调整电路230的放电路径240包括一二极管D1和一电阻器R1。二极管D1具有一阳极和一阴极，其中二极管D1的阳极是耦接至第二节点N2，而二极管D1的阴极是耦接至一第三节点N3。电阻器R1具有一第一端和一第二端，其中电阻器R1的第一端是耦接至第三节点N3，而电阻器R1的第二端是耦接至接地电位VSS。在一些实施例中，电阻器R1具有相对较大的电阻值，使得放电路径240的整体阻抗值相对较高。The discharge path 240 of the adjustment circuit 230 includes a diode D1 and a resistor R1. The diode D1 has an anode and a cathode, wherein the anode of the diode D1 is coupled to the second node N2, and the cathode of the diode D1 is coupled to a third node N3. The resistor R1 has a first terminal and a second terminal, wherein the first terminal of the resistor R1 is coupled to the third node N3, and the second terminal of the resistor R1 is coupled to the ground potential VSS. In some embodiments, the resistor R1 has a relatively large resistance value, so that the overall impedance value of the discharge path 240 is relatively high.
在一些实施例中，升压转换器200是交替地操作于一第一模式和一第二模式，其详细操作原理可如下列所述。In some embodiments, the boost converter 200 is alternately operated in a first mode and a second mode, and the detailed operation principles thereof can be described as follows.
在第一模式中，第一控制电位VC1为高逻辑电平且第二控制电位VC2为低逻辑电平，故第一晶体管M1为致能且第二晶体管M2为禁能。此时，第二寄生电容器CP2是与第三电感器L3发生共振，接着第二寄生电容器CP2再通过放电路径240进行完全放电(如一第一电流路径PA1所示)。必须注意的是，在第一模式中，由于致能的第一晶体管M1的导通电阻值远小于电阻器R1的电阻值，故几乎没有任何电流流经第二电感器L2。In the first mode, the first control potential VC1 is at a high logic level and the second control potential VC2 is at a low logic level, so the first transistor M1 is enabled and the second transistor M2 is disabled. At this time, the second parasitic capacitor CP2 resonates with the third inductor L3 , and then the second parasitic capacitor CP2 is fully discharged through the discharge path 240 (as shown by a first current path PA1 ). It should be noted that in the first mode, almost no current flows through the second inductor L2 because the on-resistance of the enabled first transistor M1 is much smaller than the resistance of the resistor R1.
在第二模式中，第一控制电位VC1为低逻辑电平且第二控制电位VC2为高逻辑电平，故第一晶体管M1为禁能且第二晶体管M2为致能。此时，第一寄生电容器CP1是与第二电感器L2发生共振，接着第一寄生电容器CP1再通过放电路径240进行完全放电(如一第二电流路径PA1所示)。必须注意的是，在第二模式中，由于致能的第二晶体管M2的导通电阻值远小于电阻器R1的电阻值，故几乎没有任何电流流经第三电感器L3。In the second mode, the first control potential VC1 is at a low logic level and the second control potential VC2 is at a high logic level, so the first transistor M1 is disabled and the second transistor M2 is enabled. At this time, the first parasitic capacitor CP1 resonates with the second inductor L2 , and then the first parasitic capacitor CP1 is fully discharged through the discharge path 240 (as shown by a second current path PA1 ). It should be noted that in the second mode, almost no current flows through the third inductor L3 since the on-resistance of the enabled second transistor M2 is much smaller than the resistance of the resistor R1 .
图3A是显示升压转换器200未使用调整电路230时的电位波形图，其中横轴代表时间，而纵轴代表电压值或电流值。如图3A所示，若未使用调整电路230，第一切换器210的第一寄生电容器CP1将会存储些许电荷。当第一切换器210由禁能状态转换为致能状态时，通过第一晶体管M1的一第一电流ID1由零开始上升，但第一寄生电容器CP1的第一端和第二端之间的一第一电压VD1却尚未下降至零，此导致第一切换器210会产生不必要的能量损耗。FIG. 3A is a graph showing potential waveforms of the boost converter 200 when the adjustment circuit 230 is not used, wherein the horizontal axis represents time, and the vertical axis represents voltage or current. As shown in FIG. 3A , if the adjustment circuit 230 is not used, the first parasitic capacitor CP1 of the first switch 210 will store some charges. When the first switch 210 is switched from the disabled state to the enabled state, a first current ID1 passing through the first transistor M1 rises from zero, but a first voltage VD1 between the first terminal and the second terminal of the first parasitic capacitor CP1 has not yet dropped to zero, which causes unnecessary energy loss of the first switch 210.
图3B是显示根据本发明一实施例所述的升压转换器200(已使用调整电路230)的电位波形图，其中横轴代表时间，而纵轴代表电压值或电流值。如图3B所示，若已使用调整电路230，则可有效抑制第一寄生电容器CP1的非理想特性。当第一切换器210由禁能状态转换为致能状态时，第一寄生电容器CP1的第一端和第二端之间的第一电压VD1已经完全放电至零，使得第一切换器210可实现近乎无损耗的零电压切换操作。FIG. 3B is a potential waveform diagram showing the boost converter 200 (using the adjustment circuit 230 ) according to an embodiment of the present invention, wherein the horizontal axis represents time, and the vertical axis represents voltage or current. As shown in FIG. 3B , if the adjustment circuit 230 is used, the non-ideal characteristics of the first parasitic capacitor CP1 can be effectively suppressed. When the first switch 210 is switched from the disabled state to the enabled state, the first voltage VD1 between the first terminal and the second terminal of the first parasitic capacitor CP1 has been completely discharged to zero, so that the first switch 210 can realize almost lossless zero-voltage switching operation.
图4A是显示升压转换器200未使用调整电路230时的电位波形图，其中横轴代表时间，而纵轴代表电压值或电流值。如图4A所示，若未使用调整电路230，第二切换器220的第二寄生电容器CP2将会存储些许电荷。当第二切换器220由禁能状态转换为致能状态时，通过第二晶体管M2的一第二电流ID2由零开始上升，但第二寄生电容器CP2的第一端和第二端之间的一第二电压VD2却尚未下降至零，此导致第二切换器220会产生不必要的能量损耗。FIG. 4A is a graph showing potential waveforms of the boost converter 200 when the adjustment circuit 230 is not used, wherein the horizontal axis represents time, and the vertical axis represents voltage or current. As shown in FIG. 4A , if the adjustment circuit 230 is not used, the second parasitic capacitor CP2 of the second switch 220 will store some charges. When the second switch 220 is switched from the disabled state to the enabled state, a second current ID2 passing through the second transistor M2 rises from zero, but a second voltage VD2 between the first terminal and the second terminal of the second parasitic capacitor CP2 has not yet dropped to zero, which causes unnecessary energy loss of the second switch 220.
图4B是显示根据本发明一实施例所述的升压转换器200(已使用调整电路230)的电位波形图，其中横轴代表时间，而纵轴代表电压值或电流值。如图4B所示，若已使用调整电路230，则可有效抑制第二寄生电容器CP2的非理想特性。当第二切换器220由禁能状态转换为致能状态时，第二寄生电容器CP2的第一端和第二端之间的第二电压VD2已经完全放电至零，使得第二切换器220可实现近乎无损耗的零电压切换操作。FIG. 4B is a potential waveform diagram showing the boost converter 200 (using the adjustment circuit 230 ) according to an embodiment of the present invention, wherein the horizontal axis represents time, and the vertical axis represents voltage or current. As shown in FIG. 4B , if the adjustment circuit 230 is used, the non-ideal characteristics of the second parasitic capacitor CP2 can be effectively suppressed. When the second switch 220 is switched from the disabled state to the enabled state, the second voltage VD2 between the first terminal and the second terminal of the second parasitic capacitor CP2 has been completely discharged to zero, so that the second switch 220 can realize nearly lossless zero-voltage switching operation.
在一些实施例中，升压转换器200的元件参数可如下列所述。第一寄生电容器CP1的电容值可介于142.5pF至157.5pF之间，优选为150pF。第二寄生电容器CP2的电容值可介于142.5pF至157.5pF之间，优选为150pF。电容器C1的电容值可介于612μF至748μF之间，优选为680μF。第二电感器L2的电感值可介于19μH至21μH之间，优选为20μH。第三电感器L3的电感值可介于19μH至21μH之间，优选为20μH。电阻器R1的电阻值可介于22.5MΩ至27.5MΩ之间，优选为25MΩ。第一控制电位VC1和第二控制电位VC2的切换频率皆可约为65kHz，以上参数范围是根据多次实验结果而得出，其有助于最佳化升压转换器200的转换效率。In some embodiments, the component parameters of the boost converter 200 can be as follows. The capacitance of the first parasitic capacitor CP1 can be between 142.5pF and 157.5pF, preferably 150pF. The capacitance of the second parasitic capacitor CP2 can be between 142.5pF and 157.5pF, preferably 150pF. The capacitance of the capacitor C1 can be between 612 μF to 748 μF, preferably 680 μF. The inductance of the second inductor L2 can be between 19 μH and 21 μH, preferably 20 μH. The inductance of the third inductor L3 can be between 19 μH and 21 μH, preferably 20 μH. The resistance value of the resistor R1 can be between 22.5MΩ and 27.5MΩ, preferably 25MΩ. Both the switching frequency of the first control potential VC1 and the second control potential VC2 may be about 65 kHz, and the above parameter ranges are obtained based on multiple experimental results, which help to optimize the conversion efficiency of the boost converter 200 .
本发明提出一种新颖的升压转换器，其包括调整电路及其放电路径。根据实际测量结果，使用前述设计的升压转换器可消除各个切换器的非理想寄生电容效应，从而可实现近乎无损耗的零电压切换操作。大致而言，本发明可有效提高升压转换器的输出效率，故其很适合应用于各种各式的电子装置当中。The present invention proposes a novel boost converter, which includes a regulation circuit and a discharge path thereof. According to actual measurement results, using the boost converter of the aforementioned design can eliminate the non-ideal parasitic capacitance effect of each switcher, so that nearly lossless zero-voltage switching operation can be achieved. Generally speaking, the present invention can effectively improve the output efficiency of the boost converter, so it is very suitable for application in various electronic devices.
值得注意的是，以上所述的电位、电流、电阻值、电感值、电容值，以及其余元件参数均非为本发明的限制条件。设计者可以根据不同需要调整这些设定值。本发明的升压转换器并不仅限于图1至图4所图示的状态。本发明可以仅包括图1至图4的任何一或多个实施例的任何一或多个项特征。换言之，并非所有图示的特征均须同时实施于本发明的升压转换器当中。虽然本发明的实施例是使用金属氧化物半导体场效晶体管为例，但本发明并不仅限于此，本技术领域人士可改用其他种类的晶体管，例如：接面场效晶体管，或是鳍式场效晶体管等等，而不致于影响本发明的效果。It should be noted that the potential, current, resistance value, inductance value, capacitance value, and other component parameters mentioned above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The boost converter of the present invention is not limited to the states illustrated in FIGS. 1 to 4 . The present invention may only include any one or more of the features of any one or more of the embodiments of FIGS. 1-4 . In other words, not all the illustrated features must be implemented in the boost converter of the present invention at the same time. Although the embodiment of the present invention uses metal-oxide-semiconductor field effect transistors as an example, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fin field effect transistors, etc., without affecting the effect of the present invention.
在本说明书以及权利要求中的序数，例如“第一”、“第二”、“第三”等等，彼此之间并没有顺序上的先后关系，其仅用于标示区分两个具有相同名字的不同元件。Ordinal numbers in the specification and claims, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to identify and distinguish two different elements with the same name.
本发明虽以优选实施例公开如上，然其并非用以限定本发明的范围，任何熟习此项技艺者，在不脱离本发明的构思和范围内，当可做些许的变动与润饰，因此本发明的保护范围当视权利要求所界定者为准。Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in this art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention should be as the criterion as defined by the claims.
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| CN202010098554.5ACN113346771B (en) | 2020-02-18 | 2020-02-18 | boost converter |
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| CN202010098554.5ACN113346771B (en) | 2020-02-18 | 2020-02-18 | boost converter |
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