Power tube soft start circuit applied to power management chipTechnical Field
The invention relates to the technical field of power tube soft start, in particular to a power tube soft start circuit applied to a power management chip.
Background
In order to drive large current, a power management chip has a large power transistor inside to ensure sufficient output current. However, during the startup of the chip, since the potential of the output capacitor does not reach the set voltage yet, if no processing is performed, the power tube in the chip is fully opened, and the output capacitor is charged with the maximum current until the set voltage. However, when the charging current is too large, the chip itself may be burned out due to too large power, and in addition, the too large charging current indicates that a large current is drawn from the input power, and may also cause the input power to be burned out or cause abnormal voltage, thereby causing a failed start-up. Therefore, the power management chip usually adds a soft start circuit during the start-up to reduce the charging current during the start-up.
As shown in fig. 1, the output voltage VOUT of the circuit is set by resistors R1 and R2, and VOUT is VREF/R1 (R1+ R2). The circuit is divided into two stages during operation, wherein in the first stage, P2 and P3 are closed, P1 and N1 are opened, and the voltage of VC1 is charged to VDD voltage; in the second stage, P1 and N1 are turned off, P2 and P3 are turned on, the voltage of VC2 is decreased to VDD, the voltage of VC1 is decreased to VOUT, at this time, the voltage of VC1 is 2 times VDD voltage because the voltage across VC1 and VC2 is VDD and VC2 is decreased to VDD, and the excess charges are dumped to COUT, so that VOUT voltage is increased. In addition, the P1 CTRL block (control block) determines whether the voltage of P1_ ON is high or low according to the FB and VREF voltages in the first stage, and when the FB voltage is higher than the VREF voltage, which means that VOUT voltage is higher than the set voltage, and P1_ ON voltage is low, the CK _ P1 voltage is high, and P1 is not turned ON; when the FB voltage is lower than VREF voltage, indicating that VOUT voltage is lower than the set voltage, P1_ ON voltage is high, CK _ P1 voltage is pulled low, and P1 can be turned ON to charge capacitor CFLY, while in the second stage, the charge ON capacitor CFLY is dumped to COUT to replenish VOUT. In brief, when the FB voltage is greater than the VREF voltage, P1 will not turn on, and therefore, charge will not be replenished to VOUT, and if VOUT is pumped down, FB will drop; when the FB voltage is lower than the VREF voltage, P1 turns on during the first phase and supplements VOUT with charge during the second phase until the FB voltage rises above the VREF voltage.
It can be seen from the above description that if the voltage VOUT is 0V and the voltage FB is lower than VREF voltage when the circuit is just started, P1 will be turned on in the first stage and output at full power, which may cause the VDD current to be too large and cause the chip to be burned, so a soft start circuit needs to be added to avoid the start current of the chip to be too large.
At present, the principle of the common soft start mode is to make the VREF voltage rise slowly when starting up, so as to disperse the current for charging VOUT, and there are two implementation modes:
1) as shown in fig. 2, implemented in a digital manner, the VREF voltage is increased by one step to one step, and one step per liter, since the FB voltage is lower than the VREF voltage, P1 will start until the FB voltage rises to the VREF voltage, and when the VREF voltage rises by one step again, P1 will turn on again, so that it can be seen that IVDD current (current flowing through VDD) is concentrated in the rising of the VREF voltage, and no current exists at other times;
2) as shown in fig. 3, the VREF voltage rises upward at a constant speed in an analog manner, when the FB voltage is lower than the VREF voltage, P1 is turned on to charge VOUT until the FB voltage catches up with the VREF voltage, compared to a digital manner, in the analog manner, although the analog manner also has a current dispersion effect, the IVDD current is not consistent, and the FB voltage also has a high or low and irregular height each time the FB voltage rises.
Although both of the above-mentioned methods can disperse the charging current during starting, when VOUT is charged, P1 is in a fully open state, so that there is a transient large current, and if the transient large current is too large, the chip may be burned or the soft start failure may still occur.
Disclosure of Invention
The invention aims to provide a power tube soft start circuit applied to a power management chip, which is used for solving the problems of chip burnout or soft start failure and the like caused by overlarge start current when the power management chip is started.
In order to realize the purpose, the following technical scheme is adopted:
a power tube soft start circuit applied to a power management chip comprises a first power tube to be started, a current source I, a capacitor C, a start control power tube and a resistor R; the current source I is connected with the capacitor C, and the start control power tube is connected with the common connecting end of the current source I and the capacitor C; the starting control power tube is also connected with the resistor R, and the first power tube is connected with the common connecting end of the starting control power tube and the resistor R; the current source I is used for charging the capacitor C so as to enable the grid voltage of the starting control power tube to slowly rise, further enable the current flowing through the resistor R to increase, and further reduce the grid voltage of the first power tube so as to carry out soft starting on the first power tube.
Furthermore, a signal control power tube is connected between the current source I and the capacitor C, and a start control power tube is connected with a common connecting end of the capacitor C and the signal control power tube; the grid electrode of the signal control power tube is used for being connected to an external signal controller, so that the signal control power tube is started once every a period of time, and further the charging time of the current source I to the capacitor C is prolonged.
Furthermore, a switch control power tube is connected between the starting control power tube and the resistor R, and the first power tube is connected with a common connecting end of the switch control power tube and the resistor R; the grid electrode of the switch control power tube is used for being connected with an external switch starter so as to control the switch control power tube to be turned on or turned off.
Furthermore, the first power tube is a P-type MOS tube, and the start control power tube is an N-type MOS tube.
Furthermore, the first power tube is a P-type MOS tube, and the start control power tube is an N-type MOS tube.
Furthermore, the first power tube is an N-type MOS tube, and the start control power tube is a P-type MOS tube.
Furthermore, the first power tube is an N-type MOS tube, and the start control power tube is a P-type MOS tube.
By adopting the scheme, the invention has the beneficial effects that:
the circuit principle is simple, convenient to use, and when can solving the power management chip and starting, starting current is too big and leads to the chip to burn out or soft start failure scheduling problem, guarantees the stability that the chip started, simultaneously, provides a plurality of specific implementation circuit, and the user can select by oneself according to the in-service use demand, and is applicable to the soft start of N type MOS pipe or P type MOS pipe, and the commonality is strong.
Drawings
FIG. 1 is a circuit diagram of a conventional charge pump in the prior art;
FIG. 2 is a diagram illustrating a digital soft start in the prior art;
FIG. 3 is a diagram illustrating an analog soft start in the prior art;
FIG. 4 is a circuit diagram of embodiment 1 of the present invention;
FIG. 5 is a circuit diagram ofembodiment 2 of the present invention;
FIG. 6 is a circuit diagram ofembodiment 3 of the present invention;
FIG. 7 is a circuit diagram ofembodiment 4 of the present invention;
FIG. 8 is a circuit diagram of embodiment 5 of the present invention;
FIG. 9 is a circuit diagram of embodiment 6 of the present invention;
FIG. 10 is a circuit diagram of embodiment 7 of the present invention;
FIG. 11 is a circuit diagram of embodiment 8 of the present invention;
wherein the figures identify the description:
1-a first power tube; 2-starting the control power tube;
3-signal control power tube; and 4, switching the control power tube.
Detailed Description
The invention is described in detail below with reference to the figures and the specific embodiments.
Referring to fig. 4 to 11, the invention provides a power tube soft start circuit applied to a power management chip, which includes a first power tube 1 to be started, a current source I, a capacitor C, a startcontrol power tube 2, and a resistor R; the current source I is connected with the capacitor C, and the startcontrol power tube 2 is connected with a common connecting end of the current source I and the capacitor C; the startingcontrol power tube 2 is also connected with a resistor R, and the first power tube 1 is connected with the common connecting end of the startingcontrol power tube 2 and the resistor R; the current source I is used for charging the capacitor C, so that the gate voltage of the startcontrol power tube 2 is slowly increased, the current flowing through the resistor R is increased, and the gate voltage of the first power tube 1 is reduced to perform soft start.
Example 1: as shown in fig. 4, the first power transistor 1 is a P-type MOS transistor, and the startcontrol power transistor 2 is an N-type MOS transistor; utilize current source I to charge electric capacity C, the voltage of node VGN department (the grid voltage of start control power tube 2) of messenger slowly rises, and then makes startcontrol power tube 2 slowly open, and IN the opening process, can make the electric current IN of flowing through resistance R slowly increase, again because the grid voltage VGP of first power tube 1 is VDD-IN R, so when electric current IN slowly increases, VGP can slowly descend, can realize slowly starting the purpose of first power tube 1.
Example 2: as shown in fig. 5, in this embodiment, on the basis of embodiment 1, a signalcontrol power tube 3 is added between a current source I and a capacitor C, and a startcontrol power tube 2 is connected to a common connection end of the capacitor C and the signalcontrol power tube 3; the gate of the signalcontrol power transistor 3 is connected to an external signal controller, so that the signalcontrol power transistor 3 is turned on at intervals, and further the charging time of the current source I to the capacitor C can be prolonged, so that the first power transistor 1 is turned on slowly, and in addition, the signalcontrol power transistor 3 can be an NMOS transistor or a PMOS transistor.
Example 3: as shown in fig. 6, in this embodiment, on the basis of embodiment 1, a switch control power tube 4 (N-type MOS tube) is added between a startcontrol power tube 2 and a resistor R, and a first power tube 1 is connected to a common connection end of the switchcontrol power tube 4 and the resistor R; the grid electrode of the switchcontrol power tube 4 is used for connecting an external switch starter so as to be used as a switch.
Example 4: as shown in fig. 7, in this embodiment, on the basis ofembodiment 3, a signalcontrol power tube 3 is added between a current source I and a capacitor C, and a startcontrol power tube 2 is connected to a common connection end of the capacitor C and the signalcontrol power tube 3; the gate of the signalcontrol power transistor 3 is connected to an external signal controller, so that the signalcontrol power transistor 3 is turned on at intervals, and further the charging time of the current source I to the capacitor C can be prolonged, so that the first power transistor 1 is turned on slowly, and in addition, the signalcontrol power transistor 3 can be an NMOS transistor or a PMOS transistor.
Example 5: as shown in fig. 8, the principle of this embodiment is similar to that of embodiment 1, except that in this embodiment, the first power transistor 1 is an N-type MOS transistor, and the start-upcontrol power transistor 2 is a P-type MOS transistor.
Example 6: as shown in fig. 9, the principle of this embodiment is similar to that ofembodiment 2, in embodiment 5, a signalcontrol power transistor 3 is added between a current source I and a capacitor C, the startcontrol power transistor 2 is connected to a common connection terminal of the capacitor C and the signalcontrol power transistor 3, and the signalcontrol power transistor 3 may be an NMOS transistor or a PMOS transistor.
Example 7: as shown in fig. 10, the principle of this embodiment is similar to that ofembodiment 3, and on the basis of embodiment 5, a switch control power transistor 4 (P-type MOS transistor) is added between the startcontrol power transistor 2 and the resistor R for use as a switch.
Example 8: as shown in fig. 11, the principle of this embodiment is similar to that ofembodiment 4, and a signalcontrol power transistor 3 is added between the current source I and the capacitor C based on embodiment 7.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.