CN113286174B - Video frame extraction method and device, electronic equipment and computer readable storage medium - Google Patents
Video frame extraction method and device, electronic equipment and computer readable storage mediumDownload PDFInfo
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- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
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Abstract
Description
Technical Field
The present invention relates to the field of computer vision technologies, and in particular, to a video frame extraction method and apparatus, an electronic device, and a computer-readable storage medium.
Background
In the field of computer vision, a large number of pictures are usually used as input data when a model is trained, and the pictures are often obtained by frame extraction through a large video file according to a certain strategy, such as uniform frame extraction according to time, frame skipping extraction for video compression, frame extraction according to time period, key frame extraction and the like. The traditional method is to use an open source tool to perform video frame extraction, which has some disadvantages, for example, the frame extraction efficiency is low due to insufficient utilization rate of CPU resources, so a method capable of improving the frame extraction efficiency is needed.
Disclosure of Invention
The invention provides a video frame extraction method, a video frame extraction device, electronic equipment and a computer readable storage medium, which are used for improving the frame extraction efficiency.
In order to solve the above technical problems, a first technical solution provided by the present invention is: provided is a video frame extracting method, comprising the following steps: obtaining a plurality of video groups; and performing frame extraction on the plurality of video groups in parallel by using a plurality of processing threads. And a plurality of processing threads perform frame extraction on a plurality of video groups in parallel, so that the video frame extraction efficiency is improved.
Wherein the performing the frame extraction on the plurality of video groups in parallel by using the plurality of processing threads comprises: acquiring parameter information of a video processing server; obtaining the plurality of processing threads according to the parameter information; or obtaining the plurality of processing threads according to the parameter information and the number of the plurality of video groups.
And a plurality of processing threads perform frame extraction on a plurality of video groups in parallel, so that the video frame extraction efficiency is improved.
The acquiring a plurality of video groups comprises: acquiring parameter information of a video processing server; and grouping videos according to the parameter information to obtain the plurality of video groups. The video scale is reduced, and the video frame extraction efficiency is improved.
The parameter information comprises the total core number and the total memory of the CPU of the video processing server.
The obtaining the plurality of processing threads according to the parameter information includes: and obtaining the plurality of processing threads according to the total CPU core number of the video processing server and the total memory, wherein each processing thread processes one video group by using a preset number of CPU core numbers. And the CPU is fully utilized, so that the video frame extraction efficiency is improved.
Wherein said decimating the plurality of video groups in parallel using the plurality of processing threads comprises: and carrying out one-to-one parallel corresponding processing on the plurality of video groups by utilizing a plurality of processing threads. The CPU of the video processing server side is fully utilized to improve the video frame extraction efficiency.
Each processing thread comprises a first sub thread and a second sub thread, and each processing thread comprises a register; the decimating the plurality of video groups in parallel with the plurality of processing threads comprises: performing frame extraction processing on each video group by using each first sub thread to obtain a target frame, wherein the target frame is stored in the register; acquiring the target frame from the register, and performing image processing on the target frame to form a target frame queue, wherein the target frame queue is stored in the register; and reading the corresponding target frame in the target frame queue from the register by utilizing each second sub thread, and storing the target frame in a memory. The target frame is stored in the register in the frame extraction process, the image processor GPU is used for carrying out image processing on the target frame, the target frame is written into the memory after the processing is finished, the target frame does not need to be written into the memory, and then the target frame is read from the memory for carrying out image processing, so that the IO (input/output) overhead is reduced, the video frame extraction efficiency is further improved, and the image quality is improved.
Wherein the image processing comprises at least one of image feature extraction and image rendering.
In order to solve the above technical problems, a second technical solution provided by the present invention is: provided is a video frame extracting device, comprising: an acquisition module for acquiring a plurality of video groups; and the processing module is used for performing frame extraction on the plurality of video groups in parallel by utilizing a plurality of processing threads.
In order to solve the above technical problems, a third technical solution provided by the present invention is: provided is an electronic device including: the video frame extraction method comprises a memory and a processor, wherein the memory stores program instructions, and the processor calls the program instructions from the memory to execute the video frame extraction method.
In order to solve the above technical problems, a fourth technical solution provided by the present invention is: there is provided a computer readable storage medium storing a program file executable to implement the video framing method according to any one of the above.
The invention has the beneficial effects that the invention is different from the prior art, and the invention utilizes a plurality of processing threads to perform frame extraction on a plurality of video groups in parallel, thereby improving the video frame extraction efficiency.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a flowchart illustrating a video frame extraction method according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for acquiring a processing thread according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a video frame extraction method according to a second embodiment of the present invention;
FIG. 4 is a schematic flow diagram of the embodiment of FIG. 3;
FIG. 5 is a schematic structural diagram of a video frame extracting apparatus according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the invention;
FIG. 7 is a schematic structural diagram of a storage medium according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, a schematic flow chart of a video frame extraction method according to a first embodiment of the present invention includes:
step S11: a plurality of video groups is obtained.
In one embodiment, if a larger video is to be decimated, the video may be divided into multiple video groups. Or in another embodiment, a plurality of smaller video groups are acquired directly. Specifically, parameter information of the video processing server, such as the total core count and the total memory of the CPU of the video processing server, may be obtained, a larger video is extracted based on the total core count and the total memory of the CPU of the video processing server, and the video is divided into a plurality of video groups, so that the scale of the video is reduced, and the video extraction efficiency is improved.
Step S12: multiple video groups are decimated in parallel using multiple processing threads.
Specifically, a plurality of processing threads are utilized to frame a plurality of video groups in parallel. For example, if the plurality of video sets includes video set 1, video set 2, video set 3, and video set 4. The multiple processing threads include a processing thread 1, a processing thread 2, and a processing thread 3, and the multiple processing threads may be used to perform one-to-one parallel processing on the multiple video sets, for example, the processing thread 1 may be used to perform frame extraction on the video set 1, the processing thread 2 may be used to process frame extraction on the video set 2, and the processing thread 3 may be used to perform frame extraction on the video set 3. If one of the processing threads finishes processing, for example, if the processing thread 1 finishes processing the video set 1, the video set 4 may be further read for frame extraction processing. Or, after the processing thread 1 performs frame extraction on the video group 1 and frame extraction is completed, the processing thread 2 may be further assisted to perform frame extraction on the video group 2. Alternatively, in another embodiment, if the plurality of sets of videos includes set 1, set 2, and set 3. The plurality of processing threads include processing thread 1, processing thread 2, processing thread 3, and processing thread 4. The processing thread 1 can be used for extracting frames from the video group 1, the processing thread 2 is used for processing the video group 2 for extracting frames, the processing thread 3 is used for processing the video group 3 for extracting frames, and the processing thread 4 is vacant for waiting for the next video group. Alternatively, in another embodiment, a video group equal to the number of processing threads may be further obtained. For example, a larger video is acquired, and the video is divided into the same number of video groups as the number of processing threads, so that one processing thread processes one video group. Specifically, the video is divided into a plurality of video groups, and a plurality of processing threads corresponding to the number of the video groups are obtained according to the number of the video groups and the parameter information. By the mode, the utilization rate of the CPU can be improved, and the video frame extraction efficiency is further improved.
In an embodiment, please refer to fig. 2, wherein fig. 2 is a flowchart illustrating an embodiment of an obtaining manner of a processing thread. The method comprises the following steps:
step S21: and acquiring parameter information of a video processing server.
Specifically, the video processing server may be a mobile terminal, such as a mobile phone, a notebook computer, or other intelligent devices, such as an image processing apparatus, and is not limited specifically.
The parameter information is the total core number and the total memory of the CPU of the video processing server.
Step S22: and obtaining a plurality of processing threads according to the parameter information.
Specifically, a plurality of processing threads are obtained according to the total core number and the total memory of the CPU of the video processing server. In an embodiment, the plurality of processing threads are obtained according to the total number of CPU cores of the video processing server and the total memory, and each processing thread processes one video group by using a preset number of CPU cores. For example, if the total number of cores of the CPU on the video processing server side is 56 cores and it is specified that one processing thread performs frame extraction processing on one video group by using a 4-core CPU, 14 processing threads can be obtained if the total memory is sufficient. For another example, if the total core number of the CPU at the video processing server is 56 cores, and a processing thread is specified to perform frame extraction processing on a video group by using a 4-core CPU, but the total memory is small, 8 processing threads can be obtained under the constraint of the total memory. It can be understood that the number of cores occupied by one processing thread for processing one video group is not limited, and it may also be specified that one processing thread processes one video group by using an 8-core CPU, or processes one video group by using a 10-core CPU, which is not described herein again. In one embodiment, in order to fully utilize the CPU and improve the efficiency of video framing, the number of processing threads obtained may further be made to correspond to the number of video groups. Specifically, when the processing threads are obtained, the number of the video groups is combined, for example, if the video groups are 8 groups, 8 processing threads are obtained, so that the CPU is fully utilized, and the efficiency of video frame extraction is improved.
By means of the method, the multiple processing threads are obtained according to the total core number and the total memory of the CPU of the video processing server side, and the multiple processing threads process the multiple video groups in parallel, so that the utilization rate of the CPU is improved, and the video frame extraction efficiency is improved.
Please refer to fig. 3, which is a flowchart illustrating a video frame extraction method according to a second embodiment of the present invention, in which each processing thread includes a first sub-thread and a second sub-thread, and a difference between the first embodiment shown in fig. 1 and the second embodiment is that, in this embodiment, step S12 specifically includes:
step S31: and performing frame extraction processing on each video group by using each first sub thread to obtain a target frame.
Referring to fig. 4, for example, in an embodiment, the current processing thread performs frame extraction processing on the video group 1, and specifically, the first sub-thread performs frame extraction on the video group. In order to reduce the amount of computation, frame skipping processing may be performed according to a predetermined rule to perform frame extraction to obtain a target frame. In one embodiment, the partial image frames may be extracted as target frames within a predetermined period of time, for example, the partial image is extracted within the first 3 seconds, the partial image is extracted within the second 3 seconds, the partial image is extracted within the 3 rd three seconds, and the extracted image is used as the target frame. Alternatively, in another embodiment, if the video group has 100 frames of images, a single frame of images may be selected as the target frame. Or, each fixed frame number may also be selected as a target frame, for example, 1-5 frames, 10-15 frames, 20-25 frames are selected as target frames, which is not limited specifically. In one embodiment, each processing thread includes a register into which the target frame is stored, the register being an integral part of the central processing unit. Registers are high-speed memory components of limited storage capacity that may be used to temporarily store instructions, data, and addresses.
Step S32: and acquiring the target frame from the register, and performing image processing on the target frame to form a target frame queue.
Specifically, the target frame is obtained from the register, and image processing is performed on the target frame to form a target frame queue. In one embodiment, an image Processing function of a Graphics Processing Unit (GPU) may be invoked to image process the target stored in the register to form a target frame queue. The image processing comprises image feature extraction, image rendering, image clustering and other operations on the target frame. The target frame queue is stored in a register.
In the prior art, when a CPU performs frame extraction, image operation cannot be directly performed on an extracted target frame, the extracted target frame needs to be stored in a memory first, and then the target frame is read from the memory and subjected to image operation by using an image processor GPU, so that IO overhead is increased, and when a high-quality image is output, time consumption is increased.
According to the method and the device, after the target frame is extracted by the first sub-thread, the target frame can be stored in the register, the image processor GPU is used for carrying out image operation on the target frame stored in the register to obtain the target frame queue, the target frame does not need to be written into the memory, IO (input/output) expenses are reduced, and image processing efficiency and image quality are improved.
Step S33: and reading the target frame in the corresponding target frame queue from the register by using each second sub thread, and storing the target frame in the memory.
And reading the target frames in the corresponding target frame queue from the register by using the second sub thread, and storing the target frames in the memory. Specifically, when reading a target frame from a target frame queue, a first-in first-out principle needs to be adopted, for example, a target frame obtained by frame extraction of a first sub-thread is a target frame 1, a target frame 2, a target frame 3, a target frame 4 \8230, an object frame 8230, a target frame n, a target frame currently extracted by the first sub-thread is a target frame n +1, and when reading from the target frame queue, a second sub-thread is read according to the sequence of the target frame 1, the target frame 2, the target frame 3, the target frame 4 \8230, the object frame 8230, the object frame n and the target frame n + 1. The memory is the memory of the video processing server.
In another embodiment, to further compress the frame drawing time, the first sub thread and the second sub thread may work simultaneously, for example, during the frame drawing of the first sub thread, the second sub thread may read the target frame from the target frame queue and write into the memory simultaneously.
According to the video frame extraction method provided by the invention, a plurality of processing threads are obtained through the total core number and the total memory of the CPU of the video processing server side, and the plurality of processing threads process a plurality of video groups in parallel, so that the utilization rate of the CPU is improved, and the video frame extraction efficiency is improved. Each processing thread comprises a first sub thread and a second sub thread, the first sub thread performs frame extraction processing on each video group to obtain a target frame, the target frame is stored in a register, the target frame is directly obtained from the register, image processing is performed on the target frame by using an image processing function of a Graphics Processing Unit (GPU) to form a target frame queue, the second sub thread reads the target frame from the target frame queue in the register and stores the target frame in a memory, the target frame does not need to be written into the memory, and the image processing is performed by reading the target frame from the memory by using the GPU. In the mode of the embodiment, the image processor GPU can be directly utilized to perform image processing on the target frame in the frame extraction process, so that IO (input/output) overhead is reduced, time consumption is reduced, and video frame extraction efficiency and image quality are further improved.
Referring to fig. 5, which is a schematic structural diagram of a video frame extracting apparatus according to an embodiment of the present invention, the video frame extracting apparatus includes an obtainingmodule 51 and aprocessing module 52.
The obtainingmodule 51 is configured to obtain a plurality of video groups. In one embodiment, if a larger video is to be decimated, the video may be divided into multiple video groups. Or in another embodiment, a plurality of smaller video groups are directly acquired. Specifically, the obtainingmodule 51 may obtain parameter information of the video processing server, such as the total number of CPU cores and the total memory of the video processing server, perform frame extraction on a larger video based on the total number of CPU cores and the total memory of the video processing server, and divide the video into a plurality of video groups, so as to reduce the video size and improve the video frame extraction efficiency.
In an embodiment, the obtainingmodule 51 is further configured to obtain parameter information of the video processing server, and obtain multiple processing threads according to the parameter information.
Specifically, a plurality of processing threads are obtained according to the total core number and the total memory of the CPU of the video processing server. In an embodiment, the plurality of processing threads are obtained according to a total number of CPU cores of the video processing server and the total memory, and each processing thread processes one video group by using a preset number of CPU cores. For example, if the total number of cores of the CPU on the video processing server side is 56 cores and it is specified that one processing thread performs frame extraction processing on one video group by using a 4-core CPU, 14 processing threads can be obtained if the total memory is sufficient. For another example, if the total number of cores of the CPU at the video processing server side is 56 cores, and it is specified that one processing thread performs frame extraction processing on one video group by using a 4-core CPU, but the total memory is small, 8 processing threads can be obtained under the constraint of the total memory. It can be understood that the number of cores occupied by one processing thread for processing one video group is not limited, and it may also be specified that one processing thread uses an 8-core CPU to process one video group, or uses a 10-core CPU to process one video group, which is not described herein again. In one embodiment, in order to fully utilize the CPU and improve the efficiency of video framing, the number of processing threads obtained may further be made to correspond to the number of video groups. Specifically, when the processing threads are obtained, the number of the video groups is combined, for example, if the video groups are 8 groups, 8 processing threads are obtained, so that the CPU is fully utilized, and the efficiency of video frame extraction is improved.
By means of the method, the multiple processing threads are obtained according to the total core number and the total memory of the CPU of the video processing server side, and the multiple processing threads process the multiple video groups in parallel, so that the utilization rate of the CPU is improved, and the video frame extraction efficiency is improved.
Theprocessing module 52 is configured to frame multiple video groups in parallel using multiple processing threads. In particular, the method comprises the following steps of,
if the plurality of video groups include video group 1, video group 2, video group 3, and video group 4. The plurality of processing threads include a processing thread 1, a processing thread 2, and a processing thread 3, and the plurality of processing threads may be used to perform one-to-one parallel corresponding processing on the plurality of video groups, for example, the processing thread 1 may be used to perform frame extraction on the video group 1, the processing thread 2 may be used to process the video group 2 to perform frame extraction, and the processing thread 3 may be used to process the video group 3 to perform frame extraction. If one of the processing threads finishes processing, for example, if the processing thread 1 finishes processing the video set 1, the video set 4 may be further read for frame extraction. Or, after the processing thread 1 performs frame extraction on the video group 1 and frame extraction is completed, the processing thread 2 may further assist in performing frame extraction on the video group 2. Alternatively, in another embodiment, if the plurality of video groups includes video group 1, video group 2, and video group 3. The plurality of processing threads include processing thread 1, processing thread 2, processing thread 3, and processing thread 4. The processing thread 1 can be used for extracting frames from the video group 1, the processing thread 2 is used for processing the video group 2 for extracting frames, the processing thread 3 is used for processing the video group 3 for extracting frames, and the processing thread 4 is vacant for waiting for the next video group. Alternatively, in another embodiment, a video group equal to the number of processing threads may be further obtained. For example, a larger video is acquired, and the video is divided into the same number of video groups as the number of processing threads, so that one processing thread processes one video group. Specifically, the video is divided into a plurality of video groups, and a plurality of processing threads corresponding to the number of the video groups are obtained according to the number of the video groups and the parameter information. By the mode, the utilization rate of the CPU can be improved, and the video frame extraction efficiency is further improved.
In an embodiment, theprocessing module 52 is further configured to perform frame extraction processing on each video group by using each first sub-thread to obtain a target frame, where the target frame is stored in a register, obtain the target frame from the register, perform image processing on the target frame to form a target frame queue, where the target frame queue is stored in the register, and use each second sub-thread to read the target frame in the corresponding target frame queue from the register and store the target frame in the memory.
In particular, the method comprises the following steps of,
specifically, the first sub-thread performs frame extraction on the video group. In order to reduce the amount of computation, frame skipping processing may be performed according to a predetermined rule to perform frame extraction to obtain a target frame. In one embodiment, the partial image frames may be extracted as target frames within a predetermined period of time, for example, the partial image is extracted within the first 3 seconds, the partial image is extracted within the second 3 seconds, the partial image is extracted within the 3 rd three seconds, and the extracted image is used as the target frame. Alternatively, in another embodiment, if the video group has 100 frames of images, a single frame of image may be selected as the target frame. Or, each fixed frame number may also be selected as a target frame, for example, 1-5 frames, 10-15 frames, 20-25 frames are selected as target frames, which is not limited specifically. In one embodiment, each processing thread includes a register into which the target frame is stored, the register being an integral part of the central processing unit. Registers are high-speed storage elements of limited storage capacity that may be used to temporarily store instructions, data, and addresses. Specifically, the target frame is obtained from the register, and image processing is performed on the target frame to form a target frame queue. In one embodiment, an image Processing function of a Graphics Processing Unit (GPU) may be invoked to image process the target objects stored in the registers to form a target frame queue. The image processing comprises the operations of image feature extraction, image rendering, image clustering and the like on the target frame. The target frame queue is stored in a register.
In the prior art, when a CPU performs frame extraction, image operation cannot be directly performed on an extracted target frame, the extracted target frame needs to be stored in a memory first, and then the target frame is read from the memory and subjected to image operation by using an image processor GPU, so that IO overhead is increased, and when a high-quality image is output, time consumption is increased.
According to the method, after the target frame is extracted by the first sub-thread, the target frame can be stored in the register, the image processor GPU is used for carrying out image operation on the target frame stored in the register to obtain the target frame queue, the target frame does not need to be written into the memory, IO (input/output) expenditure is reduced, and image processing efficiency and image quality are improved.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the invention. The electronic device comprises amemory 202 and aprocessor 201 connected to each other.
Thememory 202 is used to store program instructions for implementing the video framing method of the apparatus of any of the above.
Theprocessor 201 is used to execute program instructions stored by thememory 202.
Theprocessor 201 may also be referred to as a Central Processing Unit (CPU). Theprocessor 201 may be an integrated circuit chip having signal processing capabilities. Theprocessor 201 may also be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Thestorage 202 may be a memory bank, a TF card, etc., and may store all information in the electronic device of the device, including the input raw data, the computer program, the intermediate operation results, and the final operation results. It stores and retrieves information based on the location specified by the controller. With the memory, the electronic device can only guarantee normal operation if it has memory function. The memory of the electronic device is classified into a main memory (internal memory) and an auxiliary memory (external memory) according to the use, and also classified into an external memory and an internal memory. The external memory is usually a magnetic medium, an optical disk, or the like, and can store information for a long period of time. The memory is a storage unit on the motherboard, which is used for storing data and programs currently being executed, but is only used for temporarily storing the programs and the data, and the data is lost when the power is turned off or the power is cut off.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, which are essential or contributing to the prior art, or all or part of the technical solutions may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a system server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present application.
Fig. 7 is a schematic structural diagram of a computer-readable storage medium according to the present invention. The storage medium of the present application stores aprogram file 203 capable of implementing all the above-mentioned video frame extraction methods, where theprogram file 203 may be stored in the storage medium in the form of a software product, and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present application. The foregoing storage device includes: various media capable of storing program codes, such as a usb disk, a mobile hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, or terminal devices, such as a computer, a server, a mobile phone, and a tablet.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A method for video framing, comprising:
obtaining a plurality of video groups and a plurality of processing threads; each processing thread comprises a first sub thread and a second sub thread, and each processing thread further comprises a register;
performing one-to-one parallel frame extraction processing on the video groups by using a plurality of first sub-threads corresponding to the processing threads, wherein after processing of part of the video groups is completed, the corresponding first sub-threads assist in processing other unfinished video groups to perform frame extraction so as to obtain corresponding target frames, and storing the target frames in corresponding registers;
acquiring the target frame from the corresponding register, and performing image processing on the target frame to form a target frame queue, wherein the target frame queue is stored in the corresponding register;
and reading the target frame in the corresponding target frame queue from the corresponding register by using the plurality of second sub threads, and storing the target frame in a memory.
2. The method according to claim 1, wherein the performing, by using a plurality of first sub-threads corresponding to a plurality of processing threads, one-to-one parallel frame extraction processing on a plurality of video groups, and when some of the video processing is completed, the corresponding first sub-threads assist in processing other unfinished video groups to perform frame extraction to obtain corresponding target frames, and before storing the target frames in corresponding registers, comprises:
acquiring parameter information of a video processing server;
obtaining the plurality of processing threads according to the parameter information; or alternatively
And obtaining the plurality of processing threads according to the parameter information and the number of the plurality of video groups.
3. The method of claim 1, wherein obtaining the plurality of video groups comprises:
acquiring parameter information of a video processing server;
and grouping videos according to the parameter information to obtain the plurality of video groups.
4. The method according to any one of claims 2 to 3, wherein the parameter information includes a total core count of CPUs and a total memory of the video processing server.
5. The method of claim 4, wherein the deriving the plurality of processing threads according to the parameter information comprises:
and obtaining the plurality of processing threads according to the total CPU core number of the video processing server and the total memory, wherein each processing thread processes one video group by using a preset number of CPU core numbers.
6. The method of claim 1, wherein the image processing comprises at least one of image feature extraction and image rendering.
7. A video framing apparatus, comprising:
the device comprises an acquisition module, a processing module and a display module, wherein the acquisition module is used for acquiring a plurality of video groups and a plurality of processing threads; each processing thread comprises a first sub thread and a second sub thread, and each processing thread further comprises a register;
the processing module is used for performing one-to-one corresponding parallel frame extraction processing on the video groups by utilizing a plurality of first sub-threads corresponding to the processing threads, and when part of the video processing is completed, the corresponding first sub-threads assist in processing other unfinished video groups for frame extraction to obtain corresponding target frames and store the target frames in corresponding registers; acquiring the target frame from the corresponding register, and performing image processing on the target frame to form a target frame queue, wherein the target frame queue is stored in the corresponding register; and reading the target frame in the corresponding target frame queue from the corresponding register by using the plurality of second sub threads, and storing the target frame in a memory.
8. An electronic device comprising a memory and a processor, wherein the memory stores program instructions, and the processor retrieves the program instructions from the memory to perform the video framing method of any of claims 1-6.
9. A computer-readable storage medium, in which a program file is stored, the program file being executable to implement the video framing method according to any one of claims 1 to 6.
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| CN116389719B (en)* | 2023-06-07 | 2023-08-15 | 安元科技股份有限公司 | Video analysis frame extraction and inspection optimization system and method based on polling frame extraction |
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