Detailed Description
The following describes in detail the test structure and the specific embodiments of the test method provided by the invention with reference to the accompanying drawings.
Please refer to fig. 1, which is a schematic diagram of a test structure according to an embodiment of the present invention.
The test structure includes a first sub-test structure 110 and a second sub-test structure 120.
The first sub-test structure 110 includes: a first series structure 111, the first series structure 111 comprising a first heater 1111 and a first phase change layer 1112 on a top surface of the first heater 1111. The first series structure 111 corresponds to the phase change layer and the heater in the memory cell of the phase change memory to be tested, and the resistance of the heater in the corresponding memory cell can be obtained by testing the resistance of the heater 1111 in the first sub-test structure 110. Because in the phase change memory, the top of the phase change layer is provided with the upper electrode; correspondingly, in this embodiment, in the first serial structure 111, a first upper electrode 113 is also formed on top of the first phase change layer 1112.
The second sub-test structure 120 includes: a second series structure 121, the second series structure 121 including a second heater 1211, and a second phase change layer 1212 on a top surface of the second heater 1211. A second upper electrode 123 is further formed on top of the second phase change layer 1212.
The phase change layer and the heater within the first and second sub-test structures 110 and 120 are connected in series. Compared to the resistance values of the phase-change layer and the heater, the resistance values of the electrode and the electrical connection line are extremely small, and the first resistance value r1=rGTS1+RCH1 of the first sub-test structure 110 is the resistance value of the first phase-change layer 1112, and RCH1 is the resistance value of the first heater 1111 without considering the resistance values of the electrical connection line and the electrode; the second resistance value r2=rGTS2+RCH2 of the second sub-test structure 120, where RGTS2 is the resistance value of the second phase-change layer 1212, and RCH2 is the resistance value of the second heater 1211.
Wherein, the resistance of the second phase-change layer 1212 is the same as that of the first phase-change layer 1112, i.e. RGTS1＝RGTS2. Then R1-r2= (RGTS1+RCH1)-(RGTS2+RCH2)＝RCH1-RCH2, the ratio of the resistance value of the second heater 1211 to the resistance value of the first heater 1111 is controlled to be smaller than a set value, so that the resistance value RCH2 of the second heater 1211 is much smaller than the resistance value RCH1 of the first heater 1111, i.e., RCH2＜＜RCH1. Therefore, at RGTS1＝RGTS2, R1-r2=rCH1-RCH2≈RCH1. By testing the resistance values of the first and second series structures 111 and 121, a resistance value similar to the first heater 1111 can be obtained, so that the resistance value RCH1 of the first heater 1111 can be easily analyzed for characteristics during the phase change memory process through the design of the first and second sub-test structures 110 and 120.
The set value may range from 10 to 100. As can be seen from the formula r=ρ×l/a of the resistance, the ratio of the resistances can be controlled by controlling the ratio of the cross-sectional areas of the first heater 1111 and the second heater 1211, where ρ is the resistivity, L is the current flow path length of the resistor to be measured, and a is the cross-section of the resistor to be measured. In other specific embodiments, the set value may be set reasonably according to the accuracy requirement of the test.
The second heater 1211 is generally cylindrical in shape, and has a resistance determined by the cross-sectional area of the second heater 1211, and in particular, by the contact area of the second heater 1211 with the second phase change layer 1212. To minimize the resistance of second heater 1211, the projection of second phase change layer 1212 onto the top surface of second heater 1211 is positioned within the top surface of second heater 1211. In this embodiment, the top surface of the second heater 1211 is sized to conform to the dimensions of the second phase change layer 1212 such that the entire top of the second heater 1211 is in contact with the second phase change layer 1212. In other embodiments, to enable the second phase change layer 1212 to fully contact the second heater 1211 surface due to possible alignment errors, the second heater 1211 top surface dimension may also be slightly larger than the second phase change layer 1212 bottom surface dimension such that the second phase change layer 1212 can fully reside within the second heater 1211 top surface region.
By inputting a first test current I1 flowing through the first series structure 111 into the first sub-test structure 110 and obtaining a voltage difference V1 across the first series structure 111, a first resistance R1 can be obtained; by inputting a second test current I2 flowing through the second series structure 121 into the second sub-test structure 120 and obtaining a voltage difference V2 across the second series structure 121, a second resistance R2 can be obtained; further, the resistance RCH1 of the first heater 1111 is calculated.
In this embodiment, in order to ensure uniformity of electrical parameters between other components except for the first heater 1111 and the second heater 1211 in the first sub-test structure 110 and the second sub-test structure 120, the first sub-test structure 110 and the second sub-test structure 120 are formed on the same surface of the substrate 100, and the corresponding components are distributed in the same layer and are formed simultaneously by the same process. The first phase change layer 1112 and the second phase change layer 1212 are made of the same material and have the same dimensions, so that the resistance values of the first phase change layer 1112 and the second phase change layer 1212 are the same or almost the same within a reasonable range of process errors. Preferably, in order to keep the first serial structure 111 in the first sub-test structure 110 consistent with the phase change layer and the heater structure and the size in the actual phase change memory cell, the test structure may be formed on the same substrate in synchronization with the target memory cell to be tested, and only the size of the second heater 1212 in the second sub-test structure 120 is required to be larger than the sizes of the first heater 1111 and the heater of the memory cell in the first sub-test structure 110 during the process of performing the heater.
In order to facilitate the test, the test structure further comprises a test terminal for inputting and outputting test signals. Specifically, the first subtest structure 110 further includes: a first input terminal 115 and a first output terminal 116 electrically connected to both ends of the first series structure 111, respectively, for inputting and outputting a first test current I1, respectively; the second sub-test structure 120 further includes a second input terminal 125 and a second output terminal 126 electrically connected to both ends of the second series structure 121, for inputting and outputting the first test current I2, respectively. The electrical connection may be achieved by electrical connection lines and conductive vias.
In this embodiment, the first sub-test structure 110 and the second sub-test structure 120 are both formed on the substrate 100. The base 100 may include a semiconductor substrate and a dielectric layer formed on a surface of the semiconductor substrate, and a semiconductor device such as a transistor may be formed in the semiconductor substrate. A bottom metal layer M0 is formed on the surface of the substrate 100, and the bottom metal layer M0 includes an electrical connection wire, an electrode, and the like; the substrate 100 further has a dielectric layer 101 formed thereon, and the first series structure 111 and the second series structure 121 are both formed in the dielectric layer 101. The dielectric layer 101 has an upper metal layer M1 formed thereon, and the first input terminal 115 and the first output terminal 116, and the second input terminal 125 and the second output terminal 126 are located in the upper metal layer M1. In other embodiments, the first and second series structures 111 and 121 may be formed between any two metal layers within the dielectric layer.
Specifically, the bottom metal layer M0 has a first bottom electrode 112 and a second bottom electrode 122 formed therein. The first heater 1111 is formed on the surface of the first bottom electrode 112, the first phase change layer 1112 is formed on top of the first heater 1111, and the cross-sectional area of the first heater 1111 is smaller and only contacts with a local area of the first phase change layer 1112; a first upper electrode 113 is formed on top of the first phase change layer 1112, and the first upper electrode 113 covers the entire top surface of the first phase change layer 1112 in order to reduce the resistance of the first upper electrode 113. The first input end 115 and the first output end 116 of the first sub-test structure 110 are formed on the surface of the dielectric layer 101, and are used for connecting with external electrical signals. Specifically, the first input terminal 115 is connected to the first upper electrode 113 through a first conductive via 114, and the first conductive via 114 penetrates a portion of the dielectric layer 101 to be connected to the first upper electrode 113. The first output terminal 116 is electrically connected to the first bottom electrode 112 through a second conductive via 117 penetrating the dielectric layer 101, and thus, the first sub-test structure 110 includes a first input terminal 115, a first conductive via 114, a first upper electrode 113, a first phase change layer 1112, a first heater 1111, a first bottom electrode 112, a second conductive via 117, and a first output terminal 116 connected in sequence, constituting a serial path. In the series path, the first input terminal 115, the first conductive via 114, the first upper electrode 113, the first bottom electrode 112, the second conductive via 117, and the first output terminal 116 are used as electrical connection lines, and have a small resistance. A first test current I1 is input into the first sub-test structure 110 through the first input terminal 115 and output from the first output terminal 116, a current path is formed, and a first resistance value R1 of the first sub-test structure 110 can be measured according to a voltage difference between the first input terminal 115 and the first output terminal 116, where RL1 is a resistance of an electrical connection line in the first sub-test structure 110.
The second heater 1211 is formed on the surface of the second bottom electrode 122, the second phase-change layer 1212 is formed on top of the second heater 1211, and the second upper electrode 123 is formed on top of the second phase-change layer 1212, and the second upper electrode 123 covers the entire top surface of the second phase-change layer 1212 in order to reduce the resistance of the second upper electrode 123. The first input end 125 and the second output end 126 of the second sub-test structure 120 are formed on the surface of the dielectric layer 101, and are used for connecting with external electrical signals. Specifically, the second input terminal 125 is connected to the second upper electrode 123 through a third conductive via 124, and the third conductive via 124 penetrates a portion of the dielectric layer 101 to be connected to the second upper electrode 123. The second output terminal 126 is electrically connected to the second bottom electrode 122 through a fourth conductive via 127 penetrating the dielectric layer 101, whereby the second sub-test structure 120 includes a second input terminal 125, a third conductive via 124, a second upper electrode 123, a second phase change layer 1212, a second heater 1211, a second bottom electrode 122, a fourth conductive via 127, and a second output terminal 126, which are sequentially connected, constituting a serial path. In the series path, the second input terminal 125, the third conductive via 124, the second upper electrode 123, the second bottom electrode 122, the fourth conductive via 127, and the second output terminal 126 are used as electrical connection lines, and the resistance is small. A second test current I2 is input into the second sub-test structure 120 through the second input terminal 125 and output from the second output terminal 126, a current path is formed, and a second resistance value R2 of the second sub-test structure 120 can be measured according to a voltage difference between the second input terminal 125 and the second output terminal 126, where the second resistance value r2=rGTS2+RCH2+RL2≈RGTS2+RL2.
Only the first heater 1111 and the second heater 1211 are different in size from each other in the first sub-test structure 110 and the second sub-test structure 120, and other components, electrical connection structures and electrical parameters are consistent, so that the resistance value of the first heater, i.e. r1—r2=rCH1-RCH2≈RCH1, can be obtained by calculating the difference between the first resistance value and the second resistance value. RL1＝RL2 in the case of a consistent background condition.
Referring to fig. 2, a schematic top view of a test structure according to an embodiment of the invention is shown.
The test structure includes a first sub-test structure 210 and a second sub-test structure 220.
The first sub-test structure 210 includes a first bottom electrode 211 in an underlying metal layer, a first heater 212 formed on the first bottom electrode 211, and a first phase change layer 213 and a first upper electrode (not shown) on a surface of the first phase change layer 213 on the first heater 212. The first input terminal 215 is located in the upper metal layer and is electrically connected to the first phase change layer 213 through an electrical connection 214 and a conductive via (not shown) in the upper metal layer. The first bottom electrode 211 is connected to the electrical connection line 216 located in the upper metal layer through a conductive via 2110 and to said first output terminal 217 through said electrical connection line 216. In this embodiment, the first phase-change layer 213 of the first sub-test structure 110 is further electrically connected to the first input voltage sensing terminal 218 in the upper metal layer, and the first bottom electrode 211 is further connected to the first output voltage sensing terminal 219 in the upper metal layer through the conductive via 2111. The first input voltage sensing terminal 218 is closer to the first phase-change layer 213, and the voltages at the two ends of the first series structure formed by the first phase-change layer 213 and the first heater 212 are obtained through the first output voltage sensing terminal 219 and the first input voltage sensing terminal 218, respectively. Because of the process errors, the resistances of the electrical connection lines in the first sub-test structure 210 and the second sub-test structure 220 are difficult to be identical, and the resistance values obtained by the voltage differences between the first output voltage sensing terminal 219 and the first input voltage sensing terminal 218 and the first test current I1 are closer to the series resistances of the first phase-change layer 213 and the first heater 212, so that the influence of the electrical connection lines on the measurement result can be reduced.
The second sub-test structure 220 includes a second bottom electrode 221 in the underlying metal layer, a second heater 222 formed on the second bottom electrode 221, and a second upper electrode (not shown) on the first phase change layer 223 and its surface on the second heater 222. The second input terminal 225 is located in the upper metal layer and is electrically connected to the second phase change layer 223 via an electrical connection line 224 and a conductive via (not shown) in the upper metal layer. The second bottom electrode 221 is connected to an electrical connection line 226 located in the upper metal layer through a conductive via 2210, and is connected to the second output terminal 227 through the electrical connection line 226. In this embodiment, the second phase change layer 223 of the second sub-test structure 220 is further electrically connected to the second input voltage sensing terminal 228 in the upper metal layer, and the second bottom electrode 221 is further connected to the second output voltage sensing terminal 229 in the upper metal layer through a conductive via 2211. The second input voltage sensing terminal 228 is closer to the second phase-change layer 223, and the voltages at two ends of the second series structure formed by the second phase-change layer 223 and the second heater 222 are obtained through the second output voltage sensing terminal 229 and the second input voltage sensing terminal 228, respectively.
The second sub-test structure 220 differs from the first sub-test structure 210 only in the cross-sectional area dimensions of the first heater 212 and the second heater 222, and the other structures are identical.
Referring to fig. 3, a schematic top view of a test structure according to an embodiment of the invention is shown.
The test structures include a first sub-test structure 310 and a second sub-test structure 320.
In this embodiment, the first input terminal 315 of the first sub-test structure 310 and the electrical connection line 314 connected to the first phase change layer 313 are both located in the upper metal layer; the first output terminal 317 is located in the upper metal layer and is connected to the first bottom electrode 311 through an electrical connection line 316 located in the lower metal layer, and an interlayer interconnection is formed between the first bottom electrode 311 and the second output terminal 317 through a conductive via 3110 penetrating the dielectric layer. The first phase change layer 313 of the first sub-test structure 310 is also electrically connected to a first input voltage sensing terminal 318 in an upper metal layer, and the first bottom electrode 311 is also connected to a first output voltage sensing terminal 319 in the upper metal layer through a conductive via 3111.
The structure of the second sub-test structure 320 is consistent with that of the first sub-test structure 320, and the second input terminal 325 of the second sub-test structure 320 and the electrical connection line 324 connected to the second phase change layer 323 are all located in the upper metal layer; and the second output terminal 327 is located in the upper metal layer and is connected to the second bottom electrode 321 through an electrical connection line 326 located in the lower metal layer, and an interlayer interconnection is formed between the second bottom electrode 321 and the second output terminal 327 through a conductive via 3210 penetrating through the dielectric layer. The second phase change layer 323 of the second sub-test structure 320 is further electrically connected to a second input voltage sensing terminal 328 in the upper metal layer, and the second bottom electrode 321 is further connected to a second output voltage sensing terminal 329 in the upper metal layer through a conductive via 3211.
Referring to fig. 4, a schematic top view of a test structure according to another embodiment of the invention is shown.
In this embodiment, the first subtest structure 410 and the second subtest structure 420 share the same input 400, and the input 400 is used as both the first input of the first subtest structure 410 and the second input of the second subtest structure 420. The input terminal 400 is located in the upper metal layer and is connected to the first phase change layer 313 by an electrical connection 314 and to the second phase change layer 323 by an electrical connection 324.
In other embodiments, the first sub-test structure and the second sub-test structure may also have corresponding input terminals, respectively, and share output terminals.
In other specific embodiments, those skilled in the art may set appropriate electrical connection lines in the bottom metal layer and the upper metal layer according to actual wiring requirements, and connect the series structure formed by the phase change layer and the heater in the subtest structure to the input end and the output end respectively to form a test loop.
The test structure of the specific embodiment comprises a first sub-test structure and a second sub-test structure with the same structure, wherein the resistance of the heater in the first sub-test structure is the resistance to be tested, and the resistance of the heater in the second sub-test structure is far smaller than the resistance of the heater in the first sub-test structure, so that the resistance to be tested of the heater in the first sub-test structure can be obtained by respectively measuring the resistance of the two sub-test structures and calculating the difference value.
The specific embodiment of the invention also provides a testing method for testing the resistance of the heater in the phase-change memory cell.
In one embodiment, the test method comprises the steps of:
step 1: a test structure as described in the above detailed description is provided.
In this embodiment, the test structure is shown in fig. 1, and will not be described herein.
Step 2: and acquiring a first resistance value corresponding to the first sub-test structure, wherein the first resistance value at least comprises a series resistance value of the first phase-change layer and the first heater.
Specifically, a first test current I1 is input into the first series structure 111 through the first input terminal 115 and flows out from the first output terminal 116, so as to form a current path, and a first resistance value r1=v1/I1 is obtained through the voltage difference V1 between the first input terminal 115 and the first output terminal 116 and the first test current I1. The first resistance value R1 includes a series resistance value of the first phase change layer 1112 and the first heater 1111 and an electrical connection line.
A second resistance value r2=v2/I2 is obtained by inputting a second test current I2 into the second series structure 121 through the second input terminal 125 and flowing out from the second output terminal 126, forming a current path, and by the voltage difference V2 between the second input terminal 125 and the second output terminal 126, and the first test current I2. The second resistance value R2 includes a series resistance value of the second phase change layer 1212 and the second heater 1211 and an electrical connection line.
Step 3: and calculating a difference value between the first resistance value R1 and the second resistance value R2, and taking the difference value as the resistance value of the first heater.
Since the resistance of the second heater 1211 within the second sub-test structure 120 is much less than the resistance of the first heater 1111 within the first sub-test structure 110; and the electrical connection line structures in the first sub-test structure 110 and the second sub-test structure 120 are identical, and the resistances are the same or have smaller differences, so that the difference between the first resistance value R1 and the second resistance value R2 is equal to the resistance value of the first heater 1111.
Further, in the test process, the first test current I1 and the second test current I2 may be the same, so as to reduce a test error caused by different test currents.
Since the test current passes through the first and second heaters 1111 and 1211, heat is generated, and the first and second phase change layers 1112 and 1212 are heated to some extent. Since the resistances of the first heater 1111 and the second heater 1211 are different, the amounts of heat generated by the two may be different, so as to avoid the difference of the generated amounts of heat from causing the resistances of the first phase change layer 1112 and the second phase change layer 1212 to be different, and the test current is controlled to be less than the current threshold for causing the resistance of the first phase change layer and the second phase change layer to be changed during the test. Preferably, the test current range is controlled so that the current density (current density) flowing into the phase-change layer is 10-20 MA/cm2 or less.
Therefore, according to the testing method, the resistance value of the heater of the memory unit can be obtained only by respectively acquiring the resistance values of the two sub-test structures in the test structure, and the resistance value is irrelevant to the resistance value of the phase-change layer, so that the heating effect of the operating current in the memory unit on the phase-change layer can be accurately reflected, and more accurate current control on the memory unit is facilitated.
In other embodiments of the present invention, in order to further eliminate the influence of the resistance of the electrical connection line on the measurement result, only the voltage difference between the two ends of the series structure formed by the phase change layer and the heater in the sub-test structure may be further obtained. In one embodiment, the test structure shown in fig. 2 may be used, and when the first test current flows through the first sub-test structure 210 through the first input voltage sensing terminal 218 and the first output voltage sensing terminal 219, a voltage difference V1' between two ends of the series structure formed by the first phase change layer 213 and the first heater 212 is obtained, and since the first input voltage sensing terminal 218 and the first output voltage sensing terminal 219 are closer to the first phase change layer 213 and the first heater 212 in circuit, no current flows on the voltage sensing terminals 218 and 219, so as to eliminate a voltage drop effect. Therefore, the series resistance value of the first heater 212 and the first phase change layer 213 can be more accurately obtained, and the influence of the resistance value of the longer electrical connection line between the first input terminal 215 and the first output terminal 217 can be eliminated.
Likewise, the voltage difference V2' across the series arrangement of the second phase change layer 223 and the second heater 222 may be obtained through the second output voltage sensing terminal 228 and the second output voltage sensing terminal 229 within the second sub-test structure 220.
In the above embodiment, the resistance RCH1 =v1 '/I1-V2'/I2 of the first heater 212.
In another embodiment, the test structure shown in FIG. 4 may be employed. Since the first sub-test structure 410 and the second sub-test structure 420 of the test structure share one input terminal 400, when a first test current I1 is input to the input terminal 400 during a test, the second output terminal 327 needs to be kept floating, so that a current path cannot be formed in the second sub-test structure 420, and the first test current I1 passes through only the first sub-test structure 410. Also, when the second test current I2 is input to the input terminal 400, the first output terminal 317 needs to be kept off, so that a current path cannot be formed in the first sub-test structure 410, and the second test current I2 passes through only the second sub-test structure 420.
In other embodiments, if the first test structure and the second test structure in the test structure respectively have input ends and share output ends, only the input ends of one sub-test structure are input with test current at a time, so that a current path cannot be formed in the other sub-test structure.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.