CN113257327A - Memory device and layout and manufacturing method thereof - Google Patents

Abstract

The invention discloses a memory device, a layout thereof and a manufacturing method thereof. The memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from each other along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled in series to the first transistor. The second transistor includes one or more second semiconductor nanostructures spaced apart from each other along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

Description

Memory device and layout and manufacturing method thereof

Technical Field

Embodiments of the invention relate to a memory device and a layout and manufacturing method thereof.

Background

Integrated Circuits (ICs) sometimes include one-time programmable (OTP) memory to provide non-volatile memory (NVM) that does not lose data when the IC is powered down. One type of OTP device includes an antifuse memory. An antifuse memory includes a plurality of antifuse memory cells (or bitcells) whose terminals are opened prior to programming and shorted (e.g., connected) after programming. The antifuse memory may be based on Metal Oxide Semiconductor (MOS) technology. For example, an antifuse memory cell may include a programming MOS transistor (or MOS capacitor) and at least one read MOS transistor. The gate dielectric of the programming MOS transistor may be broken down to interconnect the gate and source or drain subcomponents of the programming MOS transistor. Depending on whether the gate dielectric of the programming MOS transistor is broken down, the anti-fuse memory cell may present different data bits by reading the combined current flowing through the programming MOS transistor and the reading MOS transistor. The antifuse memory has the advantageous feature of reverse engineering verification because the programmed state of the antifuse cell cannot be determined by reverse engineering.

Disclosure of Invention

According to an aspect of the present invention, there is provided a memory device including: a first transistor comprising: one or more first semiconductor nanostructures spaced apart from one another along a first direction, each of the one or more first semiconductor nanostructures having a first width along a second direction perpendicular to the first direction; and a second transistor coupled in series to the first transistor, comprising: one or more second semiconductor nanostructures spaced apart from each other along the first direction, each of the one or more second semiconductor nanostructures having a second, different width along the second direction.

According to another aspect of the present invention, there is provided a memory device layout comprising: a first component comprising a first sub-component and a second sub-component, the first sub-component configured to define a source and a drain of the first transistor and the second sub-component configured to define a source and a drain of the second transistor, wherein the first sub-component extending in the first direction has a first width in a second direction perpendicular to the first direction, and wherein the second sub-component extending from the first sub-component in the first direction has a second, different width in the second direction; a second component configured to define a gate of the first transistor, the second component extending over the first subcomponent in a second direction; and a third component configured to define a gate of the second transistor, the third component extending over the second sub-component in the second direction.

According to still another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including: forming a plurality of first nanostructures spaced apart from each other along a first direction, each of the plurality of first nanostructures having a first width along a second direction perpendicular to the first direction; forming a plurality of second nanostructures spaced apart from each other along the first direction, each of the plurality of second nanostructures having a second, different width along the second direction; forming a first gate extending in a second direction, the first gate surrounding each of the plurality of first nanostructures and having a first gate dielectric disposed therein; and forming a second gate extending along the second direction, the second gate surrounding each of the plurality of second nanostructures and having a second gate dielectric disposed therein.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1A illustrates an example circuit diagram of a memory cell according to some embodiments.

FIG. 1B illustrates another example circuit diagram of a memory cell according to some embodiments.

FIG. 1C illustrates another example circuit diagram of a memory cell according to some embodiments.

Fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G illustrate example design layouts of memory cells according to some embodiments.

FIG. 3 illustrates a perspective view of a memory device according to some embodiments.

FIG. 4 illustrates a flow chart of a method of fabricating the memory device of FIG. 3, in accordance with some embodiments.

Fig. 5, 6, 7A, 8A, 9A, 10, 11, 12A, 13, 14A, 15A, 16A, and 17A illustrate cross-sectional views of the memory device of fig. 3 at various stages of fabrication, taken along line a-a', in accordance with some embodiments.

Fig. 7B, 8B, 9B, and 12B illustrate top views of the memory device of fig. 3 at various stages of fabrication according to some embodiments.

Fig. 7C, 8C, 14B, 15B, 16B, 17B illustrate cross-sectional views of the memory device of fig. 3 at various stages of fabrication, taken along line B-B', in accordance with some embodiments.

Fig. 7D, 8D, 14C, 15C, 16C, 17C illustrate cross-sectional views of the memory device of fig. 3 at various stages of fabrication, taken along line C-C', in accordance with some embodiments.

FIG. 18A illustrates an example circuit diagram of a memory array according to some embodiments.

FIG. 18B illustrates an example design layout of the memory array of FIG. 18A, according to some embodiments.

FIG. 18C illustrates another example design layout of the memory array of FIG. 18, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. The term spaced relationship is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

In the fabrication of contemporary semiconductor devices, a large number of semiconductor devices, such as silicon channel n-type field effect transistors (nfets) and silicon germanium channel p-type field effect transistors (pfets), are fabricated on a single wafer. Non-planar transistor device architectures, such as fin-based transistors, may provide higher device density and higher performance than planar transistors. Some advanced non-planar transistor device architectures (e.g., nanostructured transistors) may further improve the performance of fin-based transistors. Exemplary nanostructured transistors include nanostructured transistors, nanowire transistors, and the like. The nanostructured transistor includes one or more nanostructures collectively configured as a conductive channel of the transistor, the conductive channel being completely encased by the gate stack. In contrast to fin-based transistors, in which the channel is partially wrapped by the gate stack, nanostructured transistors typically include one or more gate stacks around the entire perimeter of the nanostructured channel. In this way, the control of the nanostructure channel may be further improved, for example, resulting in a relatively large drive current given similar dimensions of the fin-based transistor and the nanostructure transistor.

The present disclosure provides various embodiments of a memory device including a plurality of memory cells, each memory cell configured in a nanostructure transistor configuration. In some embodiments, the disclosed memory cells include an antifuse memory cell, which is comprised of a programming transistor and one or more read transistors. Each of the program transistor and the read transistor includes a nanostructure transistor. Further, the programming transistor of the disclosed memory cell may have one or more nanostructure channels that are narrower than the one or more nanostructure channels of the read transistor. In this way, the programming yield of the programming transistor may be advantageously improved, in part due to the increased contact area of the gate dielectric of the programming transistor. Moreover, the read window of the read transistor may advantageously be enlarged due in part to the increase in drive current of the read transistor.

FIG. 1A illustrates an example circuit diagram of amemory cell 100 according to some embodiments. As shown, a memory cell (or sometimes referred to as a memory bit cell, memory bit, or bit) 100 includes afirst transistor 110 and asecond transistor 120. Each of the first andsecond transistors 110 and 120 may include an n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In some other embodiments,transistors 110 and 120 may comprise another type of MOSFET, for example, a p-type MOSFET, which will be discussed below with respect to fig. 1B. In some other embodiments, at least one of thetransistors 110 or 120 may be replaced by another type of electronic device (e.g., a MOS capacitor), while remaining within the scope of the present disclosure. Thefirst transistor 110 and thesecond transistor 120 are electrically coupled to each other in series. For example, thesource 110S of the first transistor is connected to thedrain 120D of the second transistor.

Thememory cell 100 may be configured as a one-time programmable (OTP) memory cell, such as an antifuse cell. It should be understood thatmemory cell 100 may be configured as any type of memory cell (e.g., a NOR-type non-volatile memory cell, a Dynamic Random Access Memory (DRAM) cell, a two-transistor Static Random Access Memory (SRAM) cell, etc.) that includes two transistors electrically coupled in series with each other.

When thememory cell 100 is configured as an antifuse cell, thefirst transistor 110 may function as a programming transistor, and thesecond transistor 120 may function as a reading transistor. As such, thedrain 110D of the first transistor is floating (e.g., not connected), and thegate 110G of the first transistor is connected to the program Word Line (WLP) 130; thegate 120G of the second transistor is coupled to a read Word Line (WLR)132 and thesource 120S of the second transistor is coupled to a Bit Line (BL) 134.

To program thememory cell 100, theread transistor 120 is turned on by providing a high voltage (e.g., a positive voltage corresponding to a logic high state) to thegate 120G via theWLR 132. Before, at the same time as, or after theread transistor 120 is turned on, a sufficiently high voltage (e.g., breakdown voltage (V)_BD) Applied to WLP 130 and a low voltage (e.g., a positive voltage corresponding to a logic low state) is applied toBL 134. A low voltage may be passed to thesource 110S which will generate VBD across thesource 110S andgate 110G, causing a breakdown of a portion of the gate dielectric of the program transistor 110 (e.g., the portion between thesource 110S andgate 110G). The behavior of the portion of the gate dielectric interconnectinggate 110G andsource 110S is equivalent resistive after the gate dielectric ofprogramming transistor 110 is broken down. Such a portion may be used as theresistor 136, for example. Prior to programming (before the gate dielectric of theprogramming transistor 110 is broken down), when theread transistor 120 is on, there is no conductive path between the BL134 and theWLP 130; after programming, when theread transistor 120 is on, a conductive path exists between the BL134 and the WLP 130 (e.g., via resistor 136).

To readmemory cell 100, similar to programming, readtransistor 120 is turned on and BL134 is coupled to a voltage corresponding to a logic low state. In response, a positive voltage is applied to thegate 110G of the program transistor. As described above, if the gate dielectric of theprogram transistor 110 is not broken down, there is no conductive path between the BL134 and theWLP 130. Thus, a relatively low current is conducted fromWLP 130 throughtransistors 110 and 120 toBL 134. If the gate dielectric of theprogram transistor 110 breaks down, a conductive path exists between the BL134 and theWLP 130. Thus, a relatively high current flows fromWLP 130 through transistor 110 (now equivalent to resistor 136) and the transistor120 toBL 134. Such low and high currents are sometimes referred to as I ofmemory cell 110, respectively_offAnd I_on. A circuit component (e.g., a sense amplifier) coupled to BL134 may couple I_offAnd I_onA distinction is made (and vice versa) to determine whether thememory cell 100 exhibits a logic high level ("1") or a logic low level ("0"). For example, when reading I_onMemory cell 100 may assume a 1; when reading I_offMemory cell 100 may assume a 0.

FIG. 1B illustrates an example circuit diagram of anothermemory cell 150 according to some embodiments.Memory cell 150 is similar tomemory cell 100 of FIG. 1A, except thatmemory cell 150 is comprised of a p-type MOSFET. As shown,memory cell 150 includes afirst transistor 160 and asecond transistor 170. Each of thefirst transistor 160 and thesecond transistor 170 may include a p-type MOSFET. Thefirst transistor 160 and thesecond transistor 170 are electrically coupled to each other in series. For example, thedrain 160D of the first transistor is connected to thesource 170S of the second transistor.Memory cell 150 may be used as an antifuse cell (as described above), withfirst transistor 160 serving as a programming transistor for the antifuse cell andsecond transistor 170 serving as a read transistor for the antifuse cell. Similar tomemory cell 100, thegate 160G of the program transistor is coupled toWLP 180, thegate 170G of the read transistor is coupled toWLR 182, and thedrain 170D of the read transistor is coupled toBL 184. The operation ofmemory cell 150 is substantially similar to the operation of memory cell 100 (except for the polarity of the voltages applied toWLP 180,WLR 182 and BL 184), and therefore, the discussion will not be repeated.

FIG. 1C illustrates an example circuit diagram of yet anothermemory cell 190 according to some embodiments.Memory cell 190 is similar tomemory cell 100 of FIG. 1A, except thatmemory cell 190 includes an additional read transistor. As shown, thememory cell 190 includes afirst transistor 191, asecond transistor 192, and athird transistor 193. Each of the first, second and third transistors 191-193 may include an n-type MOSFET. Each of transistors 191-193 can comprise a p-type MOSFET while remaining within the scope of the present disclosure. Thefirst transistor 191, thesecond transistor 192, and thethird transistor 193 are electrically coupled in series with each other. For example, thesource 191S of the first transistor is connected to thedrain 192D of the second transistor, and thesource 192S of the second transistor is connected to thedrain 193D of the third transistor. Thememory cell 190 may be used as an antifuse cell (as described above), where thefirst transistor 191 is used as a programming transistor of the antifuse cell, and the second andthird transistors 192 and 193 are used in common as a reading transistor of the antifuse cell. Similar tomemory cell 100, thegate 191G of the program transistor is coupled toWLP 194, thegates 192G and 193G of the read transistor are coupled to WLR0195 and WLR1196, respectively, and thesource 193S of the read transistor is coupled toBL 197. The operation ofmemory cell 190 is substantially similar to the operation ofmemory cell 100 and, therefore, the discussion will not be repeated.

In general, reducing the area of the gate dielectric of a program transistor may improve programming yield when programming an anti-fuse cell that includes a program transistor and one or more read transistors. By having a smaller area, the chance of gate dielectric breakdown may be increased. When reading the logic state presented by the anti-fuse cell, due to leakage, because of I_offMay be increased unexpectedly and therefore has a higher I_onIs advantageous. Thus, from I_onAnd I_offThe size of the read window defined by the ratio of (a) to (b) may be reduced, which may result in the sense amplifier being unable to distinguish between I_onAnd I_off。I_onCan be determined by the performance of the read transistor. In this regard, the programming transistors of the disclosed memory cells may be configured as first nanostructure transistors having a narrower nanostructure width, and the read transistors may be respectively configured as second nanostructure transistors having a wider nanostructure width. As used herein, nanostructure width (or width) may be referred to as the width of a nanostructure (e.g., nanoplatelet, nanowire) measured along a direction perpendicular to the direction in which the respective source and drain electrodes are aligned with each other. In this way, the programming transistor may have one or more narrower nanostructured channels, which advantageously reduces the area of the corresponding gate dielectric. Also, the read transistor mayTo have one or more wider nanostructured channels, which advantageously increases the magnitude of the current conducted through the antifuse cell.

Fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G provide various examples of design layouts to fabricate a programming transistor with a narrower nanostructure width of an antifuse cell and a read transistor with a wider nanostructure width, according to some embodiments. In some embodiments, the layouts of fig. 2A-2G may be used to fabricate nanostructured transistors. It should be understood, however, that the layout of fig. 2A-2G is not limited to fabricating nanostructured transistors. Each of the layouts of fig. 2A-2G may be used to fabricate any of a variety of other types of transistors, such as fin-based transistors (commonly referred to as finfets), nanowire transistors, and still be within the scope of the present disclosure. It will be appreciated that the layouts shown in figures 2A to 2G have been simplified for illustrative purposes. Accordingly, each layout may include one or more other components and still be within the scope of the present disclosure.

Referring to fig. 2A, alayout 200 is shown, according to some embodiments.Layout 200 includes afirst component 201, asecond component 202, and athird component 203. Each of the features 200-203 may correspond to one or more patterning processes (e.g., photolithography processes) to form physical device features. For example, thefirst component 201 may be used to define or otherwise form an active area on a substrate. Such active regions may be a stack of alternating layers of one or more nanostructure transistors, fin regions of one or more finfets, or oxide-defined (OD) regions of one or more planar transistors. The active region may serve as a source or a drain of the respective transistor. Accordingly, thefirst component 201 may be referred to herein as an "active component 201". In some embodiments, thefirst component 201 may include a plurality of sub-components, each extending along a first direction (e.g., the X-direction). These subcomponents are discussed below. The second andthird features 202 and 203, which may extend in a second direction (e.g., the Y-direction) relative to thefirst feature 201, may be used to define or otherwise fabricate gates of the respective transistors. Accordingly,second feature 202 andthird feature 203 may be referred to herein as "gate feature 202" and "gate feature 203," respectively. In manufacturing using thelayout 200, theactive features 201 may correspond to a first patterning process, and the gate features 202-203 extending over theactive features 201 may correspond to a second patterning process after the first patterning process.

As shown, theactive component 201 includes sub-components 201a, 201b, and 201 c. The sub-members 201a and 201b extending in the X direction are parallel to each other. The sub-members 201a and 201b may have a width W along the Y direction₁. The sub-member 201c extending in the X direction may have a width W in the Y direction₂. According to some embodiments, the width W₁And W₂The ratio may be any value between 0 and 1 that satisfies a predetermined condition (e.g., a design constraint or requirement). The sub-component 201c extends from the sub-components 201a and 201b such that a symbolic boundary (shown by dashedline 204 in fig. 2A) is defined between thenarrower sub-components 201a-b and the wider sub-component 201 c.

In some embodiments,gate member 203 is configured to overlie sub-members 201a and 201b (for forming a gate having a width W)₁Active area) of the substrate, thereby definingsides 207, 208, 209, and 210. For example, the sides of the sub-components 201a, 207 and 208 are placed on either side of thecentral portion 205 covered by thethird component 203; the sides of the sub-parts 201b, 209 and 210 are placed on either side of thecentral portion 206 covered by thethird part 203. Thegate member 202 is configured to cover acentral portion 211 of the sub-member 201c (for forming an active area of width W2) to definesides 212 and 213. For example, the sides of the sub-components 201c, 212 and 213 are placed on either side of thecentral portion 211 covered by thesecond component 202.Boundary 204 is located betweengate members 202 and 203 to have a narrower width W₁And a sub-assembly having a wider width W₂Are separated. Thus, at least some components of the first transistor may be defined by thecentral portion 205 and theside portion 206 and 210 of thenarrower sub-components 201a-b, and at least some components of the second transistor coupled in series with the first transistor may be defined by thecentral portion 211 and theside portion 212 and 213 of the wider sub-component 201 c.

In an example where thelayout 200 is used to fabricate an antifuse memory cell (e.g., 100 in fig. 1A), the portions of thegate member 203 overlying thecentral portion 205 and 206 may be collectively used to define thegate 110G;side 207 of sub-part 201a andside 209 of sub-part 201b may be used collectively to formdrain 110D.Side 208 ofsubcomponent 201a andside 210 ofsubcomponent 201b may be used collectively to formsource 110S; thecentral portion 205 of sub-component 201a and thecentral portion 206 of sub-component 201b may be collectively used to form the conduction channel of theprogramming transistor 110. The portion ofgate member 202 overlyingcentral portion 211 may be used to definegate 120G; theside 212 of the sub-part 201c may be used to form thedrain 120D; theside 213 of the sub-part 201c may be used to form thesource 120S. Thecentral portion 211 ofsubcomponent 201c may be used to form the conduction channel of theread transistor 120.

In some embodiments, the number of narrower sub-components covered by the gate component may be referred to as a first number ("N"), and the number of wider sub-components covered by the gate component may be referred to as a second number ("M"). The number N may correspond to the number of fins or the number of stacks of the first transistor, and the number M may correspond to the number of fins or the number of stacks of the second transistor coupled in series to the first transistor. In some embodiments, N is greater than or equal to M. Continuing the same example,programming transistor 110 may be characterized by a fin number of 2 because the number of narrower sub-components covered bygate components 203, 201a, and 201b is 2, and readingtransistor 120 may be characterized by a fin number of 1 because the number of wider sub-components covered bygate components 202, 201c is 1.

The various layouts shown in fig. 2A-2G follow a similar principle to define the programming transistor and the read transistor of the anti-fuse cell. Therefore, each layout of fig. 2B to 2G will be briefly described below.

Referring to FIG. 2B, alayout 220 is shown, according to some embodiments.Layout 220 includesactive features 221 and 222 and gate features 223 and 224. Theactive component 221 includes a first conductive layer having a width W₁And sub-members 221a and 221b having a width W₂Of (2)221 c. Theactive component 222 includes a substrate having a width W₁And sub-members 222a and 222b and having a width W₂Sub-assembly 222 c. Theboundary 225 between the gate features 223 and 224 is configured to distinguish narrower sub-features (having a width W₁) And a wider sub-part (having a width W)₂). In some embodiments, some components of the programming transistor of the anti-fuse cell may be formed bygate component 223 and having a width W₁And some components of the coupled read transistor may be defined by agate component 224 and have a width W₂Is defined (e.g. 221c, 222 c). Based on the principles defined above, the number of fins for the program transistor may be 4 and the number of fins for the read transistor may be 2.

Referring to fig. 2C, alayout 230 is shown, according to some embodiments.Layout 230 includesactive components 231, andgate components 232 and 233. Theactive component 231 includes a substrate having a width W₁And sub-members 231a, 231b, 231c and 231d of width W₂The sub-assembly 231 e. Theboundary 234 between thegate members 232 and 233 is configured to distinguish narrower sub-members (having a width W)₁) And a wider sub-part (having a width W)₂). In some embodiments, some components of the programming transistor of the anti-fuse cell may be formed fromgate component 232 and have a width W₁And some components of the coupled read transistor may be defined by agate component 233 and have a width W₂For example 231 e. Based on the principles defined above, the number of fins for the program transistor may be 4 and the number of fins for the read transistor may be 1.

Referring to fig. 2D, alayout 240 is shown, according to some embodiments.Layout 240 includesactive features 241, 242, and 243 and gate features 244 and 245. Theactive component 241 includes a substrate having a width W₁And sub-members 241a and 241b having a width W₂Sub-assembly 241 c. Theboundary 246 between thegate members 244 and 245 is configured to distinguish narrower sub-members (having a width W)₁) And a wider sub-part (having a width W)₂). Has a width W₁Active component of242, and 243 extend in the X direction across the area of the narrower sub-components (e.g., 241a-b) and wider sub-components (e.g., 241c) of theactive component 241. As such, theboundary 246 may divide each of the active components 242-243 into a first sub-component that is parallel to the narrower sub-components (e.g., 241a-b) and a second sub-component that is parallel to the wider sub-component (e.g., 241 c). In some embodiments, some components of the programming transistor of the anti-fuse cell may be formed bygate component 244, having a width W₁And a corresponding sub-assembly (e.g., 241a-b) having a width W₁And 243, and some components of the coupled read transistor may be defined by agate component 245 having a width W₂And a corresponding sub-member (e.g. 241c) having a width W₁Is defined by the second sub-component ofactive component 242 and 243.

Referring to fig. 2E, alayout 250 is shown, according to some embodiments.Layout 250 includesactive component 251, andgate components 252 and 253. Theactive component 251 includes a substrate having a width W₁And a sub-member 251a having a width W₂The sub-assembly 251 b. It is within the scope of the present disclosure that the position of the sub-component 251a disposed relative to the sub-component 251b may be moved in the Y-direction. Theboundary 254 between the gate features 252 and 253 is configured to distinguish narrower sub-components (having a width W)₁) And a wider sub-part (having a width W)₂). In some embodiments, some of the programming transistors of the anti-fuse cell may be formed bygate member 252 and have a width W₁And some components of the coupled read transistor may be defined by agate component 253 and have a width W₂For example 251 b. Based on the principles defined above, the number of fins for the program transistor may be 1, and the number of fins for the read transistor may be 1.

Referring to FIG. 2F, alayout 260 is shown, according to some embodiments.Layout 260 is similar tolayout 250 shown in FIG. 2E, except for the relative arrangement between the narrower sub-components and the wider narrower sub-components along the Y-direction. For example,layout 260 includesactive component 261, andgate components 262 and 263. Theactive component 261 includes a dielectric layer having a width W₁And a sub-member 261a having a width W₂Sub-component 261 b. It is within the scope of the present disclosure that the position of subpart 261a, which is disposed relative tosubpart 261b, may be moved in the Y-direction. Theboundary 264 between gate features 262 and 263 is configured to distinguish narrower sub-features (having a width W)₁) And a wider sub-part (having a width W)₂). In some embodiments, some components of the programming transistor of the anti-fuse cell may be formed fromgate component 262 and have a width W₁And some components of the coupled read transistor may pass throughgate component 263 and have a width W₂Is defined as sub-component (e.g. 261 b). Based on the principle defined above, the number of fins of the program transistor may be 1, and the number of fins of the read transistor may be 1.

Referring to fig. 2G, alayout 270 is shown, according to some embodiments.Layout 270 includesactive features 271 and 272 and gate features 273, 274, and 275. Theactive component 271 includes a substrate having a width W₁And sub-members 271a and 271b having a width W₂Sub-component 271 c. Theactive component 272 includes a dielectric having a width W₁And sub-members 272a and 272b, and having a width W₂And sub-assembly 272 c. Theboundary 276 between thegate members 273 and 274 is configured to distinguish narrower sub-members (having a width W₁) And a wider sub-part (having a width W)₂). In some embodiments, some of the programming transistors of the anti-fuse cell may be formed bygate feature 273 and having a width W₁May be defined by gate members 274-275 and having a width W₂For example 271c, 272 c. Based on the principles defined above, the number of fins for the program transistor may be 4 and the number of fins for the read transistor may be 2. Although in the embodiment shown in FIG. 2G, thesubcomponents 271c and 272c that define the read transistor share the same width W₂However, it should be understood that the sub-components for the read transistor may be combined into one sub-component to have a width W₂(e.g., similar to FIGS. 2E and 2F) or a mixture of subcomponents of different widths (e.g., similar to FIG. 2D)And remain within the scope of this disclosure.

Referring to fig. 3, a perspective view of amemory device 300 in a nanostructure transistor configuration is shown. According to some embodiments,memory device 300 may be part of an antifuse memory cell including a program transistor and a read transistor. The perspective view of fig. 3 is an overview of thememory device 300, and therefore, some components of thememory device 300 are not identified in fig. 3. More detailed features of thememory device 300 are shown and discussed below with reference to fig. 5-17.

Thememory device 300 may be formed on (or include) asubstrate 302. Over thesubstrate 302, thememory device 300 includes afirst gate structure 304 and asecond gate structure 314. Each of thefirst gate structure 304 and thesecond gate structure 314 is formed as a fin structure to wrap around a respective channel of the transistor. In some embodiments, the conduction channel may be collectively formed by one or more semiconductor nanostructures. Thegate structure 304 may wrap around nanostructures (or nanostructure channels) 306a, 306b, 306c, and 306d spaced apart from each other (or placed on top of each other) along the Z-direction; thegate structure 314 may wrap around nanostructures (or nanostructure channels) 316a, 316b, 316c, and 316d that are spaced apart from each other along the Z-direction (or placed on top of each other). On each side of thefirst gate structure 304, adrain 308 and asource 310 are formed. Thedrain 308 andsource 310 may be characterized as having a width approximately equal to W₁. On each side of thesecond gate structure 314, adrain 318 and asource 320 are formed. Thedrain 318 andsource 320 may be characterized as having a value approximately equal to W₂Is measured.

As a non-limiting example, thememory device 300 may be formed based on thelayout 260 shown in fig. 2F. As such,gate structures 304 and 314 may be formed from gate features 262 and 263, respectively, when viewed from the top; however,gate structures 304 and 314 may be formed from gate features 262 and 263, respectively. Thedrain 308,nanostructures 306a-d encapsulated by thegate structure 304, andsource 310 may be formed from asubcomponent 261a of anactive component 261; thedrain 318, thenanostructures 316a-d encapsulated by thegate structure 314, and thesource 320 may be formed from a subcomponent 261b of theactive component 261. In some embodiments, afirst transistor 350a (e.g., a programming transistor described above) may be formed by thegate structure 304, the respective wrapped-around channel, thedrain 308, and thesource 310; asecond transistor 350b (e.g., a read transistor as described above) may be formed from thegate structure 314, the corresponding wrapped-around channel, thedrain 318, and thesource 320.

Specifically, each of the first andsecond gate structures 304 and 314 includes a plurality of gate stacks. Each gate stack may include one or more gate dielectrics and one or more gate metals. Two of the gate stacks are configured to collectively encapsulate a respective one of the one or more nanostructures. For example, thefirst gate structure 304 includesgate stacks 305a, 305b, 305c, 305d, and 305 e. Gate stacks 305a-e can have a substantially similar width (along the Y direction) asgate structure 304, andnanostructures 306a-d can be characterized as having a width of about W₁Is less than the width (in the Y direction) of gate stacks 305 a-e. Additionally, eachgate stack 305a-e may include a portion that extends in the Z-direction to abut, connect to, or otherwise merge with an adjacent gate stack. For example, in addition to extending laterally along the nanostructures 306a (e.g., on top), thegate stack 305a also includes a downwardly extending portion to merge with an upwardly extending portion of anadjacent gate stack 305 b.

In this way, two adjacent ones ofgate stacks 305a-e may wrap around the entire perimeter of a respective one of nanostructures 306 a-d.Gate stacks 305a and 305b can be collectively wrapped around at least four sides ofnanostructure 306a, and both sides ofnanostructure 306a are coupled to drain 308 andsource 310, respectively;gate stacks 305a and 305b can be collectively wrapped on at least four sides ofnanostructure 306 a; gate stacks 305b and 305c can be co-wrapped on at least four sides ofnanostructure 306b, both sides ofnanostructure 306c being coupled to drain 308 andsource 310, respectively; gate stacks 305c and 305d can be collectively wrapped around at least four sides ofnanostructure 306c, with two sides ofnanostructure 306b coupled to drain 308 andsource 310, respectively; also, gate stacks 305d and 305e may be collectively wrapped on at least four sides ofnanostructure 306d, both sides ofnanostructure 306d being coupled to drain 308 andsource 310, respectively.

Similarly, thesecond gate structure 314 includesgate stacks 315a, 315b, 315c, 315d, and 315 e. Gate stacks 315a-e can have a substantially similar width (along the Y-direction) asgate structure 314, andnanostructures 316a-d can be characterized as having a width of about W₂Is smaller than one of the width gate stacks 315a-e (along the Y direction). In addition, each gate stack 315a-e can include a portion that extends in the Z-direction to abut, connect to, or otherwise merge with an adjacent gate stack. In this way, two adjacent gate stacks 315a-e can wrap around the entire perimeter of a respective one of the nanostructures 316 a-d. The gate stacks 315a and 315b may be collectively wrapped on at least four sides of thenanostructure 316a, with two sides of thenanostructure 316a coupled to thedrain 318 and thesource 320, respectively. The gate stacks 315b and 315c can be collectively wrapped around at least four sides of thenanostructure 316b, with two sides of thenanostructure 316b coupled to thedrain 318 and thesource 320, respectively. The gate stacks 315c and 315d can be collectively wrapped on at least four sides of thenanostructure 316c, two sides of thenanostructure 316c being coupled to thedrain 318 and thesource 320, respectively. The gate stacks 315d and 315e can collectively wrap around at least four sides of thenanostructure 316d, with two sides of thenanostructure 316d coupled to thedrain 318 and thesource 320, respectively.

Fig. 4 shows a flow diagram of amethod 400 of forming a memory device in accordance with one or more embodiments of the present disclosure. Themethod 400 may be used to form series connected antifuse memory cells comprising a program transistor and a read transistor. For example, at least some of the operations described inmethod 400 may be used to formmemory device 300. It is noted that themethod 400 is merely an example and is not intended to limit the present disclosure. Accordingly, it should be understood that additional operations may be provided before, during, and after themethod 400 of fig. 400, and only some other operations are briefly described herein.

The operations ofmethod 400 may be associated with cross-sectional views ofmemory device 300 taken along line a-a' at various stages of fabrication shown in fig. 5, 6, 7A, 8A, 9A, 10, 11, 12A, 13, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, and 18. For illustrative purposes, top views of thememory device 300 correspond to fig. 7A, 8A, 9A, and 12A, respectively, and are further illustrated in fig. 7B, 8B, 9B, and 12B; a cross-sectional view of thememory device 300 taken along line B-B' corresponds to and is further illustrated in fig. 7A, 8A, 14A, 15A, 16A, and 17A and in fig. 7C, 8C, 14B, 15B, 16B, 17B; a cross-sectional view of thememory device 300 taken along line B-B' corresponds to and is further illustrated in fig. 7A, 8A, 14A, 15A, 16A, and 17A and in fig. 7D, 8D, 14C, 15C, 16C, 17C. In some embodiments,memory device 300 may be included in or otherwise coupled to a microprocessor, another memory device, and/or other Integrated Circuit (IC). In addition, fig. 5 through 17C are simplified for a better understanding of the concepts of the present disclosure. Although the figures show thememory device 300 for clarity of illustration, it should be understood that the IC may include many other devices not shown in fig. 5-17C, such as inductors, resistors, capacitors, transistors, and so forth.

Referring first to fig. 4, in brief overview, themethod 400 begins withoperation 402 in which a substrate is provided inoperation 402. Themethod 400 proceeds tooperation 404 where, inoperation 404, an alternating series of first nanostructures and second nanostructures is formed. Themethod 400 proceeds tooperation 406 where an active region (including a first active sub-region and a second active sub-region) is defined inoperation 406. Themethod 400 proceeds tooperation 408, where a plurality of dummy gate stacks are formed inoperation 408. Themethod 400 proceeds tooperation 410 where a plurality of alternating nanostructure pillars are defined inoperation 410. Themethod 400 proceeds tooperation 412 where the respective ends of the first nanostructure are removed inoperation 412. Themethod 400 proceeds tooperation 414 where an inner spacer is formed inoperation 414. Themethod 400 proceeds tooperation 416 where source and drain are formed inoperation 416. Themethod 400 proceeds tooperation 418 where an interlayer dielectric is deposited inoperation 418. Themethod 400 proceeds tooperation 420, and inoperation 420, the dummy gate stack is removed. Themethod 400 proceeds tooperation 422 where the first nanostructure is removed inoperation 422. Themethod 400 proceeds tooperation 424 and, inoperation 424, a gate dielectric is formed. Themethod 400 proceeds tooperation 426. inoperation 426, a gate metal is formed.

Corresponding tooperation 402, fig. 5 is a cross-sectional view ofmemory device 300 includingsubstrate 302 taken along line a-a' (fig. 3) at one of the various stages of fabrication.Substrate 302 comprises a substrate of semiconductor material, such as silicon. Alternatively,substrate 302 may include other elemental semiconductor materials such as germanium. Thesubstrate 302 may also include compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. Thesubstrate 302 may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and indium gallium phosphide. In one embodiment,substrate 302 comprises an epitaxial layer. For example, the substrate may have an epitaxial layer overlying the bulk semiconductor. Further, thesubstrate 302 may include a semiconductor-on-insulator (SOI) structure. For example, thesubstrate 302 may include a Buried Oxide (BOX) layer formed by processing such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

Corresponding tooperation 404, fig. 6 is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of various stages of fabrication including an alternating series offirst nanostructures 351, 353, 355, and 357 andsecond nanostructures 352, 354, 356, and 358. Thefirst nanostructures 351, 353, 355, 357 may comprise SiGe sacrificial nanostructures (hereinafter referred to as "SiGesacrificial nanostructures 351, 353, 355, 357"), and thesecond nanostructures 352, 354, 356, 358 may comprise Si nanostructures (hereinafter referred to as "Si nanostructures 352, 354, 356, 358". SiGesacrificial nanostructures 351, 353, 355, 357 and alternating series ofSi nanostructures 352, 354, 356, 358 may be formed as a stack over thesubstrate 302. such stack may sometimes be referred to as a superlattice. in a non-limiting example, the SiGesacrificial nanostructures 351, 353, 355, 357 may be 25% SiGe. it is understood that the percentage of Ge in each SiGesacrificial nanostructure 351, 353, 355, 357 may be any value between 0 and 100 (except 0 and 100), and still within the scope of the present disclosure, thenanostructures 352, 354, 356, and 358 may include a first semiconductor material other than Si, and thenanostructures 351, 353, 355, and 357 may include a second semiconductor material other than SiGe, as long as the first second semiconductor material and the second semiconductor material, respectively, have different etching characteristics (e.g., etching rates).

The alternating series of nanostructures may be formed by epitaxially growing one layer, and then epitaxially growing until the desired number and thickness of nanostructures are obtained. The epitaxial material may be grown from gaseous or liquid precursors. The epitaxial material may be grown using Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), or other suitable processes. Depending on the type of transistor, epitaxial silicon, silicon germanium and/or carbon doped silicon (Si: C) may be doped during deposition (in-situ doping) by adding dopants of n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium).

Corresponding tooperation 406, FIG. 7A is a cross-sectional view ofmemory device 300 taken along line A-A' (FIG. 3) at one of various stages of fabrication, including definedactive sub-regions 368 and 370. For illustrative purposes, fig. 7B, 7C, and 7D also provide respective top views of a cross-sectional view taken along line B-B '(fig. 3) and a cross-sectional view taken along line C-C' (fig. 3), respectively, ofmemory device 300 at this stage of fabrication. As described above, thememory device 300 may be formed based on thelayout 260 shown in fig. 2F. For example, thelayout 260 may be used in a patterning process (e.g., a photolithography process) to form a mask over the nanostructures 351-358 (fig. 6). The mask may have a geometry substantially similar tofeatures 261 oflayout 260. The mask may then be used to etch the nanostructures 351-358 to formactive sub-regions 368 and 370, as shown in fig. 7B-7D. Corresponding to subcomponent 261a (FIG. 2F),active sub-region 368 is therefore characterized as having a width W in the Y-direction₁And corresponding to subcomponent 261b (fig. 2F),active sub-region 370 is thus characterized as having a width W in the Y-direction₂. Referring again to fig. 7A, "etched"SiGe nanostructure 359, Si nanostructure 360, SiGe nanostructure 361, Si nanostructure 362, SiGe nanostructure 363, Si nanostructure 364, SiGe nanostructure 365, and Si nanostructure 366 are stacked on top of each other along the Z direction, which may collectively constituteactive sub-regions 368 and 370. In this way, a symbolic boundary (as shown by dashedline 369 in fig. 7A and 7B) may be defined to distinguish betweenactive sub-regions 368 and 370.

Corresponding tooperation 408, fig. 8A is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of various stages of fabrication, including firstdummy gate stack 371 and seconddummy gate stack 372. For illustrative purposes, fig. 8B, 8C, and 8D also provide respective top views of a cross-sectional view taken along line B-B '(fig. 3) and a cross-sectional view taken along line C-C' (fig. 3), respectively, ofmemory device 300 at this stage of fabrication. Each of the dummy gate stacks 371 and 372 includes a dummy gate and a hard mask. For example, in fig. 8A, the firstdummy gate stack 371 includes adummy gate 371a formed over theSi nanostructure 366 and ahard mask 371b formed over thedummy gate 371 a. The seconddummy gate stack 372 includes adummy gate 372a formed over theSi nanostructure 366 and ahard mask 372b formed over thedummy gate 372 a.

In some embodiments, dummy gate stacks 371 and 372 correspond to gate features 262 and 263, respectively, of layout 260 (fig. 2F). In this way, dummy gate stacks 371 and 372 extending in the Y direction may be formed on theactive subregions 368 and 370, respectively, as shown in fig. 8B to 8D. In particular, thedummy gate stack 371 may be formed over and around sidewalls of theactive sub-region 368 and thedummy gate 372 may be formed over and around sidewalls of theactive sub-region 370, as shown in the top view of fig. 8B. Thedummy gates 371a and 372a may be formed by depositing amorphous silicon (a-Si) over and around theactive subregions 368 and 370. Other materials suitable for forming the dummy gate (e.g., polysilicon) may be used and remain within the scope of this disclosure. The a-Si is then planarized to the desired level. A hard mask (not shown) is deposited on the planarized a-Si and patterned (e.g., according to gate features 262 and 263 of layout 260 (fig. 2F)) to formhard masks 371b and 372 b. Thehard masks 371b and 372b may be formed of a nitride or oxide layer. An etching process, such as a Reactive Ion Etching (RIE) process, is performed on the a-Si to form dummy gate stacks 371 and 372.

After the dummy gate stacks 371 and 372 are formed,bias gate spacers 373 and 374 may be formed to extend along respective sidewalls of the dummy gate stacks 371 and 372, as shown in fig. 3 and 4. Fig. 8A to 8B. The offsetgate spacers 373 and 374 may be formed using a spacer pull down formation process. The offsetgate spacers 373 and 374 can also be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials) followed by directional etching (e.g., RIE).

Corresponding tooperation 410, fig. 9A is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of various stages of fabrication, including alternatingnanostructure pillars 375 and 376. For illustrative purposes, fig. 9B also provides a corresponding top view ofmemory device 300 at this stage of fabrication. After forming the offsetgate spacers 373 and 374, alternatingnanostructure pillars 375 and 376 may be formed from theactive sub-regions 368 and 370, respectively. In forming the alternatingnanostructure pillars 375 and 376, the offsetgate spacers 373 and 374, thedummy gates 371a and 372a, and the hard masks 371B and 372B may be used as masks to define theplaceholders 375 and 376 for the alternating nanostructure pillars, and theactive sub-regions 368 and 370 (enclosed by dashed lines in fig. 9B) may be subjected to an etching process to form the alternatingnanostructure pillars 375 and 376.

As in fig. 9A-9B, alternating nanostructure pillars 375 (obscured by diagonal line patterns in fig. 9B) are covered bydummy gate stack 371 andbias gate spacers 373; alternating nanostructure pillars 376 (obscured by diagonal line patterns in fig. 9B) are covered by the dummy gate stacks 372 and the biasgate isolation layer 374. Alternatingnanostructure pillars 375 are located in the region ofsubstrate 302 whereprogram transistor 350a (shown in fig. 3) will be formed and alternatingnanostructure pillars 376 are located in the region ofsubstrate 302 where readtransistor 350b (shown in fig. 3) will be formed. Each of the alternatingnanostructure pillars 375 and 376 includes an alternating "defined" stack of SiGe/Si nanostructures. For example, each of the alternatingnanostructure pillars 375 and 376 includes a stack of alternating defined SiGe nanostructures 359', definedSi nanostructures 360', defined SiGe nanostructures 361', definedSi nanostructures 362', defined SiGe nanostructures 363', definedSi nanostructures 364', defined SiGe nanostructures 365', and defined Si nanostructures 366'.

In some embodiments, the definedSi nanostructures 360', 362', 364', and 366' of alternatingnanostructure pillars 375 may correspond tonanostructures 306d, 306c, 306b, and 306a (as shown in fig. 3) when extended source/drain junctions are not formed; the definedSi nanostructures 360', 362', 364', and 366' of the alternatingnanostructure pillars 376 may correspond to thenanostructures 316d, 316c, 316b, and 316a, respectively (as shown in fig. 3).

Corresponding tooperation 412, fig. 10 is a cross-sectional view of thememory device 300 taken along line a-a ' (fig. 3) at one of the various stages of fabrication, with respective ends of each of the defined SiGe nanostructures 359', the defined SiGe nanostructures 361', the defined SiGe nanostructures 363', and the defined SiGe nanostructures 365' removed. In this way, etched SiGesacrificial nanostructures 378, 379, 380, and 381 may be formed. In some embodiments of the present disclosure, a first application may be used to remove end portions of the defined SiGe nanostructures 359', 361', 363', and 365', a so-called "pull back" process to pull the defined SiGe nanostructures 359', 361', 363', and 365' back the initial pull back distance so that the ends of the etched SiGesacrificial nanostructures 378, 379, 380, and 381 terminate below the offsetgate spacers 373 and 374. The pull back process may include a Hydrogen Chloride (HCL) gas isotropic etch process that etches SiGe without corroding Si.

Corresponding tooperation 414, fig. 11 is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of various stages of fabrication, includinginterior spacers 382, 383, 384, 385, 386, 387, 388, and 389. In some embodiments, the interior spacers 382-389 may be conformally formed by Chemical Vapor Deposition (CVD) or by single layer doping of nitride (MLD) followed by spacer RIE. In some other embodiments, the interior spacers 382-389 may be deposited using, for example, a conformal deposition process followed by an isotropic or anisotropic etch back to remove excess spacer material on the vertical sidewalls of the alternatingnanostructure pillars 375 and 376 and on the surface of thesemiconductor substrate 302. The material of theinterior spacers 382 and 389 may be formed of the same or different material (e.g., silicon nitride) as the offsetgate spacers 373 and 374. For example, the interior spacers 382-389 may be formed of silicon nitride, boron carbon nitride, silicon carbon oxynitride, or any other type of dielectric material suitable for forming insulated gate sidewall spacers for FET devices (e.g., dielectric materials having a dielectric constant k of less than about 5).

Corresponding tooperation 416, fig. 12A is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of the various stages of fabrication, includingdrain 308,source 310, drain 318, andsource 320. For illustrative purposes, fig. 12B also provides a corresponding top view ofmemory device 300 at this stage of fabrication. In some embodiments of the present disclosure, an epitaxial layer growth process may be used to form thedrain 308 on the exposed ends of the definedSi nanostructures 360', 362', 364', and 366' of the alternatingnanostructure pillars 375 in the region of thesubstrate 302 on the left side of thedummy gate stack 371, as shown in fig. 12B. An epitaxial layer growth process may be used to form asource 310 on the exposed ends of the definedSi nanostructures 360', 362', 364', and 366' of the alternatingnanostructure pillars 375 in the region of thesubstrate 302 on the right side of thedummy gate stack 371, as shown in fig. 12B. An epitaxial layer growth process may be used to formdrain 318 on the exposed ends of the definedSi nanostructures 360', 362', 364', and 366' of alternatingnanostructure pillars 376 in the region ofsubstrate 302 on the left side ofdummy gate stack 372, as shown in fig. 12B. Asource 320 is formed on the exposed ends of the definedSi nanostructures 360', 362', 364', and 366' in the region of thesubstrate 302 on the right side of thedummy gate stack 372 using an epitaxial layer growth process, as shown in fig. 12B.

In some embodiments, thedrain 308 andsource 310 may be formed to follow the shape of theactive sub-region 368, drain 318, andsourceThe pole 320 can be formed to follow the shape of the active sub-region 370 (fig. 7B). Thus, drain 308 andsource 310 may be characterized as having approximately W₁And thedrain 318 andsource 320 may be characterized as having a width (in the Y direction) of about W₂Width (in Y direction). In addition, thesource 310 and thedrain 318 may be merged together.

In-situ doping (ISD) may be applied to form doped drain/sources 308, 310, 318, and 320, creating the necessary junctions forprogram transistor 350a and readtransistor 350 b. N-type and p-type FETs are formed by implanting different types of dopants into selected regions of the device (e.g., drain/source 308, 310, 318, and 320) to form the necessary junctions. The N-type device may be formed by implanting arsenic (As) or phosphorus (P), and the P-type device may be formed by implanting boron (B).

Corresponding tooperation 418, fig. 13 is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of the various stages of fabrication, including an interlayer dielectric (ILD)material 394.ILD material 394 may be formed by: an oxide material (e.g., silicon dioxide) is deposited and then the bulk oxide is polished (e.g., using CMP) to a level that biases thegate spacers 373 and 374 and thehard masks 371b and 372 b.

Corresponding tooperation 420, fig. 14A is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of the various stages of fabrication, with dummy gate stacks 371 and 372 (fig. 13) removed. For illustrative purposes, fig. 14B and 14C also provide a cross-sectional view ofmemory device 300 at this stage of fabrication taken along lines B-B '(fig. 3) and C-C' (fig. 3), respectively. After forming theprotective ILD material 394, as shown in fig. 13, the dummy gate stacks 371 (includingdummy gate 371a andhard mask 371b) and 372 (includingdummy gate 372a andhard mask 372b) are removed. Dummy gate stacks 371 and 372 may be removed by a known etching process such as RIE or Chemical Oxide Removal (COR).

After removing dummy gate stacks 371 and 372, the respective top boundaries of alternatingnanostructure pillars 375 and 376 may be exposed again. In particular, the respective top boundaries of the defined Si nanostructures 366' of the alternatingnanostructure pillars 375 and 376 may be exposed, as shown in fig. 14A-14C. In addition to the top boundary, the respective sidewalls of alternatingnanostructure pillars 375 and 376 in the Y-direction may also be exposed, as shown in fig. 14B-14C.

Corresponding tooperation 422, fig. 15A is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of the various stages of fabrication, with etched SiGesacrificial nanostructures 378, 379, 380, and 381 removed (fig. 14A-14C). For purposes of illustration, fig. 15B and 15C also provide a cross-sectional view ofmemory device 300 at this stage of fabrication taken along lines B-B '(fig. 3) and C-C' (fig. 3), respectively. In some embodiments, the etched SiGesacrificial nanostructures 378, 379, 380, and 381 of the two alternatingnanostructure pillars 375 and 376 are removed. The etched SiGesacrificial nanostructures 378, 379, 380, and 381 may be removed by applying a selective etch, such as hydrochloric acid (HCl).

After removing the etched SiGesacrificial nanostructures 378, 379, 380, and 381, the respective bottom boundaries of the definedSi nanostructures 360', 362', 364', and 366' of the two alternatingnanostructure pillars 375 and 376 may be exposed, as shown in the cross-sectional views of fig. 15B-15C. Note that the bottom boundary may be completely exposed when viewed in the X direction (e.g., fig. 15B-15C), while being partially exposed when viewed in the Y direction (due to theinterior spacers 382 and 389) (fig. 15A).

According to some embodiments of the present disclosure, the partially exposed definedSi nanostructures 360', 362', 364', and 366' of the alternatingnanostructure pillars 375 may be collectively configured as a conduction channel of theprogramming transistor 350a (fig. 3); the partially exposed definedSi nanostructures 360', 362', 364', and 366' of the alternatingnanostructure pillars 376 may collectively be configured as a conduction channel of theread transistor 350b (fig. 3). As such, the partially exposed definedSi nanostructures 360', 362', 364', and 366' of alternatingnanostructure pillars 375 may be referred to herein as "conduction channels 395 a"; the partially exposed definedSi nanostructures 360', 362', 364', and 366' of the alternatingnanostructure pillars 376 may be referred to herein as "conduction channels 395 b".Conduction channel 395a and 395b configurationTo conduct current through theprogram transistor 305a and theread transistor 305b, respectively. Typically, such a conduction channel has a length and a width. The length may be parallel to the current flow and the width may be perpendicular to the current flow. As shown in fig. 15B-15C, the width of theconduction channel 395a can be about W₁And the width ofconduction channel 395b can be about W₂. Although four Si nanostructures are formed as the conduction channels of theprogram transistor 305a and theread transistor 305b of thememory device 300, it should be understood that a memory device fabricated by the methods disclosed herein may include any number of nanostructures to form the conduction channels thereof and remain within the scope of the present disclosure.

Corresponding tooperation 424, fig. 16A is a cross-sectional view ofmemory device 300 taken along line a-a' (fig. 3) at one of the various stages of fabrication, includinggate dielectrics 396A and 396 b. For illustrative purposes, fig. 16B and 16C also provide a cross-sectional view ofmemory device 300 at this stage of fabrication taken along lines B-B '(fig. 3) and C-C' (fig. 3), respectively. Referring to fig. 16A-16C, a gate dielectric 396A can be wrapped around each Si nanostructure of theconduction channel 395 a; a gate dielectric 396b can be wrapped around each Si nanostructure of theconduction channel 395 b.Gate dielectrics 396a and 396b may be formed of different high-k dielectric materials or the same high-k dielectric material.Gate dielectrics 396a and 396b may comprise a stack of various high-k dielectric materials. Thegate dielectrics 396a and 396b can be deposited using any suitable method, including, for example, Atomic Layer Deposition (ALD). In some embodiments,gate dielectrics 396a and 396b may optionally comprise a substantially thin oxide (e.g., SiO)_x) And (3) a layer.

Corresponding tooperation 426, fig. 17A is a cross-sectional view ofmemory device 300, taken along line a-a' (fig. 3), includinggate metals 397A and 397b, at one of the various stages of fabrication. For illustrative purposes, fig. 17B and 17C also provide a cross-sectional view ofmemory device 300 at this stage of fabrication taken along lines B-B '(fig. 3) and C-C' (fig. 3), respectively. As shown in fig. 17A-17C, gate metal 397A may surround each Si nanostructure of theconduction channel 395a with agate dielectric 396a disposed therebetween;gate metal 397b may surround each Si nanostructure of theconduction channel 395b with a gate dielectric 396b disposed therebetween. Thegate metals 397a and 397b may be formed of different metal materials or the same metal material.Gate metals 397a and 397a may comprise a stack of multiple metal materials. It should be understood thatgate metals 397a-397b may include any other conductive material and remain within the scope of this disclosure.Gate metals 397a and 397b may be deposited using any suitable method, including, for example, CVD. In some embodiments, thegate metal 397a, thecorresponding gate dielectric 396a, and the offsetgate spacer 373 may be collectively referred to as a gate structure, such as thegate structure 304 shown in fig. 3. Similarly,gate metal 397b, corresponding gate dielectric 396b, and offsetgate spacers 374 may be collectively referred to as a gate structure, such asgate structure 314 shown in fig. 3.

In some embodiments, after forminggate structures 304 and 314, one or more interconnect structures may be formed to connect each ofgate structure 304,gate structure 314, andsource 320 to connectmemory device 300 to other components or devices. For example, one or more interconnect structures (e.g., via structures commonly referred to as VGs) may be formed over thegate structure 304 to connect thegate structure 304 to one or more upper metal layers that may include a program Word Line (WLP); one or more interconnect structures (e.g., metal structures commonly referred to as MD, via structures commonly referred to as VD) may be formed over thegate structure 314 to connect thegate structure 314 to one or more upper metal layers that may include a read Word Line (WLR); one or more interconnect structures (e.g., via structures) may be formed throughILD 394 and oversource 320 to connectsource 320 to one or more upper metal layers, which may include a Bit Line (BL). As such,memory device 300, which is an example antifuse memory cell, may be connected to one or more other memory cells similar tomemory device 300. For example, a plurality ofsuch memory devices 300 may be arranged (e.g., coupled) by respective WLPs, read WLs, and BLs to form a memory array.

Theexample memory device 300 discussed above in fig. 3 and 5-17C is fabricated based on thelayout 260 of fig. 2. It will be appreciated that the other layouts discussed in fig. 2A-2E may also be used to form memory devices of any of a variety of transistor device architectures. For example, when using thelayout 200 in fig. 2A to form thememory cell 100 in a nanostructure transistor configuration (fig. 1A), thememory cell 100 may include a first stack of nanostructures forming part of the conduction channel of theprogram transistor 110 based on thecentral portion 205, a second stack of nanostructures forming another part of the conduction channel of theprogram transistor 110 based on thecentral portion 206, and a third stack of nanostructures forming the conduction channel of theread transistor 120 based on thecentral portion 211. The first and second stacks of each nanostructure may be characterized as having a width W₁And the third stack of each nanostructure can be characterized as having a width W₂. In some embodiments, each nanostructure of one of the first, second, and third stacks may be parallel to a corresponding nanostructure of the other stack.

FIG. 18A illustrates an example circuit diagram of amemory array 1800 according to some embodiments. Thememory array 1800 may include a plurality ofmemory cells 1802 coupled to one another via respective WLPs, WLRs, and BLs. In some embodiments, the memory cell may be substantially similar tomemory cell 100 shown in FIG. 1A. For example, eachmemory cell 1802 may include aprogram transistor 1802a and aread transistor 1802b coupled in series with each other via BL (e.g., 1810). Further,program transistor 1802a is gated by WLP (e.g., 1818) and readtransistor 1802b is gated by WLR (e.g., 1819). As such, thememory array 1800 may include a plurality of BLs (e.g., 1810, 1811, 1812, 1813, 1814, 1815, 1816, 1817), a plurality of WLPs (e.g., 1818, 1820, 1822, 1824), and a plurality of WLRs (e.g., 1819, 1821, 1823, 1825).

FIG. 18B illustrates anexemplary layout 1840 for fabricating thememory array 1800, according to some embodiments. Thelayout 1840 may include a plurality of bit/unit cell layouts (e.g., 1842, 1844) arranged relative to one another. In some embodiments, each of the bit cell layouts 1842-1844 may be substantially similar to thelayout 220 shown in FIG. 2B. For example, thebit cell layout 1842 includesactive components 1842a (similar to active component 221) and 1842b (similar to active component 222), andgate components 1842c (similar to gate component 223) and 1842d (similar to gate component 224). Thememory array 1800 may be implemented with respective gate features (e.g., 1858, 1859, 1860, 1861, 1862, 1863, 1864, 1865, 1866, 1867, 1868, 1869) and BL features (e.g., 1850, 1851, 1852, 1853, 1854, 1855, 1856, 1857).Gate member 1842d may be part ofgate member 1859 andgate member 1842c may be part ofgate member 1860. It is understood that the bitcell layout (e.g., 1842-1844) may be replaced with any of the other layouts shown in fig. 2A-2G and remain within the scope of this disclosure. In some embodiments, two adjacent bit cell layouts disposed along the same BL may mirror each other (e.g., rotated 180 ° with respect to a centerline between the two adjacent bit cell layouts). For example, thebitcells 1842 and 1844 may be mirror images of each other relative to thenotional centerline 1843.

FIG. 18C illustrates anotherexample layout 1870 to fabricate thememory array 1800 according to some embodiments. Thelayout 1870 may be substantially similar to thelayout 1840 of fig. 18B, except that thelayout 1870 includes one or more edge dummy protectors. Thus, the reference numbers of FIG. 18B may continue to be used in the discussion of FIG. 18C. As shown, thelayout 1870 includesedge dummy protectors 1871, 1872, 1873, and 1874 disposed along the sides of thelayout 1840. Theedge dummy protections 1871 and 1874 may include one or more gate components (e.g., 1875, 1876, 1877) parallel to the gate components 1858-. In addition, theedge dummy guard 1870 may further include two side active components 1890 and 1899. For simplicity, the components of theedge dummy guard 1874 are omitted. Similarly, theedge dummy protectors 1872 and 1873 may include one or more gate members (e.g., 1878, 1879, 1880, 1881, 1882, 1883, 1884, 1885, 1886, 1887, 1888, 1889) aligned with the gate members 1858-1869, respectively, and one or more active members (e.g., 1900, 1901) aligned with the side active member 1899. For simplicity, the components of theedge dummy guard 1873 are omitted. In some embodiments, the device components (e.g., gates) formed by the edge dummy protections 1870-1874 may be characterized as not having active functionality.

In one aspect of the disclosure, a memory device is disclosed. The memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from each other along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device includes a second transistor coupled in series to the first transistor. The second transistor includes one or more second semiconductor nanostructures spaced apart from each other along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

In the above memory device, the first transistor and the second transistor are configured as a programming transistor and a reading transistor, respectively, of the antifuse memory cell, the one or more first semiconductor nanostructures of the programming transistor are configured to conduct current in a third direction perpendicular to the first direction and the second direction, and the one or more second semiconductor nanostructures of the reading transistor are configured to conduct current in the third direction.

In the above memory device, the second different width is greater than the first width.

In the above memory device, a ratio of the second different width to the first width satisfies a condition.

In the above memory device, further comprising: one or more third semiconductor nanostructures spaced apart from each other along the first direction, each of the one or more third semiconductor nanostructures having a first width along the second direction.

In the above memory device, each of the one or more third semiconductor nanostructures is parallel to a corresponding one of the one or more first semiconductor nanostructures and a corresponding one of the one or more second semiconductor nanostructures.

In the above memory device, further comprising: a first gate metal surrounding each of the one or more first semiconductor nanostructures, wherein a first gate dielectric is disposed; and a second gate metal surrounding each of the one or more second semiconductor nanostructures, wherein a second gate dielectric is disposed.

In the above memory device, further comprising: a first drain disposed on a first side of a first gate metal coupled to one or more first semiconductor nanostructures, wherein the first drain has a first width along a second direction; a first source disposed on a second side of the first gate metal coupled to the one or more first semiconductor nanostructures, wherein the first source has a first width along the second direction; a second drain disposed on a second side of the first gate metal and a first side of a second gate metal coupled to the one or more second semiconductor nanostructures, wherein the second drain has a second width along a second direction; and a second source disposed on a second side of the second gate metal coupled to the one or more second semiconductor nanostructures, wherein the second source has a second width along the second direction.

In the above memory device, further comprising: a first gate metal surrounding each of the one or more first semiconductor nanostructures, wherein a first gate dielectric is disposed; a second gate metal surrounding each of the one or more second semiconductor nanostructures, wherein a second gate dielectric is disposed; a third gate metal surrounding each of the one or more second semiconductor nanostructures, wherein a third gate dielectric is disposed; a first drain disposed on a first side of a first gate metal coupled to one or more first semiconductor nanostructures, wherein the first drain has a first width along a second direction; a first source disposed on a second side of the first gate metal coupled to the one or more first semiconductor nanostructures, wherein the first source has a first width along the second direction; a second drain disposed on a second side of the first gate metal and a first side of a second gate metal coupled to the one or more second semiconductor nanostructures, wherein the second drain has a second width along a second direction; a second source disposed on a second side of a second gate metal coupled to the one or more second semiconductor nanostructures, wherein the second source has a second width along a second direction; a third drain disposed on a second side of the second gate metal and a first side of the third gate metal coupled to the one or more second semiconductor nanostructures, wherein the third drain has a second width along the second direction; a third source disposed on a second side of a third gate metal coupled to the one or more second semiconductor nanostructures, wherein the third source has a second width along the second direction.

In another aspect of the present disclosure, a memory device layout is disclosed. The memory device layout includes a first component including a first subcomponent and a second subcomponent. The first sub-component is configured to define a source and a drain of the first transistor, and the second sub-component is configured to define a source and a drain of the second transistor. The first sub-member extending in the first direction has a first width in a second direction perpendicular to the first direction. A second sub-member extending from the first sub-member in the first direction has a second different width in the second direction. The memory device layout includes a second component configured to define a gate of the first transistor. The second component extends over the first subcomponent in a second direction. The memory device layout includes a third component configured to define a gate of the second transistor. The third component extends over the second subcomponent in a second direction.

In the above memory device layout, the second different width is greater than the first width.

In the above memory device layout, a boundary between the first sub-component and the second sub-component of the first component is located between the second component and the third component.

In the above memory device layout, the first component is further configured to define respective sources and drains of the third transistor, the memory device layout further comprising: a fourth feature configured to define a gate of the third transistor, the fourth feature extending over the second sub-feature in the second direction.

In the above memory device layout, the first component further includes a third sub-component parallel to the first sub-component, the third sub-component having the first width along the second direction, the second sub-component of the first component also extending from the third sub-component along the first direction.

In the above memory device layout, the first component further includes a fourth sub-component parallel to the first sub-component and the second sub-component, the fourth sub-component having a first width along the second direction.

In the above memory device layout, the gate of the first transistor would be coupled to a program word line and the second transistor would be coupled to a read word line.

In the above memory device layout, the second sub-component of the first component includes a first portion and a second portion respectively located on different sides of the third component, and wherein the first portion or the second portion is coupled to the bit line.

In the above memory device layout, a ratio of the second different width to the first width satisfies a condition.

In yet another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a plurality of first nanostructures spaced apart from one another along a first direction. Each of the plurality of first nanostructures has a first width along a second direction perpendicular to the first direction. The method includes forming a plurality of second nanostructures spaced apart from each other along a first direction. Each of the plurality of second nanostructures has a second, different width along the second direction. The method includes forming a first gate extending along a second direction, the first gate surrounding each of the plurality of first nanostructures and having a first gate dielectric disposed therein. The method includes forming a second gate extending along a second direction, the second gate surrounding each of the plurality of second nanostructures and having a second gate dielectric disposed therein.

In the above method, the plurality of first nanostructures are configured as conduction channels of a programming transistor of the antifuse cell, and the plurality of second nanostructures are configured as conduction channels of a reading transistor of the antifuse cell, the second different width being greater than the first width.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A memory device, comprising:

a first transistor comprising:

one or more first semiconductor nanostructures spaced apart from one another along a first direction, each of the one or more first semiconductor nanostructures having a first width along a second direction perpendicular to the first direction; and

a second transistor coupled in series to the first transistor, comprising:

one or more second semiconductor nanostructures spaced apart from each other along the first direction, each of the one or more second semiconductor nanostructures having a second, different width along the second direction.

2. The memory device of claim 1, wherein the first transistor and the second transistor are configured as a programming transistor and a read transistor, respectively, of an antifuse memory cell, the one or more first semiconductor nanostructures of the programming transistor configured to conduct current in a third direction perpendicular to the first direction and the second direction, the one or more second semiconductor nanostructures of the read transistor configured to conduct current in the third direction.

3. The memory device of claim 1, wherein the second different width is greater than the first width.

4. The memory device of claim 1, wherein a ratio of the second different width to the first width satisfies a condition.

5. The memory device of claim 1, further comprising:

one or more third semiconductor nanostructures spaced apart from each other along the first direction, each of the one or more third semiconductor nanostructures having the first width along the second direction.

6. The memory device of claim 5, wherein each of the one or more third semiconductor nanostructures is parallel to a corresponding one of the one or more first semiconductor nanostructures and a corresponding one of the one or more second semiconductor nanostructures.

7. The memory device of claim 1, further comprising:

a first gate metal surrounding each of the one or more first semiconductor nanostructures, wherein a first gate dielectric is disposed; and

a second gate metal surrounding each of the one or more second semiconductor nanostructures, wherein a second gate dielectric is disposed.

8. The memory device of claim 7, further comprising:

a first drain disposed on a first side of the first gate metal coupled to the one or more first semiconductor nanostructures, wherein the first drain has the first width along the second direction;

a first source disposed on a second side of the first gate metal coupled to the one or more first semiconductor nanostructures, wherein the first source has the first width along the second direction;

a second drain disposed on the second side of the first gate metal and a first side of the second gate metal coupled to the one or more second semiconductor nanostructures, wherein the second drain has the second width along the second direction; and

a second source disposed on a second side of the second gate metal coupled to the one or more second semiconductor nanostructures, wherein the second source has the second width along the second direction.

9. A memory device layout, comprising:

a first component comprising a first subcomponent and a second subcomponent configured to define a source and a drain of a first transistor and the second subcomponent configured to define a source and a drain of a second transistor, wherein the first subcomponent extending in a first direction has a first width in a second direction perpendicular to the first direction, and wherein the second subcomponent extending from the first subcomponent in the first direction has a second, different width in the second direction;

a second component configured to define a gate of the first transistor, the second component extending over the first subcomponent along the second direction; and

a third component configured to define a gate of the second transistor, the third component extending over the second subcomponent along the second direction.

10. A method for manufacturing a semiconductor device, comprising:

forming a plurality of first nanostructures spaced apart from each other along a first direction, each of the plurality of first nanostructures having a first width along a second direction perpendicular to the first direction;

forming a plurality of second nanostructures spaced apart from each other along the first direction, each of the plurality of second nanostructures having a second, different width along the second direction;

forming a first gate extending along the second direction, the first gate surrounding each of the plurality of first nanostructures and having a first gate dielectric disposed therein; and

forming a second gate extending along the second direction, the second gate surrounding each of the plurality of second nanostructures and having a second gate dielectric disposed therein.

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