CN113238805A - Chip system and starting method of chip system - Google Patents
Chip system and starting method of chip systemDownload PDFInfo
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- CN113238805A CN113238805ACN202110538442.1ACN202110538442ACN113238805ACN 113238805 ACN113238805 ACN 113238805ACN 202110538442 ACN202110538442 ACN 202110538442ACN 113238805 ACN113238805 ACN 113238805A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
Translated fromChinese
Description
Technical Field
The embodiment of the invention relates to the technical field of chip architecture, in particular to a chip system and a starting method of the chip system.
Background
When a system-on-chip is started, it is usually adopted that the system-on-chip is started by reading a start code stored in a Read-Only Memory (ROM) after the system-on-chip is reset and released. As shown in fig. 1, which is a schematic structural diagram of a chip system in the prior art, as shown in the figure, a Central Processing Unit (CPU) in the chip system sends a command prompt CMD to a read only memory ROM after reset release, the ROM returns boot code data of a stored boot code through an on-chip bus according to the CMD, the CPU obtains complete boot code data through multiple reads, completes boot according to the complete boot code data, and controls the work of the whole chip system by the CPU.
However, in the prior art, when the chip system is started, the start code is usually fixed in the internal ROM, and the ROM has an unalterable characteristic after the chip system is manufactured, and in case that the start code in the ROM is incorrect, the whole chip system cannot be started normally, and even needs to be invalidated, so that the start mode has uniqueness, and the requirement of the user on the diversity of the start mode cannot be met.
Disclosure of Invention
The embodiment of the invention provides a chip system and a starting method of the chip system, which aim to realize the diversity of starting modes of the chip system.
In a first aspect, an embodiment of the present invention provides a chip system, including: the system comprises a Central Processing Unit (CPU), a serial communication interface and an address remapping unit which are connected with the CPU, and an on-chip storage unit which is connected with the address remapping unit through an on-chip bus;
the CPU is used for initializing according to the acquired reset signal;
the serial communication interface is used for sending the acquired starting instruction to the address remapping unit, wherein the starting instruction comprises starting data and a target address;
the address remapping unit is used for sending the starting data to the on-chip storage unit through the on-chip bus and storing the starting data in a target address of the on-chip storage unit;
and the CPU is used for reading the starting data from the target address of the on-chip storage unit through the on-chip bus based on the address remapping unit when the reset signal is released, and starting according to the starting data.
Optionally, the system further includes a selection unit, the selection unit is connected to the serial communication interface through a first input port, and the selection unit is connected to the external host through a second input port; and the selection unit is used for selecting the reset signal input from the first input port or the second input port according to a first selection instruction of a user and transmitting the reset signal to the CPU.
Optionally, the selecting unit is further configured to select a reset release message input from the first input port or the second input port according to a second selection instruction of the user, and transmit the reset release message to the CPU, so that the CPU releases the reset signal.
Optionally, the system further comprises a peripheral device, the peripheral device being connected to the bus; and the CPU is also used for controlling the working state of the peripheral equipment after starting.
Optionally, the system further includes a read only memory ROM connected to the on-chip bus, and an address remapping unit, and is further configured to update a historical start address with a target address, where the ROM stores historical start data in the historical start address.
Optionally, the CPU is configured to delete the saved historical operating data according to the acquired reset signal, and restore to an initial state to perform initialization.
In a second aspect, an embodiment of the present invention provides a method for starting a chip system, where the method is applied to the chip system, and includes: initializing according to the acquired reset signal through the CPU;
sending the obtained starting instruction to an address remapping unit through a serial communication interface, wherein the starting instruction comprises starting data and a target address;
sending the starting data to an on-chip storage unit through an on-chip bus by a remapping unit, and storing the starting data in a target address of the on-chip storage unit;
when the CPU determines that the reset signal is released, starting data is read from a target address of the on-chip storage unit through the on-chip bus based on the address remapping unit, and starting is carried out according to the starting data.
Optionally, before the initialization is performed by the CPU according to the acquired reset signal, the method further includes: a reset signal sent from the serial communication interface or an external host is acquired.
Optionally, after the starting is performed according to the starting data, the method further includes: the working state of the peripheral equipment is controlled by the CPU.
Optionally, the initializing by the CPU according to the acquired reset signal includes: and deleting the saved historical operating data by the CPU according to the acquired reset signal, and restoring to an initial state for initialization.
According to the technical scheme of the embodiment of the invention, the starting data acquired through the serial communication interface is stored in the target address of the on-chip storage unit, so that the CPU is started according to the starting data read from the target address after reset release, and the starting data can be changed as required, so that the requirement of a user on the diversity of starting modes is met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a prior art chip system;
FIG. 2 is a schematic structural diagram of a chip system according to an embodiment of the present invention;
fig. 3 is a flowchart of a startup method of a chip system according to a second embodiment of the present invention;
fig. 4 is a flowchart of a startup method of a chip system according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, software implementations, hardware implementations, and so on.
Example one
Fig. 2 is a schematic structural diagram of a chip system according to an embodiment of the present invention, where the chip system includes: a central processing unit CPU 11, aserial communication interface 12 and anaddress remapping unit 13 connected to the CPU, and an on-chip memory unit 15 connected to the address remapping unit via an on-chip bus 14.
The CPU 11 is used for initializing according to the acquired reset signal; theserial communication interface 12 is configured to send the obtained start instruction to the address remapping unit, where the start instruction includes start data and a target address; theaddress remapping unit 13 is configured to send the start data to the on-chip memory unit through the on-chip bus, and store the start data in a target address of the on-chip memory unit; and the CPU 11 is used for reading starting data from the target address of the on-chip storage unit through the on-chip bus based on the address remapping unit when the reset signal is released, and starting according to the starting data.
Optionally, the system further includes aselection unit 16, theselection unit 16 is connected to the serial communication interface through a first input port, and the selection unit is connected to the external host through a second input port; and the selection unit is used for selecting the reset signal input from the first input port or the second input port according to a first selection instruction of a user and transmitting the reset signal to the CPU.
Optionally, the CPU is configured to delete the saved historical operating data according to the acquired reset signal, and restore to an initial state to perform initialization.
Optionally, the system further includes a read only memory ROM connected to the on-chip bus, and an address remapping unit, and is further configured to update a historical start address with a target address, where the ROM stores historical start data in the historical start address.
Specifically, the addition of serial communication has two roles:
the first function is: in this embodiment, a reset channel controlled by the serial communication interface is newly added under the condition that the original reset channel is reserved, the CPU can be reset by any one reset signal input by the two reset channels, and the selection unit can specifically select the reset channel according to a first selection instruction input by a user. And when any reset signal is wrong, the user can select the other reset signal, so that the purpose of controlling the reset of the CPU is achieved. After acquiring the reset signal, the CPU deletes historical operating data saved in the previous operating process, and restores to an initial state for initialization, thereby preparing for the CPU to start up to re-execute a new task.
The second function is: although the chip system includes a read onlymemory ROM 18 connected to an on-chip bus, the boot history data in the ROM is already written in the boot history address in the ROM during the manufacturing process of the chip system, and even if the written boot history data is found to be incorrect or the boot mode needs to be changed according to the actual situation, the boot history data in the ROM cannot be revised again. Theserial communication interface 12 is added to send the acquired boot instruction to theaddress remapping unit 13, and since the boot instruction includes boot data and a target address, theaddress remapping unit 13 sends the boot data to the on-chip storage unit 15 through the on-chip bus, and stores the boot data included in the instruction in the target address of the on-chip storage unit. The on-chip Memory unit in this embodiment may be any Memory space capable of performing data updating, for example, a Random Access Memory (RAM), etc., and of course, this embodiment is merely an example, and does not limit the specific type of the on-chip Memory unit. Compared with the prior ROM starting mode, the method and the device have the advantages that the user can modify historical starting data according to needs and store the acquired new starting data in the on-chip storage space, so that the starting space of the chip system is remarkably expanded. As shown by the dotted line in fig. 2, a schematic diagram of the transmission process of saving the startup data acquired through the serial communication interface in the on-chip storage unit is shown.
It should be noted that, while theaddress remapping unit 13 sends the boot data to the on-chip storage unit through the on-chip bus and stores the boot data in the target address of the on-chip storage unit, in order to facilitate the subsequent CPU to read new boot data from a correct location, theaddress remapping unit 15 updates the historical boot address with the target address, so that the CPU can determine the storage location of the new boot data by accessing the address remapping unit, and does not continue to read the historical boot data that may be incorrect from the historical boot address of the original ROM.
Optionally, the selectingunit 16 is further configured to select a reset release message input from the first input port or the second input port according to a second selection instruction of the user, and transmit the reset release message to the CPU, so that the CPU releases the reset signal.
When the starting data is stored in the target address of the on-chip storage unit by the address remapping unit, and the CPU obtains the disappearance of the reset release through the first input port of the selection unit connected with the serial communication interface or the second input port of the selection unit, the reset signal is released. After the reset signal is released, the CPU reads the starting data from the target address of the on-chip storage unit through the on-chip bus based on the address remapping unit and starts according to the acquired starting data.
Optionally, the chip system further includes aperipheral device 17, the peripheral device being connected to the bus; and the CPU is also used for controlling the working state of the peripheral equipment after starting. Therefore, the CPU after starting controls the normal work of the whole chip system.
It should be noted that in this embodiment, the serial communication interface may be used as one Master device, and of course, other types ofMaster device masters 19 may also be included in the chip system, and a specific type of the other types ofMaster device masters 19 is not limited in this embodiment.
According to the technical scheme of the embodiment of the invention, the starting data acquired through the serial communication interface is stored in the target address of the on-chip storage unit, so that the CPU is started according to the starting data read from the target address after reset release, and the starting data can be changed as required, so that the requirement of a user on the diversity of starting modes is met.
Example two
Fig. 3 is a flowchart of a method for starting a system on chip according to an embodiment of the present invention, where the method can be applied to the system on chip according to the embodiment of the present invention. As shown in fig. 3, the method specifically includes the following operations:
in step S101, initialization is performed by the CPU according to the acquired reset signal.
Optionally, before the initialization is performed by the CPU according to the acquired reset signal, the method may further include: a reset signal sent from the serial communication interface or an external host is acquired.
Optionally, initializing by the CPU according to the acquired reset signal may include: and deleting the saved historical operating data by the CPU according to the acquired reset signal, and restoring to an initial state for initialization.
Specifically, the system also comprises a selection unit, wherein the selection unit is connected with the serial communication interface through a first input port and is connected with an external host through a second input port; and the selection unit is used for selecting the reset signal input from the first input port or the second input port according to a first selection instruction of a user and transmitting the reset signal to the CPU.
It should be noted that, in this embodiment, in the case of keeping the original one reset channel, a reset channel controlled by the serial communication interface is newly added, any one reset signal input through the two reset channels can reset the CPU, and specifically, the selection unit can perform selection according to the first selection instruction input by the user. And when any path of reset signal is wrong, another path of reset signal can be selected, so that the aim of controlling the reset of the CPU is fulfilled. After the CPU acquires the reset signal, the CPU deletes historical operating data stored in the previous operating process and restores the historical operating data to an initial state for initialization, so that preparation is made for the CPU to start and execute a new task again.
Step S102, sending the obtained starting instruction to an address remapping unit through a serial communication interface, wherein the starting instruction comprises starting data and a target address.
Specifically, in the present embodiment, the boot space of the system-on-chip is expanded by the serial communication interface, and although the system-on-chip includes the read only memory ROM connected to the on-chip bus, the historical boot data in the ROM is already written into the historical boot address in the ROM during the manufacturing process of the system-on-chip, and even if the written historical boot data is found to be incorrect or the boot method needs to be changed according to actual conditions, the historical boot data in the ROM cannot be modified again. The obtained starting instruction can be sent to the address remapping unit by adding the serial communication interface, and the starting instruction contains starting data and a target address, so that the address remapping unit sends the starting data to the on-chip storage unit through the on-chip bus and stores the starting data contained in the instruction in the target address of the on-chip storage unit. The on-chip Memory unit in this embodiment may be any Memory space capable of performing data updating, such as a Random Access Memory (RAM), and the like. Compared with the prior ROM starting mode, the method has the advantages that the user can modify the historical starting data according to the requirement and store the acquired new starting data in the on-chip storage space, so that the starting space of the chip system is remarkably expanded.
Step S103, the starting data is sent to the on-chip storage unit through the on-chip bus by the address remapping unit and is stored in the target address of the on-chip storage unit.
Specifically, in this embodiment, the address remapping unit sends the startup data to the on-chip memory unit through the on-chip bus, and stores the startup data in the target address of the on-chip memory unit. Meanwhile, in order to facilitate the subsequent CPU to read new starting data from a correct position, the historical starting address is updated by the target address through the address remapping unit, so that the CPU can determine the storage position of the new starting data by accessing the address remapping unit, and the historical starting data which is possibly wrong is not continuously read from the historical starting address of the original ROM.
And step S104, when the CPU determines that the reset signal is released, reading starting data from the target address of the on-chip storage unit through the on-chip bus based on the address remapping unit, and starting according to the starting data.
Specifically, when the address remapping unit is determined to store the start data in the target address of the on-chip storage unit, and the CPU obtains the disappearance of the reset release through the first input port of the selection unit connected to the serial communication interface or the second input port of the selection unit, the reset signal is released. After the reset signal is released, the CPU reads the starting data from the target address of the on-chip storage unit through the on-chip bus based on the address remapping unit and starts according to the acquired starting data.
According to the technical scheme of the embodiment of the invention, the starting data acquired through the serial communication interface is stored in the target address of the on-chip storage unit, so that the CPU is started according to the starting data read from the target address after reset release, and the starting data can be changed as required, so that the requirement of a user on the diversity of starting modes is met.
EXAMPLE III
Fig. 4 is a flowchart of a startup method of a chip system according to an embodiment of the present invention, where the embodiment is based on the foregoing embodiment, and after performing startup according to startup data, the method further includes: the working state of the peripheral equipment is controlled by the CPU.
In step S201, initialization is performed by the CPU according to the acquired reset signal.
Optionally, before the initialization is performed by the CPU according to the acquired reset signal, the method may further include: a reset signal sent from the serial communication interface or an external host is acquired.
Optionally, initializing by the CPU according to the acquired reset signal may include: and deleting the saved historical operating data by the CPU according to the acquired reset signal, and restoring to an initial state for initialization.
Step S202, sending the obtained starting instruction to an address remapping unit through a serial communication interface, wherein the starting instruction comprises starting data and a target address.
Step S203, sending the start data to the on-chip storage unit through the on-chip bus by the address remapping unit, and storing the start data in the target address of the on-chip storage unit.
Step S204, when the CPU determines that the reset signal is released, starting data is read from the target address of the on-chip storage unit through the on-chip bus based on the address remapping unit, and starting is carried out according to the starting data.
In step S205, the operating state of the peripheral device is controlled by the CPU.
Specifically, the chip system further comprises a peripheral device, and the peripheral device is connected with the bus. In this embodiment, the CPU in the startup state may also control the operating state of the peripheral device, so as to ensure that other peripheral devices of the chip system can operate normally after the CPU is started.
It should be noted that the peripheral device in this embodiment may include a USB port, a sound card, or the like, and the specific type of the peripheral device is not limited in this embodiment, and it is within the scope of the present application as long as the CPU can control the operating state of the peripheral device and ensure the normal operation of the whole chip system.
According to the technical scheme of the embodiment of the invention, the starting data acquired through the serial communication interface is stored in the target address of the on-chip storage unit, so that the CPU is started according to the starting data read from the target address after reset release, and the starting data can be changed as required, so that the requirement of a user on the diversity of starting modes is met. And the CPU after starting controls the working state of the peripheral equipment, thereby ensuring the normal work of other peripheral equipment of the chip system.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A chip system, comprising: the device comprises a Central Processing Unit (CPU), a serial communication interface and an address remapping unit which are connected with the CPU, and an on-chip storage unit which is connected with the address remapping unit through an on-chip bus;
the CPU is used for initializing according to the acquired reset signal;
the serial communication interface is used for sending the acquired starting instruction to the address remapping unit, wherein the starting instruction comprises starting data and a target address;
the address remapping unit is used for sending the starting data to the on-chip storage unit through the on-chip bus and storing the starting data in a target address of the on-chip storage unit;
and the CPU is used for reading the starting data from the target address of the on-chip storage unit through the on-chip bus based on the address remapping unit when the reset signal is released, and starting according to the starting data.
2. The system of claim 1, further comprising a selection unit, the selection unit being connected to the serial communication interface via a first input port, the selection unit being connected to an external host via a second input port;
the selection unit is used for selecting the reset signal input from the first input port or the second input port according to a first selection instruction of a user and transmitting the reset signal to the CPU.
3. The system according to claim 2, wherein the selection unit is further configured to select a reset release message input from the first input port or the second input port according to a second selection instruction of a user, and transmit the reset release message to the CPU, so that the CPU releases the reset signal.
4. A system according to any of claims 1 to 3, further comprising a peripheral device, said peripheral device being connected to said bus;
and the CPU is also used for controlling the working state of the peripheral equipment after being started.
5. The system of claim 4, further comprising a Read Only Memory (ROM) coupled to the on-chip bus,
the address remapping unit is further configured to update a historical boot start address with the target address, where the ROM stores historical boot data in the historical boot address.
6. The system of claim 1, wherein the CPU is configured to delete the saved historical operating data according to the acquired reset signal, and restore the saved historical operating data to an initial state for initialization.
7. A startup method of a chip system, applied to the chip system according to any one of claims 1 to 6, comprising:
initializing according to the acquired reset signal through the CPU;
sending the obtained starting instruction to an address remapping unit through a serial communication interface, wherein the starting instruction comprises starting data and a target address;
sending the starting data to the on-chip storage unit through the on-chip bus by an address remapping unit, and storing the starting data in a target address of the on-chip storage unit;
and when the CPU determines that the reset signal is released, reading the starting data from the target address of the on-chip storage unit through the on-chip bus based on the address remapping unit, and starting according to the starting data.
8. The method according to claim 7, before the initialization by the CPU according to the acquired reset signal, further comprising:
acquiring the reset signal transmitted from a serial communication interface or an external host.
9. The method of claim 7, wherein after the booting according to the booting data, further comprising:
and controlling the working state of the peripheral equipment by the CPU.
10. The method according to any one of claims 7 to 9, wherein the initializing by the CPU according to the acquired reset signal includes:
and deleting the saved historical operating data by the CPU according to the acquired reset signal, and restoring to an initial state for initialization.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12332782B2 (en) | 2023-03-22 | 2025-06-17 | Stmicroelectronics International N.V. | Integrated circuit with address remapping circuitry to respond to a memory access request |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010028715A (en)* | 1999-09-22 | 2001-04-06 | 서평원 | apparatus and method for booting in data processing system |
| CN101599024A (en)* | 2009-07-29 | 2009-12-09 | 迈普通信技术股份有限公司 | A kind of device of switching and booting codes in double memory area, system and method |
| CN103514100A (en)* | 2012-06-19 | 2014-01-15 | 三星电子株式会社 | Memory system and SOC (system-on-chip) including linear address remapping logic |
| WO2015100878A1 (en)* | 2013-12-30 | 2015-07-09 | 深圳市中兴微电子技术有限公司 | Chip starting method, multi-core processor chip and storage medium |
| CN112068904A (en)* | 2020-09-27 | 2020-12-11 | 山东云海国创云计算装备产业创新中心有限公司 | Chip boot operation method, device and related assembly |
- 2021
- 2021-05-18CNCN202110538442.1Apatent/CN113238805A/enactivePending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010028715A (en)* | 1999-09-22 | 2001-04-06 | 서평원 | apparatus and method for booting in data processing system |
| CN101599024A (en)* | 2009-07-29 | 2009-12-09 | 迈普通信技术股份有限公司 | A kind of device of switching and booting codes in double memory area, system and method |
| CN103514100A (en)* | 2012-06-19 | 2014-01-15 | 三星电子株式会社 | Memory system and SOC (system-on-chip) including linear address remapping logic |
| WO2015100878A1 (en)* | 2013-12-30 | 2015-07-09 | 深圳市中兴微电子技术有限公司 | Chip starting method, multi-core processor chip and storage medium |
| CN112068904A (en)* | 2020-09-27 | 2020-12-11 | 山东云海国创云计算装备产业创新中心有限公司 | Chip boot operation method, device and related assembly |
Non-Patent Citations (1)
| Title |
|---|
| 苏奎峰等编著: "《TMS320x281x DSP原理及其C程序开发 第2版》", 30 September 2011, 北京航空航天大学出版社, pages: 438* |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12332782B2 (en) | 2023-03-22 | 2025-06-17 | Stmicroelectronics International N.V. | Integrated circuit with address remapping circuitry to respond to a memory access request |
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