CN113224133B - Multi-gate-change field effect transistor structure, manufacturing method thereof and chip device - Google Patents

Abstract

Translated fromChinese

本发明涉及一种多栅极变化的场效晶体管结构及其制造方法、芯片装置，晶体管包括位于底层的漏极外延层、位于顶层的源极层以及嵌入于漏极外延层内的源极延伸倒鳍、第一栅极与第二栅极;第一栅极排列在源极延伸倒鳍之间,第二栅极对准在源极延伸倒鳍上,第一栅极与第二栅极的两侧各形成有成对由源极层至漏极外延层内部并联的对称型沟道;优选示例中,漏极外延层在对应源极延伸倒鳍的底部部位形成屏蔽栅底部浮空反极型柱底结。本发明提供的场效晶体管架构为多栅极变化的密集化,具有衬底背面漏极与顶面源极电子流分区均匀化的效果、以及减少开槽工艺的效果。

The invention relates to a multi-gate variable field effect transistor structure, a manufacturing method and a chip device. The transistor comprises a drain epitaxial layer on the bottom layer, a source electrode layer on the top layer and a source electrode extension embedded in the drain epitaxial layer. An inverted fin, a first gate and a second gate; the first gate is arranged between the source extended inverted fins, the second gate is aligned on the source extended inverted fin, the first gate and the second gate A pair of symmetrical channels connected in parallel from the source layer to the drain epitaxial layer are formed on both sides; in a preferred example, the drain epitaxial layer forms a shielded gate bottom floating counter at the bottom portion of the corresponding source extended inverted fin. Polar bottom junction. The structure of the field effect transistor provided by the present invention is the densification of multi-gate changes, and has the effect of uniformizing the electron flow partition of the drain and the source of the top surface of the substrate, and the effect of reducing the slotting process.

Description

Translated fromChinese

多栅极变化的场效晶体管结构及其制造方法、芯片装置Field effect transistor structure with multi-gate variation, its manufacturing method, and chip device

技术领域technical field

本发明涉及半导体晶体管的技术领域，尤其是涉及一种多栅极变化的场效晶体管结构及其制造方法、芯片装置。The present invention relates to the technical field of semiconductor transistors, and in particular, to a field effect transistor structure with multiple gate changes, a manufacturing method thereof, and a chip device.

背景技术Background technique

场效晶体管结构作为半导体芯片的关键重要器件,目前已有多种结构,主要包括有以下几类:FinFET鳍式场效晶体管、JFET结型场效晶体管、面场效晶体管、穿隧式场效晶体管槽栅场效应管、分裂栅场效应管以及超级结场效应管。其中FinFET鳍式场效晶体管、JFET结型场效晶体管、面场效晶体管以及穿隧式场效晶体管结构都是将源极接点与漏极接点设计在半导体衬底的同一表面，随着晶圆薄化与器件微小化的趋势发展,由晶圆背面漏电流的问题会越来越是一个需要面对与克服的难题。其中,JFET结型场效应晶体管与穿隧式场效晶体管,由于将沟道层设计在半导体衬底的有源区内,漏电流的问题比较严重,FinFET鳍式晶体管是将沟道层以额外沉积的方式设计在突出鳍状的栅极上,漏电流的问题相对较轻,但器件结构与工艺相对复杂。FinFET鳍式晶体管的沟道层以氧化层表面外延方式形成显然不具有如内生方式形成沟道层的单晶结构,故其沟道层电性能稳定性不及JFET结型场效应晶体管、面场效晶体管与穿隧式场效晶体管。槽栅（trench gate）场效应管存在硅极限的限制，导致实现同样导通电阻占用更大的晶圆面积器件的功率密度无法提升。分裂栅场效应管和超级结场效应管虽然可以突破硅极限但工艺制程复杂且工艺控制窗口窄；另外器件容易出现电流集中可靠性差的现象，使器件的性能和可靠性很难兼得。As a key and important device of semiconductor chips, the field effect transistor structure has a variety of structures, mainly including the following categories: FinFET fin field effect transistor, JFET junction field effect transistor, surface field effect transistor, tunnel field effect transistor Transistor trench gate field effect transistor, split gate field effect transistor and super junction field effect transistor. Among them, the FinFET fin field effect transistor, JFET junction field effect transistor, surface field effect transistor and tunnel field effect transistor structure are all designed with source and drain contacts on the same surface of the semiconductor substrate. With the trend of thinning and device miniaturization, the problem of leakage current from the backside of the wafer will become more and more difficult to face and overcome. Among them, JFET junction field effect transistor and tunnel field effect transistor, because the channel layer is designed in the active region of the semiconductor substrate, the problem of leakage current is more serious, FinFET fin transistor is the channel layer with extra The deposition method is designed on the protruding fin-shaped gate, and the problem of leakage current is relatively light, but the device structure and process are relatively complex. The channel layer of the FinFET fin transistor is formed by epitaxy on the surface of the oxide layer. Obviously, it does not have a single crystal structure such as the channel layer formed by the endogenous method, so the electrical stability of the channel layer is not as good as that of the JFET junction field effect transistor and the surface field. effect transistors and tunneling field effect transistors. The trench gate FET is limited by the silicon limit, so that the power density of the device with the same on-resistance occupying a larger wafer area cannot be improved. Although split gate field effect transistor and super junction field effect transistor can break through the silicon limit, the process is complicated and the process control window is narrow; in addition, the device is prone to the phenomenon of poor reliability of current concentration, making it difficult to achieve both performance and reliability of the device.

现有技术中的FinFET鳍式晶体管可见于CN103985712A、CN106981517A、CN106887461A,都具有突出于衬底的栅极鳍。现有技术中的JFET结型场效应晶体管可见于CN1507070A、CN108257955A,不具有突出于衬底的栅极且沟道层以衬底内掺杂区图案界定。现有技术中的面场效晶体管可见于CN107534060A,不具有突出于衬底的栅极,单元占据表面积较大。现有技术中的穿隧式场效晶体管可见于CN110797387A、CN110943121A,为FinFET鳍式晶体管的一种变种,两鳍状结构以外延方式形成图案磊晶层,鳍状结构侧壁覆盖栅极层并予以填埋,将原本鳍状结构的栅极功能变化为沟道功能,同一表面上两鳍状结构的顶部分别作为源极与漏极。FinFET fin transistors in the prior art can be found in CN103985712A, CN106981517A, CN106887461A, and all have gate fins protruding from the substrate. JFET junction field effect transistors in the prior art can be found in CN1507070A and CN108257955A, which do not have a gate protruding from the substrate and the channel layer is defined by a pattern of doped regions in the substrate. The surface field effect transistor in the prior art can be seen in CN107534060A, does not have a gate protruding from the substrate, and the unit occupies a large surface area. The tunneling field effect transistors in the prior art can be found in CN110797387A and CN110943121A, which are a variant of the FinFET fin transistor. It is buried to change the gate function of the original fin structure into a channel function, and the tops of the two fin structures on the same surface are used as source and drain respectively.

在场效晶体管结构的制造中需要多道的堆叠开罩或是挖沟槽的工艺,在维持产品有效电性能下如何减少堆叠开罩或是挖沟槽的工艺次数也是需要持续研究的。In the manufacture of field effect transistor structures, multiple stacking and trenching processes are required. How to reduce the number of stacking and trenching processes while maintaining the effective electrical performance of the product also requires continuous research.

发明内容SUMMARY OF THE INVENTION

本发明的主要目的一是提供一种多栅极变化的场效晶体管结构，主要进步在于以创新的晶体管架构解决场效晶体管的源极电子流分布不均、产品性能和可靠性不兼容、产品性能和加工难度不兼容的问题。该晶体管架构还具有减少半导体开槽工艺的效果。The main purpose of the present invention is to provide a field effect transistor structure with multiple gate changes. The main progress is to solve the uneven distribution of source electron currents of field effect transistors, product performance and reliability incompatibility, product performance and reliability with innovative transistor structure. The problem of incompatibility between performance and processing difficulty. The transistor architecture also has the effect of reducing the semiconductor trenching process.

本发明的主要目的二是提供一种多栅极变化的场效晶体管结构的制造方法，用以实现极处电子流分布均匀场效晶体管结构的制作。The second main purpose of the present invention is to provide a method for manufacturing a field effect transistor structure with multiple gate changes, so as to realize the fabrication of a field effect transistor structure with uniform electron current distribution at the pole.

本发明的主要目的三是提供一种半导体芯片装置，具有安装芯片时即实现源极或/与漏极对外结合的效果。The third main purpose of the present invention is to provide a semiconductor chip device, which has the effect that the source electrode or/and the drain electrode are combined externally when the chip is mounted.

本发明的主要目的一是通过以下技术方案得以实现的：Main purpose one of the present invention is achieved through the following technical solutions:

提出一种多栅极变化的场效晶体管结构，包括：A multi-gate variation field effect transistor structure is proposed, including:

漏极衬底，具有由漏极外延层提供的处理表面与对应的背面，由所述处理表面形成有相互平行的第一沟槽，所述第一沟槽的内壁绝缘处理，所述第一沟槽的底部内设置源极延伸倒鳍，所述第一沟槽的深度不超过所述漏极外延层的厚度;The drain substrate has a processed surface and a corresponding back surface provided by the drain epitaxial layer, first trenches parallel to each other are formed on the processed surface, the inner walls of the first trenches are insulated and processed, and the first trenches are A source extension inverted fin is arranged in the bottom of the trench, and the depth of the first trench does not exceed the thickness of the drain epitaxial layer;

有源层，形成于所述漏极外延层中，由所述有源层形成有位于所述第一沟槽之间的第二沟槽，所述第二沟槽的内壁绝缘处理，所述第二沟槽内设置有第一栅极，所述第二沟槽的第二深度足以贯穿所述有源层但小于所述第一沟槽的第一深度;设置所述第一栅极的同时还在所述第一沟槽内对准所述源极延伸倒鳍的上方设置有第二栅极;所述第二栅极与所述第一栅极具有不同的形状轮廓;an active layer formed in the drain epitaxial layer, a second trench between the first trenches is formed from the active layer, the inner wall of the second trench is insulated, the A first gate is disposed in the second trench, and the second depth of the second trench is sufficient to penetrate the active layer but is less than the first depth of the first trench; At the same time, a second gate is also arranged above the source extending inverted fin in the first trench; the second gate and the first gate have different shape profiles;

内介电层，形成于所述第一栅极上与所述第二栅极上,使所述第一栅极与所述第二栅极为嵌埋结构;an inner dielectric layer formed on the first gate and the second gate, so that the first gate and the second gate are embedded structures;

源极层，形成于所述漏极外延层上，所述源极层等电位连接所述源极延伸倒鳍，所述场效晶体管的沟道分别位于所述第一栅极的两侧与所述第二栅极的两侧。A source layer is formed on the drain epitaxial layer, the source layer is equipotentially connected to the source extension fin, and the channel of the field effect transistor is located on both sides of the first gate and both sides of the second gate.

通过采用上述技术方案，利用排列于源极延伸倒鳍之间的第一栅极与位于源极延伸倒鳍上的第一栅极，嵌埋第一栅极的第二沟槽的第二深度足以贯穿有源层但小于嵌埋源极延伸倒鳍与第二栅极的第一沟槽的第一深度,实现了隔离栅之间纵向沟道的密集化,在源极与漏极之间的电子流分区且均匀化;此外,以第二栅极与第一栅极具有不同的形状轮廓,分别由第一沟槽的中段形状与第二沟槽的底部形状定义形成,有源区内在第二栅极与第一栅极的两侧外各形成纵向沟道,使漏极外延层或/与漏极衬底的电子流不易跨过以源极延伸倒鳍形成的隔离栅。By adopting the above technical solution, the second depth of the second trench of the first gate electrode is embedded by using the first gate electrode arranged between the source extended back fins and the first gate electrode located on the source extended back fin The first depth is sufficient to penetrate the active layer but is smaller than the first depth of the first trench where the buried source extends the inverted fin and the second gate, so that the densification of the longitudinal channel between the isolation gates is realized, and the depth between the source and the drain is realized. In addition, the second gate and the first gate have different shapes and contours, which are respectively defined by the shape of the middle section of the first trench and the bottom shape of the second trench, and the active area is in the The second gate and the first gate each form a vertical channel on both sides, so that the electron flow of the drain epitaxial layer or/and the drain substrate cannot easily cross the isolation gate formed by the source extending back fin.

由于第一栅极与第二栅极的埋入深度突破所述有源层到达所述漏极外延层的内部，在埋入式栅极两侧形成相对于处理表面纵向且并联的成对短沟道;漏极衬底的背面可作为漏极垫的接触,电子流的移动是由处理表面到漏极外延层的背面,过程中是经过了源极延伸倒鳍的分区隔开以及对应第一栅极与第二栅极两侧的每一侧绝缘处理的其中一侧沟道的多个半栅极开关导通,在源极延伸倒鳍的分区的场效应分区流动在漏极衬底的背面,实现了分区内四个或四个以上相邻源极分路下的半栅晶体管两侧沟道导通在漏极衬底的背面,使原本衬底背面漏电流的缺陷转换成有益与有意义的漏极输出,并且避免了电子流如熔丝效应集中于漏极衬底的背面的局部区域。Since the buried depths of the first gate and the second gate break through the active layer and reach the inside of the drain epitaxial layer, paired short-circuits longitudinally and in parallel with respect to the processing surface are formed on both sides of the buried gate. channel; the backside of the drain substrate can be used as the contact of the drain pad, and the movement of the electron flow is from the treated surface to the backside of the drain epitaxial layer, in the process, it is separated by the source extension fin and the corresponding first A gate and a plurality of half-gate switches of one side of the channel of each side of the insulating process on both sides of the second gate are turned on, and the field effect partition of the partition extending the inverted fin at the source flows in the drain substrate It realizes that the channels on both sides of the half-gate transistor under four or more adjacent source shunts in the partition are conducted on the backside of the drain substrate, so that the original defect of the leakage current on the backside of the substrate can be converted into beneficial With meaningful drain output, and avoids electron flow such as fuse effects concentrated in the local area of the backside of the drain substrate.

此外,利用源极层与源极延伸倒鳍制程上分离设计与结构上导通,提供了漏极外延层内隔离栅的作用,工艺上源极层只需要在器件台面之外设置接触孔连接即可,而不需要额外制作其他沟槽,源极延伸倒鳍的材质选择具有更多自由度,以克服工艺填孔填槽的困难、提高源极延伸倒鳍与漏极外延层的热膨胀适配度。In addition, the separation design and structural conduction of the source layer and the source extension inverted fin process are used to provide the isolation gate in the drain epitaxial layer, and the source layer only needs to be connected outside the device mesa. That is, without the need to make other trenches, the material selection of the source extension back fin has more degrees of freedom, so as to overcome the difficulty of filling the hole and fill the groove in the process, and improve the thermal expansion adaptability of the source extension back fin and the drain epitaxial layer. Matching degree.

本发明在较佳示例中可以进一步配置为：所述源极层还覆盖于所述内介电层上，所述有源层由所述漏极外延层的所述处理表面内化形成，所述内介电层凹陷于所述处理表面,以利所述源极层与所述有源区的欧姆接触的结合。In a preferred example of the present invention, it can be further configured that: the source layer is also covered on the inner dielectric layer, and the active layer is formed by internalizing the treated surface of the drain epitaxial layer, so The inner dielectric layer is recessed on the processing surface to facilitate the combination of the source layer and the ohmic contact of the active region.

可以通过采用上述优选技术特点，利用覆盖在所述内介电层上的源极层以及内介电层凹陷于处理表面,源极层跨过源极延伸倒鳍的隔离导通相接在内介电层上,以扩大源极接触，所述内介电层电绝缘所述第一栅极与第二栅极的顶部与延伸的源极层。器件结构中少了内介电层在处理表面上的沉淀厚度而能更薄。当所述有源层由所述漏极外延层的所述处理表面内化形成,所述有源层与所述漏极外延层两者的晶格匹配,没有界面间隙的缺陷,晶体管的沟道结构与漏极外延层成为一体结构,在电性能稳定度上优于外延生长的有源层或沟道层;当所述源极层与所述有源区之间为欧姆接触的结合,能缩小两者的电阻。By adopting the above-mentioned preferred technical features, the source layer covered on the inner dielectric layer and the inner dielectric layer can be used to be recessed on the processing surface, and the source layer extends across the source and the isolation conduction of the inverted fin is connected to the inside. on a dielectric layer to expand the source contact, the inner dielectric layer electrically insulates the tops of the first and second gates from the extended source layer. The device structure can be thinner by reducing the precipitation thickness of the inner dielectric layer on the treated surface. When the active layer is formed by internalizing the treated surface of the drain epitaxial layer, the active layer and the drain epitaxial layer are lattice-matched, and there are no interfacial gap defects, the trenches of the transistor. The channel structure and the drain epitaxial layer become an integrated structure, which is superior to the active layer or channel layer grown by epitaxy in terms of electrical performance stability; when the source layer and the active region are combined by ohmic contact, The resistance of both can be reduced.

本发明在较佳示例中可以进一步配置为：所述有源层包括位于底层的沟道层、位于所述沟道层上且在沟槽开口两侧的源极领域结,所述源极领域结以斜角离子注入形成,用于连接沟槽凹陷区内的所述源极层至对应第一栅极与第二栅极的两侧。In a preferred example of the present invention, the active layer can be further configured as follows: the active layer includes a channel layer on the bottom layer, and source field junctions on the channel layer and on both sides of the trench opening, the source field junctions The junction is formed by ion implantation at an oblique angle, and is used for connecting the source layer in the recessed area of the trench to two sides corresponding to the first gate and the second gate.

通过采用上述优选技术特点，利用所述有源层中的源极领域结,在源极层与有源层沟道层之间形成电子流连接，第一沟槽与第二沟槽的开口端能形成供所述源极层填入的自对准凹陷区，所述源极层能槽口角隅包覆方式通过源极领域结导接到对应第一栅极与第二栅极两侧的沟道。By adopting the above-mentioned preferred technical features, using the source field junction in the active layer, an electron flow connection is formed between the source layer and the channel layer of the active layer, and the open ends of the first trench and the second trench are A self-aligned recessed area for the source layer to be filled can be formed, and the source layer can be connected to the corresponding first gate and the second gate through the source field junction in a notch-corner cladding manner. channel.

本发明在较佳示例中可以进一步配置为：所述有源层还包括位于顶层的欧姆接触层,分隔于所述源极领域结之间且显露于所述处理表面,所述欧姆接触层的厚度小于所述源极领域结的下沉深度。In a preferred example, the present invention may be further configured as: the active layer further includes an ohmic contact layer on the top layer, separated between the source field junctions and exposed on the processing surface, and the ohmic contact layer has an ohmic contact layer. The thickness is less than the sink depth of the source field junction.

通过采用上述优选技术特点，利用所述有源层位于顶层的欧姆接触层，供所述源极层的直接结合,并有效界定所述源极领域结在所述处理表面上的显露区域。By adopting the above-mentioned preferred technical features, the ohmic contact layer with the active layer on the top layer is used for direct bonding of the source layer, and the exposed area of the source region junction on the processing surface is effectively defined.

本发明在较佳示例中可以进一步配置为：所述漏极外延层在对应所述第一沟槽底部的部位还形成有深植入区，以形成屏蔽栅底部浮空反极型柱底结。In a preferred example of the present invention, a deep implantation region is further formed on the drain epitaxial layer at a portion corresponding to the bottom of the first trench, so as to form a floating inversion post-bottom junction at the bottom of the shielded gate .

通过采用上述优选技术特点，利用屏蔽栅底部浮空反极型柱底结由所述源极延伸倒鳍的底部透出,以增加浮空反极型柱对临近的极型柱的电荷平衡,在制作上可以减少所述第一沟槽的深度和底部绝缘层厚度,也有利于所述源极延伸倒鳍的填充形成。By adopting the above-mentioned preferred technical features, the bottom junction of the floating inversion column at the bottom of the shielded gate is used to penetrate through the bottom of the source extending inverted fin, so as to increase the charge balance of the floating inversion column to the adjacent polar column, In manufacturing, the depth of the first trench and the thickness of the bottom insulating layer can be reduced, which is also beneficial to the filling and formation of the source extending inverted fin.

本发明在较佳示例中可以进一步配置为：所述源极延伸倒鳍与所述衬底外延层之间的绝缘厚度大于所述第一栅极或/与所述第二栅极的表面至所述衬底外延层的栅氧厚度;所述第二栅极的底部与所述源极延伸倒鳍之间形成有第一隔离氧化层,所述第二栅极的顶部与所述源极层之间形成有第二隔离氧化层,以增加埋入式栅极与源极的隔离厚度,所述第二隔离氧化层还形成并覆盖于所述第一栅极的顶部。In a preferred example of the present invention, it can be further configured that: the insulating thickness between the source extending back fin and the substrate epitaxial layer is greater than the surface of the first gate or/and the second gate to The gate oxide thickness of the epitaxial layer of the substrate; a first isolation oxide layer is formed between the bottom of the second gate and the source extending back fin, and the top of the second gate and the source A second isolation oxide layer is formed between the layers to increase the isolation thickness between the buried gate and the source, and the second isolation oxide layer is also formed and covers the top of the first gate.

通过采用上述优选技术特点，利用源极延伸倒鳍的绝缘厚度大于所述第一栅极或/与所述第二栅极的栅氧厚度，使源极延伸倒鳍具有电子流隔离分区作用但不具有栅极的场效应开关作用;优选配合第二栅极的底部与顶部形成的第一隔离氧化层与第二隔离氧化层，第二栅极的栅极场效应只作用于第二栅极的两侧,叠加态的源极延伸倒鳍与第二栅极之前产生效应隔离作用。By adopting the above-mentioned preferred technical features, the insulating thickness of the source extended back fin is larger than the gate oxide thickness of the first gate or/and the second gate, so that the source extended back fin has the function of electron flow isolation and partition, but It does not have the field effect switching function of the gate; it is preferable to cooperate with the first isolation oxide layer and the second isolation oxide layer formed on the bottom and top of the second gate, and the gate field effect of the second gate only acts on the second gate On both sides of the superposition state, the source electrode of the superimposed state extends the inverted fin and the second gate electrode before producing the effect of isolation.

本发明在较佳示例中可以进一步配置为：以所述第一栅极与第二栅极等电位连接下的电场效应，来自所述源极层的电子流在所述处理表面上分流沿着所述第二沟槽与所述第一沟槽上半部的侧壁轮廓的对称侧移动到所述第一沟槽下半部之间的所述漏极衬底，均匀在所述漏极衬底的所述背面或设置于该背面的漏极金属垫。The present invention may be further configured, in a preferred example, such that the flow of electrons from the source layer is shunted along the processing surface by the electric field effect under the equipotential connection of the first gate and the second gate. The symmetrical sides of the sidewall profiles of the upper half of the second trench and the first trench are moved to the drain substrate between the lower half of the first trench, evenly over the drain The backside of the substrate or the drain metal pad disposed on the backside.

通过采用上述优选技术特点，利用所述第一栅极与第二栅极等电位连接下的电场效应，实现电子流由顶面至底面的在所述漏极外延层的所述第一沟槽之间的分区均匀化。By adopting the above-mentioned preferred technical features, the electric field effect under the equipotential connection of the first gate and the second gate is used to realize the electron flow from the top surface to the bottom surface of the first trench in the drain epitaxial layer The partitions between are homogenized.

本发明的主要目的二是通过以下技术方案得以实现的：Main purpose two of the present invention is achieved through the following technical solutions:

提出一种多栅极变化的场效晶体管结构的制造方法，用以制造如上所述任意技术方案可能组合的场效晶体管结构，该制造方法包括：A method for manufacturing a field effect transistor structure with multi-gate variation is provided, which is used to manufacture the field effect transistor structure with any possible combination of the above-mentioned technical solutions, and the manufacturing method includes:

提供漏极衬底，具有由漏极外延层提供的处理表面与对应的背面，由所述处理表面刻蚀形成相互平行的第一沟槽;providing a drain substrate having a processed surface provided by the drain epitaxial layer and a corresponding back surface, and first trenches parallel to each other are formed by etching the processed surface;

在所述处理表面与所述第一沟槽内形成第一效应氧化层，使所述第一沟槽的内壁绝缘处理;A first effect oxide layer is formed in the treated surface and the first trench, so that the inner wall of the first trench is insulated and treated;

以沉淀填充方式在所述第一沟槽的底部内设置源极延伸倒鳍，并去除所述源极延伸倒鳍与所述第一效应氧化层在所述处理表面上的部位，所述第一沟槽的深度不超过所述漏极外延层的厚度;A source extension back fin is arranged in the bottom of the first trench by means of precipitation filling, and the portion of the source extension back fin and the first effect oxide layer on the processing surface is removed, and the first effect oxide layer is removed. The depth of a trench does not exceed the thickness of the drain epitaxial layer;

由所述处理表面刻蚀形成位于所述第一沟槽之间的第二沟槽;etching the treated surface to form second trenches between the first trenches;

在所述处理表面上、所述第二沟槽内与所述第一沟槽的剩余空间内与形成第二效应氧化层，使所述第二沟槽的内壁与所述第一沟槽剩余空间的内壁绝缘处理;A second effect oxide layer is formed on the treated surface, in the second trench and in the remaining space of the first trench, so that the inner wall of the second trench and the first trench remain Insulation treatment of the inner wall of the space;

以沉淀填充方式在所述第二沟槽内设置第一栅极以及在所述第一沟槽剩余空间内设置第二栅极，所述第二栅极位于所述源极延伸倒鳍上;所述第二栅极与所述第一栅极具有不同的形状轮廓;Disposing a first gate in the second trench and disposing a second gate in the remaining space of the first trench in a precipitation-filling manner, the second gate being located on the source extending inverted fin; the second gate has a different shape profile from the first gate;

在所述漏极外延层的所述处理表面下以能量注入方式形成有源层，所述有源层的底面在所述第二沟槽与所述第一沟槽剩余空间能贯穿的范围内;An active layer is formed under the treatment surface of the drain epitaxial layer by means of energy injection, and the bottom surface of the active layer is within the range where the remaining space of the second trench and the first trench can penetrate ;

以沉淀覆盖方式在所述第一栅极与所述第二栅极上形成内介电层,使所述第一栅极与所述第二栅极为嵌埋结构;forming an inner dielectric layer on the first gate and the second gate by means of deposition and covering, so that the first gate and the second gate are embedded structures;

在所述漏极外延层上形成源极层，所述源极层等电位连接所述源极延伸倒鳍，所述场效晶体管的沟道分别位于所述第一栅极的两侧与所述第二栅极的两侧。A source layer is formed on the drain epitaxial layer, the source layer is equipotentially connected to the source extension back fin, and the channel of the field effect transistor is located on both sides of the first gate and the both sides of the second gate.

通过采用上述技术方案，利用所述源极延伸倒鳍的预先制作,减少半导体制程中在漏极外延层的沟槽内填充源极延伸物的工艺难度，用于形成源极延伸倒鳍的第一沟槽上还能形成另一形状变化的第二栅极，最终制得多栅极变化密集化的场效晶体管。By adopting the above technical solution, the prefabrication of the source extension inverted fin is used to reduce the process difficulty of filling the source extension in the trench of the drain epitaxial layer in the semiconductor process, and the first step for forming the source extension inverted fin is reduced. Another second gate with a shape change can also be formed on a trench, and finally a field effect transistor with multiple gate changes and denser can be produced.

本发明在较佳示例中可以进一步配置为：The present invention can be further configured as:

在提供所述漏极衬底的步骤后,还包括：以离子植入方式在所述漏极外延层在对应所述第一沟槽底部的部位形成屏蔽栅底部浮空反极型柱底结;具体的,所述漏极衬底为导电型半导体晶圆;After the step of providing the drain substrate, the method further includes: forming a floating inversion pillar bottom junction at the bottom of the shielded gate at the portion of the drain epitaxial layer corresponding to the bottom of the first trench by ion implantation ; Specifically, the drain substrate is a conductive semiconductor wafer;

或/与,在形成所述第一效应氧化层的步骤中,包括：以热氧化方式在所述第一沟槽内形成所述第一效应氧化层的氧化层;之后以沉淀方式在所述第一沟槽内形成所述第一效应氧化层的淀积层;具体的，所述第一效应氧化层的材质包括氧化硅;Or/and, in the step of forming the first effect oxide layer, comprising: forming an oxide layer of the first effect oxide layer in the first trench by thermal oxidation; A deposition layer of the first effect oxide layer is formed in the first trench; specifically, the material of the first effect oxide layer includes silicon oxide;

或/与,在设置所述源极延伸倒鳍的步骤中,所述源极延伸倒鳍与所述第一效应氧化层在所述处理表面上的部位去除方法包括选择性刻蚀或是化学机械研磨与回刻蚀;优选的,所述源极延伸倒鳍的材质包括导电多晶硅;Or/and, in the step of disposing the source extension back fin, the method for removing the portion of the source extension back fin and the first effect oxide layer on the processing surface includes selective etching or chemical Mechanical grinding and etch back; preferably, the material of the source extending back fin includes conductive polysilicon;

或/与,在形成所述第二沟槽的步骤中,包括的前置步骤是：在所述处理表面上形成第一硬掩膜层,以遮盖所述处理表面以及所述源极延伸倒鳍的顶部;在形成所述第二沟槽的步骤后,包括的后置步骤是：刻蚀在所述处理表面上的所述第一硬掩膜层,在所述源极延伸倒鳍上的所述第一硬掩膜层被保留形成为第一隔离氧化层;优选的,在所述第二沟槽形成之后,以离子植入方式在所述漏极外延层在对应所述第二沟槽底部的部位形成栅下浮空反极型结;Or/and, in the step of forming the second trench, a pre-step is included: forming a first hard mask layer on the processing surface to cover the processing surface and the source electrode extension. the top of the fin; after the step of forming the second trench, a post-processing step included is: etching the first hard mask layer on the processing surface, on the source extending inverted fin The first hard mask layer is retained to form a first isolation oxide layer; preferably, after the second trench is formed, ion implantation is performed on the drain epitaxial layer corresponding to the second trench. The bottom part of the trench forms a floating inversion junction under the gate;

或/与,在形成所述第二效应氧化层的步骤中,所述第二效应氧化层具体为栅氧化层,以热氧化或热氧化加上淀积方式形成所述栅氧化层于所述第二沟槽与所述第一沟槽剩余空间的内壁与所述处理表面上;Or/and, in the step of forming the second effect oxide layer, the second effect oxide layer is specifically a gate oxide layer, and the gate oxide layer is formed on the gate oxide layer by thermal oxidation or thermal oxidation plus deposition. The second groove and the inner wall of the remaining space of the first groove and the processing surface;

或/与,在设置所述第一栅极与第二栅极的步骤中,去除所述第一栅极与第二栅极在所述处理表面上的相接部位,去除方法包括选择性刻蚀或是化学机械研磨与回刻蚀,使所述第一栅极与第二栅极的顶面凹陷于所述处理表面;优选的,所述栅极的材质包括导电多晶硅,含有掺杂离子;Or/and, in the step of arranging the first gate and the second gate, the contact part of the first gate and the second gate on the processing surface is removed, and the removal method includes selective etching. etching or chemical mechanical polishing and etching back, so that the top surfaces of the first gate and the second gate are recessed in the treatment surface; preferably, the material of the gate includes conductive polysilicon, containing dopant ions ;

或/与,在形成所述有源层的步骤中,所述有源层由所述漏极外延层的所述处理表面内化形成;所述有源层包括位于底层的沟道层、位于所述沟道层上且在沟槽开口两侧的源极领域结;所述源极领域结用于连接沟槽凹陷区内的所述源极层至对应第一栅极与第二栅极的两侧;所述源极领域结的形成方法包括：先在所述第一栅极、所述第二栅极上与所述处理表面上形成第二硬掩膜沉淀;经过斜角刻蚀,所述第二硬掩膜沉淀形成为在所述第一栅极与所述第二栅极上的第二隔离氧化层以及在所述处理表面上的自对准掩膜体;在位于所述处理表面上的自对准掩膜体的遮挡下斜角离子注入用于形成所述源极领域结的掺杂物;Or/and, in the step of forming the active layer, the active layer is formed by internalizing the treated surface of the drain epitaxial layer; the active layer includes a channel layer on the bottom layer, a channel layer on the bottom layer, source field junctions on the channel layer and on both sides of the trench opening; the source field junctions are used to connect the source layer in the recessed area of the trench to the corresponding first gate and second gate The method for forming the source field junction includes: firstly forming a second hard mask deposit on the first gate, the second gate and the processing surface; , the second hard mask deposition is formed as a second isolation oxide layer on the first gate and the second gate and a self-aligned mask body on the treated surface; oblique ion implantation of a dopant for forming the source field junction under the shading of the self-aligned mask body on the treated surface;

或/与,在形成所述源极层的步骤中，所述源极层还覆盖于所述内介电层上，所述源极层的材质为金属;在形成所述源极层的步骤后，对所述漏极衬底的背面进行晶背减薄与晶背金属化。Or/and, in the step of forming the source layer, the source layer is also covered on the inner dielectric layer, and the material of the source layer is metal; in the step of forming the source layer Afterwards, backside thinning and backside metallization are performed on the backside of the drain substrate.

可以通过采用上述优选技术特点，利用上述对应的特征或其组合达到如上所述相应的技术效果。The above-mentioned corresponding technical effects can be achieved by adopting the above-mentioned preferred technical characteristics, using the above-mentioned corresponding characteristics or their combinations.

本发明的主要目的三是通过以下技术方案得以实现的：Main purpose three of the present invention is achieved through the following technical solutions:

提出一种半导体芯片装置，包括：如上所述任意技术方案可能组合的场效晶体管结构,或者,使用的场效晶体管结构包括:位于处理表面下的漏极外延层、位于所述处理表面上的源极层以及嵌入于所述漏极外延层内的源极延伸倒鳍、第一栅极与第二栅极;所述第一栅极排列在所述源极延伸倒鳍之间,所述第二栅极对准在所述源极延伸倒鳍上,所述第一栅极与所述第二栅极的两侧各形成有成对由所述源极层至所述漏极外延层内部并联的对称型沟道;优选的,所述漏极外延层在对应所述源极延伸倒鳍的底部部位形成屏蔽栅底部浮空反极型柱底结;优选的,所述有源层包括位于底层的沟道层、位于所述沟道层上且在沟槽开口两侧的源极领域结,所述源极领域结以斜角离子注入形成,用于连接沟槽凹陷区内的所述源极层至对应第一栅极与第二栅极的两侧;更优选的,所述有源层还包括位于顶层的欧姆接触层,分隔于所述源极领域结之间且显露于所述处理表面,所述欧姆接触层的厚度小于所述源极领域结的下沉深度。A semiconductor chip device is proposed, comprising: a field effect transistor structure that may be combined with any of the above technical solutions, or, the used field effect transistor structure includes: a drain epitaxial layer located under a processing surface, a drain epitaxial layer located on the processing surface A source layer and a source extension back fin embedded in the drain epitaxial layer, a first gate and a second gate; the first gate is arranged between the source extension back fins, the The second gate is aligned on the source extension fin, and two sides of the first gate and the second gate are each formed with a pair of epitaxial layers from the source layer to the drain an internal parallel symmetric channel; preferably, the drain epitaxial layer forms a shielded gate bottom floating reverse pole bottom junction at the bottom portion corresponding to the source extended inverted fin; preferably, the active layer It includes a channel layer on the bottom layer, a source field junction on the channel layer and on both sides of the trench opening, the source field junction is formed by ion implantation at an oblique angle, and is used for connecting the grooves in the recessed area of the trench. The source layer is to the two sides corresponding to the first gate and the second gate; more preferably, the active layer further includes an ohmic contact layer on the top layer, separated and exposed between the source field junctions On the treated surface, the thickness of the ohmic contact layer is smaller than the sinking depth of the source region junction.

通过采用上述技术方案，利用位于处理表面上的源极层与嵌埋于漏极外延层的栅极,建立以有源层沟道层厚度方向定义的多个竖立并联沟道，电子流能均匀输出(或输入)在背面。当半导体芯片装置安装在载板上即完成源极或/与漏极接触连接,能节省一个或全部电极位的连接操作，随着芯片越来越薄,不需要考虑芯片背面漏电流的问题。By adopting the above technical solution, using the source layer located on the processing surface and the gate embedded in the drain epitaxial layer, a plurality of vertical parallel channels defined by the thickness direction of the active layer channel layer are established, and the electron flow can be uniform. The output (or input) is on the back. When the semiconductor chip device is mounted on the carrier board, the source or/and drain contact connection is completed, which can save the connection operation of one or all electrode positions. As the chip becomes thinner and thinner, there is no need to consider the problem of leakage current on the back of the chip.

综上所述，本发明的技术方案包括以下至少一种对现有技术作出贡献的技术效果：To sum up, the technical solutions of the present invention include at least one of the following technical effects that contribute to the prior art:

1.通过用于嵌埋源极延伸倒鳍与第二栅极的第一沟槽与用于嵌埋第一栅极的第二沟槽形成位于处理表面上的自对准掩膜体，避免了以处理表面作为台面(mesa)区形成接触孔，使台面(mesa)的面积减少，可以提升器件的电流密度20%以上;1. A self-aligned mask body on the processing surface is formed by the first trench for burying the source extension fin and the second gate and the second trench for burying the first gate to avoid In order to form contact holes with the treated surface as the mesa area, the area of the mesa (mesa) is reduced, and the current density of the device can be increased by more than 20%;

2.通过第一栅极与第二栅极两侧提升纵向沟道排列密度，使沟道导通电阻降低且并联数量增加;2. The vertical channel arrangement density is increased on both sides of the first gate and the second gate, so that the channel on-resistance is reduced and the number of parallel connections is increased;

3.浮空反极型柱底结(具体如P柱)引入能增加平台的拓展性，在其它工艺不变的情况下拓展半导体器件的击穿电压等级，减少工艺开发导致的成本增加，减少了产线切换成本提升工艺共用性;3. The introduction of floating reverse pole bottom junction (such as P-pillar) can increase the scalability of the platform, expand the breakdown voltage level of semiconductor devices under the condition that other processes remain unchanged, reduce the cost increase caused by process development, reduce Reduce production line switching costs and improve process commonality;

4.通过多次自对准工艺实现了器件对光刻加工精度波动的免疫，加工工艺窗口增大，有源层的制作形成不是全表面实施就是在自对准掩膜体下图案化形成，光刻加工精度波动不影响有源层的制作;4. The device is immune to fluctuations in lithography processing accuracy through multiple self-alignment processes, the processing window is increased, and the fabrication of the active layer is either implemented on the full surface or patterned under the self-aligned mask body. Fluctuations in lithography processing accuracy do not affect the fabrication of the active layer;

5.在制造上能够只通过四次光刻(对应到以下具体实施方式的光刻定义第一沟槽的步骤S3、光刻定义第二沟槽的步骤S91、光刻定义源极与栅极接触孔的步骤S191以及光刻定义出顶面上的源极接触区的步骤S203)便能形成了整个完整的半导体器件，相比传统半导体器件制造工艺的技术转用至少减少了一半光刻次数，例如中间制程的有源层、源极领域结、第一隔离氧化层以及第二隔离氧化层的图案化上都是基于第一沟槽与第二沟槽在处理表面下的物理形状实现自对准，使加工流程和加工成本大幅下降;5. Only four times of photolithography can be used in manufacturing (corresponding to step S3 of defining the first trench by photolithography, step S91 of defining the second trench by photolithography, and step S91 of defining the source electrode and gate electrode by photolithography in the following specific embodiments) The step S191 of the contact hole and the step S203 of defining the source contact region on the top surface by photolithography can form the entire semiconductor device, which reduces the number of photolithography by at least half compared to the technology transfer of the traditional semiconductor device manufacturing process. For example, the patterning of the active layer, the source field junction, the first isolation oxide layer and the second isolation oxide layer in the intermediate process is based on the physical shape of the first trench and the second trench under the treatment surface. Alignment, which greatly reduces the processing flow and processing cost;

6.实现单位源包（cell）的尺寸降低，使器件的优值（FOM=Rdson*Qg）特性得到大幅提升;其中Rdson表示漏极/源极通态电阻;Qg表示总栅极充电电荷量;FOM(Figure ofmerit)为优值,或称质量因子,是衡量功率器件设计优劣的重要标准,FOM越小表明器件的性能越佳;以漏极外延层内隔离栅之间纵向多组成对并联的对称型沟道,个别沟道长度变短并且沟道并联数量倍数增加,缩小源极与漏极之间的Rdson值或/与Qg值,在有限处理表面内功率型半导体器件优值能更好的缩小。6. The size of the unit source package (cell) is reduced, so that the figure of merit (FOM=Rdson*Qg) characteristics of the device are greatly improved; where Rdson represents the drain/source on-state resistance; Qg represents the total gate charge amount ;FOM (Figure of Merit) is the figure of merit, or quality factor, which is an important criterion to measure the pros and cons of power device design. The smaller the FOM, the better the performance of the device; the vertical multiple pairs between the isolation gates in the drain epitaxial layer For parallel symmetric channels, the individual channel lengths are shortened and the number of parallel channels is increased by multiples, reducing the Rdson value or/and Qg value between the source and drain, and the figure of merit of power semiconductor devices in a limited processing surface. Better zoom out.

附图说明Description of drawings

图1绘示本发明一些较佳实施例的场效晶体管结构在横切栅极的局部结构示意图；FIG. 1 is a schematic diagram illustrating a partial structure of a field effect transistor structure in a cross-section gate according to some preferred embodiments of the present invention;

图2绘示本发明一些较佳实施例的制作场效晶体管结构的过程中所提供漏极衬底的示意图；2 is a schematic diagram illustrating a drain substrate provided in a process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;

图3绘示本发明一些较佳实施例的制作场效晶体管结构的过程中由漏极外延层的处理表面刻蚀形成相互平行的第一沟槽的示意图；3 is a schematic diagram illustrating the formation of mutually parallel first trenches by etching the treated surface of the drain epitaxial layer in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图4绘示本发明一些较佳实施例的制作场效晶体管结构的过程中在第一沟槽底部的部位离子植入形成屏蔽栅底部浮空反极型柱底结的示意图；4 is a schematic diagram illustrating the formation of a floating inversion column bottom junction at the bottom of the shielded gate by ion implantation at the bottom of the first trench in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图5绘示本发明一些较佳实施例的制作场效晶体管结构的过程中在处理表面上与第一沟槽内形成第一效应氧化层的示意图；5 is a schematic diagram illustrating the formation of a first effect oxide layer on the treated surface and in the first trench in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图6绘示本发明一些较佳实施例的制作场效晶体管结构的过程中在第一沟槽内形成源极延伸倒鳍的示意图；6 is a schematic diagram illustrating the formation of a source extension inverted fin in the first trench in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图7绘示本发明一些较佳实施例的制作场效晶体管结构的过程中去除源极延伸倒鳍与第一效应氧化层在处理表面上部位的示意图；7 is a schematic diagram illustrating the removal of the source extension back fin and the first effect oxide layer on the treated surface in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图8绘示本发明一些较佳实施例的制作场效晶体管结构的过程中形成第一硬掩膜层在处理表面上与源极延伸倒鳍上的示意图；8 is a schematic diagram illustrating the formation of a first hard mask layer on the processing surface and the source extension back fin in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图9绘示本发明一些较佳实施例的制作场效晶体管结构的过程中由处理表面刻蚀形成第二沟槽的示意图；9 is a schematic diagram illustrating the formation of the second trench by etching the treated surface in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图10绘示本发明一些较佳实施例的制作场效晶体管结构的过程中刻蚀第一硬掩膜层形成为源极延伸倒鳍上的第一硬掩膜氧化膜的示意图；10 is a schematic diagram illustrating a first hard mask oxide film formed by etching a first hard mask layer to form a source extension back fin in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;

图11绘示本发明一些较佳实施例的制作场效晶体管结构的过程中在处理表面上、第二沟槽内与第一沟槽的剩余空间内形成第二效应氧化层的示意图；11 is a schematic diagram illustrating the formation of a second effect oxide layer on the treated surface, in the second trench and in the remaining space of the first trench in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图12绘示本发明一些较佳实施例的制作场效晶体管结构的过程中在第二沟槽内设置第一栅极以及在第一沟槽的剩余空间内形成的第二栅极的示意图；12 is a schematic diagram illustrating the first gate disposed in the second trench and the second gate formed in the remaining space of the first trench in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图13绘示本发明一些较佳实施例的制作场效晶体管结构的过程中去除第一栅极与第二栅极相接在所述处理表面上的部位的示意图；13 is a schematic diagram illustrating the removal of the portion where the first gate electrode and the second gate electrode are connected to the processing surface in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图14绘示本发明一些较佳实施例的制作场效晶体管结构的过程中在处理表面下以能量注入方式形成有源层的示意图；14 is a schematic diagram illustrating the formation of an active layer by energy injection under the treatment surface in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;

图15绘示本发明一些较佳实施例的制作场效晶体管结构的过程中由第二硬掩膜沉淀形成为在所述第一栅极与所述第二栅极上的第二隔离氧化层以及在所述处理表面上的自对准掩膜体的示意图；FIG. 15 illustrates a second isolation oxide layer formed on the first gate and the second gate by deposition of a second hard mask in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention. and a schematic diagram of a self-aligned mask body on the treated surface;

图16绘示本发明一些较佳实施例的制作场效晶体管结构的过程中以斜角离子注入形成源极领域结的示意图；16 is a schematic diagram illustrating the formation of a source-field junction by oblique ion implantation in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;

图17绘示本发明一些较佳实施例的制作场效晶体管结构的过程中以沉淀覆盖方式在处理表面上形成内介电层的示意图；17 is a schematic diagram illustrating the formation of an internal dielectric layer on the treated surface by means of deposition coverage in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;

图18绘示本发明一些较佳实施例的制作场效晶体管结构的过程中以刻蚀方式形成在所述第一栅极上与所述第二栅极上的内介电层的示意图；18 is a schematic diagram illustrating the inner dielectric layers formed on the first gate electrode and the second gate electrode by etching in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图19绘示本发明一些较佳实施例的制作场效晶体管结构的过程中以离子注入方式形成位于有源层顶层的欧姆接触层的示意图；19 is a schematic diagram of forming an ohmic contact layer on the top layer of the active layer by ion implantation in the process of fabricating the field effect transistor structure according to some preferred embodiments of the present invention;

图20绘示本发明一些较佳实施例的制作场效晶体管结构的过程中在处理表面上形成源极层的示意图；20 is a schematic diagram illustrating the formation of a source layer on the treated surface in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;

图21绘示本发明一些较佳实施例中所制得的场效晶体管结构在使用状态中电子流流动示意图。FIG. 21 is a schematic diagram illustrating the flow of electron flow in the use state of the field effect transistor structure fabricated in some preferred embodiments of the present invention.

附图标记: 1、漏极衬底;10、漏极外延层;11、处理表面;12、背面;13、第一沟槽;14、表面酸化膜;15、主体区;16、漏极金属垫; 17、参杂浓度清晰变化水平面;20、源极延伸倒鳍; 30、有源层;31、第二沟槽;32、沟道层;33、源极领域结;34、欧姆接触层; 41、第一栅极;42、第二栅极;50、内介电层; 60、源极层;70、浮空反极型柱底结; 81、第一隔离氧化层;82、第二隔离氧化层; 81A、第一硬掩膜层;82B、自对准掩膜体; 91、第一效应氧化层;92、第二效应氧化层。Reference numerals: 1. Drain substrate; 10. Drain epitaxial layer; 11. Treated surface; 12. Back surface; 13. First trench; 14. Surface acidizing film; 15. Body region; 16. Drain metal Pad; 17. The level of doping concentration changes clearly; 20, the source extends the inverted fin; 30, the active layer; 31, the second trench; 32, the channel layer; 33, the source field junction; 34, theohmic contact layer 41, the first gate; 42, the second gate; 50, the inner dielectric layer; 60, the source layer; 70, the floating reverse pole bottom junction; 81, the first isolation oxide layer; 82, the first Two isolation oxide layers; 81A, the first hard mask layer; 82B, the self-aligned mask body; 91, the first effect oxide layer; 92, the second effect oxide layer.

具体实施方式Detailed ways

下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是作为理解本发明的发明构思一部分实施例，而不能代表全部的实施例，也不作唯一实施例的解释。基于本发明中的实施例，本领域普通技术人员在理解本发明的发明构思前提下所获得的所有其他实施例，都属于本发明保护的范围内。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments for understanding the inventive concept of the present invention, and cannot represent All embodiments are not to be interpreted as the only embodiment. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art on the premise of understanding the inventive concept of the present invention fall within the protection scope of the present invention.

需要说明，若本发明实施例中有涉及方向性指示(诸如上、下、左、右、前、后……)，则该方向性指示仅用于解释在某一特定姿态下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。为了更方便理解本发明的技术方案,以下将本发明的多栅极变化的场效晶体管结构及其制造方法、芯片装置做进一步详细描述与解释，但不作为本发明限定的保护范围。以下实施例中以N型场效晶体管表示,在不同示例变化上也可以调整为P型场效晶体管,并且,本领域技术人员应当知道说明书所指的源极与漏极是一种相对概念,不是绝对概念,在变化例具体应用中,示例的源极可以作为漏极连接使用,示例的漏极可以作为源极连接使用,当说明书中记载的源极作为源极连接,当说明书中记载的漏极必然作为漏极连接;当说明书中记载的源极作为漏极连接,当说明书中记载的漏极必然作为源极连接。为了方便理解本申请的技术方案,说明书与保护范围仍使用“源极”与“漏极”,实际上不限定于于源极与漏极,而是使用上代表两个不同电位极的第一电极与第二电极。此外,说明书中记载的“反极”即是与基础极相反的电极,例如源漏极的基础极是N型,则反极是P型,反之亦然。因此,本领域技术人员在理解本发明的技术方案后能把半导体器件的“源极”与“漏极”进行互换,也能把N型源漏极与P型沟道的组合更换为P型源漏极与N型沟道的组合,本发明的保护范围自然也包含这样的等效互换。It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) involved in the embodiments of the present invention, the directional indications are only used to explain the relationship between various components in a specific posture If the specific posture changes, the directional indication also changes accordingly. In order to more easily understand the technical solutions of the present invention, the multi-gate variable field effect transistor structure, its manufacturing method, and the chip device of the present invention will be described and explained in further detail below, but it is not a protection scope limited by the present invention. In the following embodiments, an N-type field effect transistor is used, and it can also be adjusted to a P-type field effect transistor in different example changes, and those skilled in the art should know that the source electrode and the drain electrode referred to in the description are a relative concept, It is not an absolute concept. In the specific application of the variation, the source of the example can be used as a drain connection, and the drain of the example can be used as a source connection. When the source described in the specification is used as the source connection, when the The drain must be connected as the drain; when the source described in the specification is connected as the drain, the drain described in the specification must be connected as the source. In order to facilitate the understanding of the technical solution of the present application, the description and protection scope still use "source" and "drain", which are not limited to the source and the drain, but use the first electrode representing two different potential electrodes. electrode and second electrode. In addition, the "reverse electrode" described in the specification is the electrode opposite to the base electrode. For example, the base electrode of the source and drain is N-type, and the reverse electrode is P-type, and vice versa. Therefore, those skilled in the art can exchange the "source" and "drain" of the semiconductor device after understanding the technical solution of the present invention, and can also replace the combination of N-type source-drain and P-type channel with P-type The combination of type source-drain type and N-type channel, the protection scope of the present invention naturally also includes such an equivalent interchange.

此外,文中提及的“效应氧化层”与“隔离氧化层”的区别在于,栅极或隔离栅透过“效应氧化层”还能发挥电效应作用,“隔离氧化层”是隔离了电效应作用。通常“隔离氧化层”的厚度是大于作为栅氧功能的“效应氧化层”的厚度,而与其他非用于栅氧功能的“效应氧化层”的厚度没有决定关系。“隔离氧化层”的隔离功能不单纯只考虑个别厚度,而要是与其他叠层绝缘层相加下能发挥场效应隔离作用也称之为“隔离氧化层”。In addition, the difference between the "effect oxide layer" and the "isolation oxide layer" mentioned in the article is that the gate or isolation gate can also play an electrical effect through the "effect oxide layer", and the "isolation oxide layer" isolates the electrical effect. effect. Usually, the thickness of the "isolation oxide layer" is greater than the thickness of the "effect oxide layer" that functions as a gate oxide, and has no decisive relationship with the thickness of other "effect oxide layers" that are not used for the gate oxide function. The isolation function of the "isolation oxide layer" does not only consider the individual thickness, but if it is combined with other laminated insulating layers, it can play a field effect isolation effect, which is also called "isolation oxide layer".

图1绘示本发明一些较佳实施例的场效晶体管结构在横切栅极的局部结构示意图,图2至图20绘示本发明一些较佳实施例的场效晶体管结构在制程个别步骤的示意图,图21绘示本发明一些较佳实施例的场效晶体管结构在使用状态的示意图。附图所示包括多个实施例具有共性的部分，变化例具有差异或区别的部分另以文字方式描述。因此，应当基于产业特性与技术本质，熟知本领域的技术人员应正确且合理的理解与判断以下所述的个别技术特征或其任意多个的组合是否能够表征到同一实施例，或者是多个技术本质互斥的技术特征仅能分别表征到不同变化实施例。FIG. 1 is a schematic diagram showing the partial structure of the field effect transistor structure in the cross-gate according to some preferred embodiments of the present invention, and FIG. 2 to FIG. 20 are the schematic diagrams of the field effect transistor structure of some preferred embodiments of the present invention in individual steps of the process. Schematic diagram, FIG. 21 is a schematic diagram of the field effect transistor structure of some preferred embodiments of the present invention in a use state. The figures shown in the drawings include the common parts of the various embodiments, and the parts with differences or differences in the variations are also described in text. Therefore, based on industrial characteristics and technical nature, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features described below or any combination of any of them can represent the same embodiment, or whether multiple Technical features that are technically mutually exclusive can only be represented by different variant embodiments.

参照图1，为本发明实施例公开的一种多栅极变化的场效晶体管结构，主要包括:漏极衬底1、以分区电子流的源极延伸倒鳍20、开关电子流的有源层30、位于源极延伸倒鳍20之间的第一栅极41、对准在源极延伸倒鳍20上的第二栅极42以及位于顶部的源极层60,以实现场效晶体管电子流开关的功能。本实施例以N型场效应晶体管表示,在变化例中本领域技术人员应当能调整为P型场效应晶体管。源极延伸倒鳍20的下沉深度大于第一栅极41的下沉深度,而呈反置倒鳍型。Referring to FIG. 1 , a multi-gate variable field effect transistor structure disclosed in an embodiment of the present invention mainly includes: a drain substrate 1, a source extending theinverted fin 20 for partitioning the electron flow, and an active switch for switching the electron flow.Layer 30, afirst gate 41 between thesource extension fins 20, asecond gate 42 aligned on thesource extension fins 20, and asource layer 60 on top to realize the field effect transistor electronic function of the flow switch. This embodiment is represented by an N-type field effect transistor, and those skilled in the art should be able to adjust it to a P-type field effect transistor in the modified example. The sinking depth of the source extendinginverted fin 20 is greater than the sinking depth of thefirst gate electrode 41 , and the inverted fin type is formed.

漏极衬底1具有由漏极外延层10提供的处理表面11与对应的背面12，由所述处理表面11形成有相互平行的第一沟槽13，所述第一沟槽13的内壁绝缘处理，所述第一沟槽13内设置源极延伸倒鳍20，所述第一沟槽13的深度不超过所述漏极外延层10的厚度。具体的,源极延伸倒鳍20位于第一沟槽13的底部。漏极衬底1在半导体制程中是半导体晶圆,在产品中是切单后的芯片基础层，漏极衬底1的基础材质通常是硅,也可以是碳化硅、III-V族或II-VI化合物,在掺杂电子提供物质或电洞提供物质后具有导电性,掺杂区域在芯片有效区,可以全面也可以区块状,示例是重N型掺杂。漏极衬底1通常是单晶结构,就N型晶体管具体例如是N+单晶硅。漏极外延层10是由漏极衬底1磊晶外延生长的功能层,通常与漏极衬底1具有相同的晶向,也是单晶结构,就N型晶体管具体例如N-单晶硅,导电性低于漏极衬底1。漏极外延层10的一个作用是在漏极外延层10与漏极衬底1之间提供掺杂浓度清晰变化的水平面17,以利于沟道竖立式场效晶体管的半导体制作。处理表面11是半导体工艺的处理表面，背面12是相反于处理表面11的表面。第一沟槽13由处理表面11形成,表示第一沟槽13的开口朝向处理表面11，第一沟槽13的底部朝向背面12,第一沟槽13没有贯通漏极外延层10。图中绘示的虽然只有两个第一沟槽13,但实际上是两条以上的多条,沟槽数量可以调整,图1中的结构在左右两侧可以适当的重复展开;较优的沟槽形状在处理表面111上是多个平行直条状,但也可以是平行具有相同间隔的各种弯曲形状。使用上源极延伸倒鳍20应与源极保持相同的场电压,源极延伸倒鳍20为导电性,材质优选为多晶态的导电硅或其他导电性半导体材料,能与漏极外延层10有着相同或相近的热膨胀适配性;在其他示例中也可以是半导体工艺中使用的导电材料,例如：钨、铜、铝,常用为钨。源极延伸倒鳍20的结构可以如图1所示的单层结构也可以是多层叠加结构。The drain substrate 1 has a processedsurface 11 and acorresponding back surface 12 provided by thedrain epitaxial layer 10 , the processedsurface 11 is formed with afirst trench 13 parallel to each other, and the inner wall of thefirst trench 13 is insulated. In the process, thesource extension fin 20 is disposed in thefirst trench 13 , and the depth of thefirst trench 13 does not exceed the thickness of thedrain epitaxial layer 10 . Specifically, thesource extension fin 20 is located at the bottom of thefirst trench 13 . The drain substrate 1 is a semiconductor wafer in the semiconductor manufacturing process, and is a chip base layer after dicing in the product. The base material of the drain substrate 1 is usually silicon, or silicon carbide, III-V group or II. The -VI compound has conductivity after doping with electron-donating material or hole-donating material. The doping area is in the effective area of the chip, which can be comprehensive or block-shaped. An example is heavy N-type doping. The drain substrate 1 is usually a single crystal structure, for example, an N+ single crystal silicon for an N-type transistor. Thedrain epitaxial layer 10 is a functional layer epitaxially grown from the drain substrate 1, usually has the same crystal orientation as the drain substrate 1, and is also a single crystal structure. For N-type transistors, such as N-single crystal silicon, The conductivity is lower than that of the drain substrate 1 . One function of thedrain epitaxial layer 10 is to provide alevel surface 17 with clearly varying doping concentration between thedrain epitaxial layer 10 and the drain substrate 1, so as to facilitate semiconductor fabrication of the channel vertical field effect transistor. The treatedsurface 11 is the treated surface for the semiconductor process, and thebackside 12 is the opposite surface to the treatedsurface 11 . Thefirst trench 13 is formed by the treatedsurface 11 , indicating that the opening of thefirst trench 13 faces the treatedsurface 11 , the bottom of thefirst trench 13 faces theback surface 12 , and thefirst trench 13 does not penetrate thedrain epitaxial layer 10 . Although there are only twofirst grooves 13 shown in the figure, there are actually more than two grooves, the number of grooves can be adjusted, and the structure in FIG. 1 can be appropriately repeated on the left and right sides; The groove shape is a plurality of parallel straight strips on the processing surface 111, but may be various curved shapes in parallel with the same interval. Using the uppersource extension fin 20 should maintain the same field voltage as the source, thesource extension fin 20 is conductive, and the material is preferably polycrystalline conductive silicon or other conductive semiconductor materials, which can be connected with the drain epitaxial layer. 10 has the same or similar thermal expansion compatibility; in other examples, it can also be a conductive material used in semiconductor processing, such as: tungsten, copper, aluminum, commonly used as tungsten. The structure of the source extension invertedfin 20 may be a single-layer structure as shown in FIG. 1 or a multi-layer stack structure.

有源层30形成于所述漏极外延层10中，由所述有源层30形成有位于所述第一沟槽13之间的第二沟槽31，所述第二沟槽31的内壁绝缘处理，所述第二沟槽31内设置第一栅极41，所述第二沟槽31的第二深度足以贯穿所述有源层30但小于所述第一沟槽13的第一深度;设置所述第一栅极41的同时还在所述第一沟槽41内对准所述源极延伸倒鳍20的上方设置有第二栅极42;所述第二栅极42与所述第一栅极41具有不同的形状轮廓。有源层30的一部分(沟道层)是受到第一栅极41与第二栅极42的电场作用形成电子流的开通与关闭。在本优选实施例中,有源层30是由漏极外延层10内生形成,例如对漏极外延层10进行反极型离子植入或还包括同极型的离子植入,有源层30与漏极外延层10有一体适配的晶格结构;在一变化示例中，有源层30是由漏极外延层10表面外延生长。第二沟槽31的底部高于第一沟槽13的底部,即相比于第一沟槽13,第二沟槽31的底部更靠近处理表面11。第一栅极41与第二栅极42不超过处理表面11上而为嵌埋形态。第一栅极41与第二栅极42为导电性,材质优选为多晶态的导电硅或其他导电性半导体材料,能与漏极外延层10有着相同或相近的热膨胀适配性;在其他示例中也可以采用半导体工艺中使用的其他导电材料,例如：钨、铜、铝,常用为钨。第一栅极41的结构可以如图1所示的单层结构也可以是多层叠加结构。第一栅极41的底部形状与第二栅极42的底部形状可以不相同;例如，第一栅极41的底部形状为往下突出的圆弧形切面，第二栅极42的底部形状为往下突出的非圆弧形切面,其分别作用是：第一栅极41更容易成形以及增加第二栅极42与源极延伸倒鳍20的结合。又图1示例中，浮空反极型柱底结70对应沟槽宽度的尺寸能大于第一沟槽13的宽度。Anactive layer 30 is formed in thedrain epitaxial layer 10 , and asecond trench 31 between thefirst trenches 13 is formed by theactive layer 30 , and the inner wall of thesecond trench 31 is Insulation treatment, afirst gate 41 is disposed in thesecond trench 31 , the second depth of thesecond trench 31 is sufficient to penetrate theactive layer 30 but less than the first depth of thefirst trench 13 ; While setting thefirst gate 41, asecond gate 42 is provided above thesource extension fin 20 in thefirst trench 41; thesecond gate 42 is connected to the Thefirst gate electrode 41 has different shape profiles. A part of the active layer 30 (the channel layer) is turned on and off by the electric field of thefirst gate 41 and thesecond gate 42 to form an electron flow. In the present preferred embodiment, theactive layer 30 is formed by endogenous formation of thedrain epitaxial layer 10 . For example, thedrain epitaxial layer 10 is implanted with reverse ion implantation or also includes homopolar ion implantation. 30 and thedrain epitaxial layer 10 have an integrally adapted lattice structure; in a variant example, theactive layer 30 is epitaxially grown from the surface of thedrain epitaxial layer 10 . The bottom of thesecond trench 31 is higher than the bottom of thefirst trench 13 , that is, the bottom of thesecond trench 31 is closer to theprocessing surface 11 than thefirst trench 13 . Thefirst gate electrode 41 and thesecond gate electrode 42 do not exceed the processedsurface 11 but are embedded. Thefirst gate 41 and thesecond gate 42 are conductive, and the material is preferably polycrystalline conductive silicon or other conductive semiconductor materials, which can have the same or similar thermal expansion compatibility with thedrain epitaxial layer 10; in other Other conductive materials used in semiconductor processes, such as tungsten, copper, aluminum, commonly used as tungsten, can also be used in the example. The structure of thefirst gate 41 may be a single-layer structure as shown in FIG. 1 or a multi-layer stacking structure. The bottom shape of thefirst gate 41 and the bottom shape of thesecond gate 42 may be different; for example, the bottom shape of thefirst gate 41 is a downwardly protruding arc-shaped section, and the bottom shape of thesecond gate 42 is The non-circular arc-shaped sections protruding downward have the respective functions of: thefirst gate 41 is easier to form and the combination of thesecond gate 42 and thesource extension fin 20 is increased. In the example of FIG. 1 , the size of the floating inversioncolumn bottom junction 70 corresponding to the width of the trench can be larger than the width of thefirst trench 13 .

内介电层50形成于所述第一栅极41与所述第二栅极42上,使所述第一栅极41与所述第二栅极42为嵌埋结构。内介电层50为绝缘性质,隔离了第一栅极41与源极层60以及隔离了第二栅极42与源极层60，内介电层50的材质具体可为氧化硅、PSG（磷硅玻璃）或BPSG（硼磷硅玻璃）,以有效隔离源极与栅极。图中绘示的内介电层50虽然只有一层,在不同变化示例中可以是多层叠加的绝缘结构。至于源极延伸倒鳍20与源极层60的接触孔连接以及栅极41,42与顶面栅极垫的接触孔连接可位于处理表面111的台面(mesa)区域以外,图未示出。被嵌埋的第一栅极41与第二栅极42可以利用其本身的端部延伸或连接引线将电信号引拉到台面区域之外，第一栅极41与第二栅极42的场电位可以独立调整或共同调整。在源极接触区内以其他接触孔贯穿内介电层50，使源极延伸倒鳍20与源极层60等电位连接，不需要额外设置控制信号线与控制电极。Theinner dielectric layer 50 is formed on thefirst gate 41 and thesecond gate 42, so that thefirst gate 41 and thesecond gate 42 are embedded structures. Theinner dielectric layer 50 is an insulating property, which isolates thefirst gate 41 and thesource layer 60 and isolates thesecond gate 42 and thesource layer 60. The material of theinner dielectric layer 50 may specifically be silicon oxide, PSG ( Phosphosilicate glass) or BPSG (Borophosphosilicate glass) to effectively isolate the source and gate. Although theinner dielectric layer 50 shown in the figure has only one layer, in different variation examples, it may be a multi-layer stacked insulating structure. The contact hole connection between thesource extension fin 20 and thesource layer 60 and the contact hole connection between thegates 41, 42 and the top gate pad may be located outside the mesa region of the processing surface 111, which is not shown. The embeddedfirst gate 41 and thesecond gate 42 can use their own end extensions or connecting leads to pull electrical signals out of the mesa area. The field of thefirst gate 41 and thesecond gate 42 Potentials can be adjusted independently or jointly. In the source contact region, other contact holes penetrate through theinner dielectric layer 50 , so that thesource extension fin 20 and thesource layer 60 are equipotentially connected, and additional control signal lines and control electrodes are not required.

源极层60形成于所述漏极外延层10上，所述源极层60等电位连接所述源极延伸倒鳍20，所述场效晶体管的沟道分别位于所述第一栅极41的两侧与所述第二栅极42的绝缘壁外两侧,沟道为多个纵向并联且成对形态，能取代现有技术中以有源层30的厚度方向定义场效晶体管的沟道长度，以提供竖立向于处理表面11且在源极延伸倒鳍20之间的多个且短距离的并联晶体管沟道。本实施例中，源极层60是几乎整面覆盖在处理表面11上的单元台面区，还能保留栅极接触区，即源极层60在栅极接触区分割为栅极接触。源极层60导通至源极延伸倒鳍20，源极层60为导电性,材质优选为铝或其他导电金属材料,额外具有金属垫的作用,以省略金属垫的制作;在其他示例中源极层60也可以采用半导体工艺中使用的其他导电材料,例如：钨、铜、多晶态的导电硅。该源极层60的结构可以如图1所示的单层结构也可以是多层叠加结构。有源区30的主体层是反型注入层,即沟道层32,该层厚度方向具体作为晶体管沟道的长度方向。Thesource layer 60 is formed on thedrain epitaxial layer 10 , thesource layer 60 is equipotentially connected to the source extension backfin 20 , and the channels of the field effect transistors are located at thefirst gate 41 respectively The two sides of thesecond gate electrode 42 and the outer two sides of the insulating wall of thesecond gate electrode 42, the channel is a plurality of vertical parallel and paired forms, which can replace the channel of the field effect transistor defined by the thickness direction of theactive layer 30 in the prior art. track length to provide multiple and short distance parallel transistor channels that stand between thehandle surface 11 and the source extending backfins 20 . In this embodiment, thesource layer 60 is a unit mesa region covering almost the entire surface of theprocessing surface 11 , and the gate contact region can still be reserved, that is, thesource layer 60 is divided into gate contacts in the gate contact region. Thesource layer 60 is connected to the source extending backfin 20, thesource layer 60 is conductive, and the material is preferably aluminum or other conductive metal materials, and additionally has the function of a metal pad, so as to omit the production of the metal pad; in other examples Thesource layer 60 can also be made of other conductive materials used in semiconductor processes, such as tungsten, copper, and polycrystalline conductive silicon. The structure of thesource layer 60 may be a single-layer structure as shown in FIG. 1 or a multi-layer stacking structure. The main body layer of theactive region 30 is an inversion injection layer, namely thechannel layer 32, and the thickness direction of the layer is specifically the length direction of the transistor channel.

实施例的基础原理为：利用排列于源极延伸倒鳍20之间的第一栅极41与位于源极延伸倒鳍20上的第一栅极42，嵌埋第一栅极41的第二沟槽31的第二深度足以贯穿有源层30但小于嵌埋源极延伸倒鳍20与第二栅极42的第一沟槽13的第一深度,实现了隔离栅之间纵向沟道的密集化,在源极与漏极之间的电子流分区且均匀化;此外,以第二栅极42与第一栅极41具有不同的形状轮廓,分别由第一沟槽13的中段形状与第二沟槽31的底部形状定义形成,有源区30内在第二栅极42与第一栅极41的两侧外各形成纵向沟道,使漏极外延层10或/与漏极衬底1的电子流不易跨过以源极延伸倒鳍20形成的隔离栅。The basic principle of the embodiment is: using thefirst gate 41 arranged between the source extendedinverted fins 20 and thefirst gate 42 located on the source extendedinverted fin 20 to embed the second gate of thefirst gate 41 . The second depth of thetrenches 31 is sufficient to penetrate theactive layer 30 but is smaller than the first depth of thefirst trenches 13 embedded in the source extension backfins 20 and thesecond gate electrodes 42, so as to realize the longitudinal channel separation between the isolation gates. Densification, the electron flow between the source and the drain is partitioned and uniform; in addition, thesecond gate 42 and thefirst gate 41 have different shape profiles, which are respectively determined by the shape of the middle section of thefirst trench 13 and the shape of thefirst gate 41. The bottom shape of thesecond trench 31 is defined and formed, and a vertical channel is formed in theactive region 30 on both sides of thesecond gate 42 and thefirst gate 41, so that thedrain epitaxial layer 10 or/and the drain substrate are formed. The electron flow of 1 cannot easily cross the isolation barrier formed by the source-extendedinverted fin 20 .

由于第一栅极41与第二栅极42的埋入深度突破所述有源层30到达所述漏极外延层10的内部，在埋入式栅极41,42两侧形成相对于处理表面11纵向且并联的成对短沟道;漏极衬底1的背面12可作为漏极垫16的接触,电子流的移动是由处理表面11到漏极外延层10的背面12,过程中是经过了源极延伸倒鳍20的分区隔开以及对应第一栅极41与第二栅极42两侧的每一侧绝缘处理的其中一侧沟道的多个半栅极开关导通,在源极延伸倒鳍20的分区的场效应分区流动在漏极衬底1的背面12,实现了分区内四个或四个以上相邻源极分路下的半栅晶体管两侧沟道导通在漏极衬底1的背面12,使原本衬底背面漏电流的缺陷转换成有益与有意义的漏极输出,并且避免了电子流如熔丝效应集中于漏极衬底1的背面12的局部区域。Since the buried depths of thefirst gate 41 and thesecond gate 42 break through theactive layer 30 and reach the inside of thedrain epitaxial layer 10 , a surface opposite to the processing surface is formed on both sides of the buriedgates 41 and 42 . 11 Longitudinal and parallel paired short channels; thebackside 12 of the drain substrate 1 can be used as a contact for thedrain pad 16, and the movement of the electron flow is from the treatedsurface 11 to thebackside 12 of thedrain epitaxial layer 10, and the process is The plurality of half-gate switches on one side of the channel after the partitioning of the source extendinginverted fin 20 and the insulation treatment corresponding to each side of thefirst gate 41 and thesecond gate 42 are turned on. The field effect partition of the partition of the source extendinginverted fin 20 flows on theback surface 12 of the drain substrate 1, realizing channel conduction on both sides of the half-gate transistor under four or more adjacent source shunts in the partition On thebackside 12 of the drain substrate 1, the original defect of the backside leakage current of the substrate is converted into a beneficial and meaningful drain output, and the electron flow such as the fuse effect is avoided to concentrate on thebackside 12 of the drain substrate 1. Partial area.

此外,利用源极层60与源极延伸倒鳍20制程上分离设计与结构上导通,提供了漏极外延层10内隔离栅的作用,工艺上源极层60只需要在器件台面之外设置接触孔连接即可,而不需要额外制作其他沟槽,源极延伸倒鳍20的材质选择具有更多自由度,以克服工艺填孔填槽的困难、提高源极延伸倒鳍20与漏极外延层10的热膨胀适配度。In addition, the use of thesource layer 60 and the source extension invertedfin 20 is used to separate the design in the process and conduct on the structure, so as to provide the function of isolation gate in thedrain epitaxial layer 10, and thesource layer 60 only needs to be outside the device mesa in the process. It is enough to set the contact hole connection, without the need to make additional trenches, the material selection of thesource extension fin 20 has more degrees of freedom, so as to overcome the difficulty of filling the hole and fill the groove in the process, and improve thesource extension fin 20 and the drain. The degree of thermal expansion adaptation of theextreme epitaxial layer 10 .

关于源极层60与有源层30的具体化,在较佳示例中,所述源极层60还形成于所述内介电层50上;所述有源层30由所述漏极外延层10的所述处理表面11内化形成，所述内介电层50凹陷于所述处理表面11,以利所述源极层60与所述有源区30的欧姆接触的结合。利用还形成于所述内介电层50上的源极层60,源极层60跨过源极延伸倒鳍20的隔离导通相接在内介电层50上,以扩大源极接触。所述内介电层50电绝缘所述第一栅极41顶部与延伸其上的源极层60,以及电绝缘所述第二栅极42顶部与延伸其上的源极层60。器件结构中少了内介电层50在处理表面11上的沉淀厚度而能更薄。当所述有源层30由所述漏极外延层10的所述处理表面11内化形成,所述有源层30与所述漏极外延层10两者的晶格匹配,没有界面间隙的缺陷,晶体管的沟道结构与漏极外延层10成为一体结构,在电性能稳定度上优于外延生长的有源层或沟道层;当所述源极层60与所述有源区30之间为欧姆接触的结合,能缩小两者的电阻。Regarding the embodiment of thesource layer 60 and theactive layer 30, in a preferred example, thesource layer 60 is also formed on theinner dielectric layer 50; theactive layer 30 is epitaxially formed by the drain Theprocessing surface 11 of thelayer 10 is formed by internalization, and theinner dielectric layer 50 is recessed in theprocessing surface 11 to facilitate the combination of the ohmic contact between thesource layer 60 and theactive region 30 . With thesource layer 60 also formed on theinner dielectric layer 50, thesource layer 60 is conductively connected to theinner dielectric layer 50 across the isolation of the source extension backfins 20 to enlarge the source contact. Theinner dielectric layer 50 electrically insulates the top of thefirst gate 41 from thesource layer 60 extending thereon, and electrically insulates the top of thesecond gate 42 from thesource layer 60 extending thereon. The device structure can be thinner by reducing the deposition thickness of theinner dielectric layer 50 on the treatedsurface 11 . When theactive layer 30 is formed by internalizing the treatedsurface 11 of thedrain epitaxial layer 10, theactive layer 30 and thedrain epitaxial layer 10 are lattice-matched, and there is no interface gap. Defects, the channel structure of the transistor and thedrain epitaxial layer 10 become an integral structure, which is better than the active layer or channel layer grown by epitaxial growth in electrical performance stability; when thesource layer 60 and theactive region 30 The combination of ohmic contact between them can reduce the resistance of the two.

示例中,第一沟槽13的宽度介于0.2～3.0um,第二沟槽31的宽度介于 0.21～4.0um。而第二沟槽31的底部高度介于第二栅极42的底部高度与源极延伸倒鳍20的顶部高度之间;示例中,第二沟槽31的底部高度与第一沟槽13的底部存在高度差,第一沟槽13由处理表面11起的深度介于1.5～10um。In an example, the width of thefirst trench 13 is between 0.2 and 3.0 μm, and the width of thesecond trench 31 is between 0.21 and 4.0 μm. The bottom height of thesecond trench 31 is between the bottom height of thesecond gate 42 and the top height of the source extending backfin 20; in the example, the bottom height of thesecond trench 31 is the same as thefirst trench 13 There is a height difference at the bottom, and the depth of thefirst trench 13 from theprocessing surface 11 is between 1.5-10 μm.

关于有源层30的具体化，所述有源层30包括位于底层的沟道层32、位于所述沟道层32上且在沟槽开口两侧的源极领域结33,所述源极领域结33以斜角离子注入形成,用于连接沟槽凹陷区内的所述源极层60至对应第一栅极41与第二栅极42的两侧。利用所述有源层30中的源极领域结33,在源极层60与有源层沟道层32之间形成可开关的电子流连接，第一沟槽13与第二沟槽31的开口端能形成供所述源极层60填入的自对准凹陷区，所述源极层60能槽口角隅包覆方式通过源极领域结33导接到对应第一栅极41与第二栅极42两侧的沟道。在另一变化示例中,所述有源层30可以外延方式磊晶形成,无论是内生方式还是外延方式形成的沟道层都是单晶结构,沟道电性能稳定,但内生方式漏极外延层10内形成的沟道层具有与漏极外延层10较优的晶格匹配度。示例中,有源层30的厚度介于0.5～3um。Regarding the embodiment of theactive layer 30, theactive layer 30 includes achannel layer 32 on the bottom layer, andsource field junctions 33 on thechannel layer 32 and on both sides of the trench opening. Thefield junction 33 is formed by ion implantation at an oblique angle, and is used for connecting thesource layer 60 in the recessed area of the trench to two sides corresponding to thefirst gate 41 and thesecond gate 42 . Using thesource field junction 33 in theactive layer 30, a switchable electron flow connection is formed between thesource layer 60 and the activelayer channel layer 32, and the connection between thefirst trench 13 and thesecond trench 31 is The open end can form a self-aligned recessed area for thesource layer 60 to be filled in, and thesource layer 60 can be connected to the correspondingfirst gate 41 and thefirst gate 41 and thefirst gate 41 through thesource area junction 33 in a notch-corner cladding manner. Two channels on both sides of thegate 42 . In another variation example, theactive layer 30 may be formed by epitaxial epitaxy, and the channel layer formed by either endogenous or epitaxial method is a single crystal structure, and the electrical performance of the channel is stable, but the endogenous leakage The channel layer formed in theelectrode epitaxial layer 10 has better lattice matching with thedrain epitaxial layer 10 . In an example, the thickness of theactive layer 30 ranges from 0.5 to 3 μm.

关于有源层30的更具体化,在较佳示例中,所述有源层30还包括位于顶层的欧姆接触层34,分隔于所述源极领域结33之间且显露于所述处理表面11,所述欧姆接触层34的厚度小于所述源极领域结33的下沉深度。利用所述有源层30位于顶层的欧姆接触层34，供所述源极层60的直接结合,并有效界定所述源极领域结33在所述处理表面11上的显露区域。在N型晶体管的示例结构中,沟道层32为P-型掺杂区,源极领域结33为N+型掺杂区,欧姆接触层34为P+型掺杂区,其中就P型掺杂浓度而言,欧姆接触层34高于沟道层32;故沟道层32在栅极41,42两侧会有晶体管沟道效应,欧姆接触层34在源极层60的表面不会有晶体管沟道效应,欧姆接触层34倾向于具有导电性。而沟道层32的P型掺杂物质具体可以是硼(B),沟道层32的沟道作用产生于厚度向,而非与处理表面11相同或平行的表面向。在另一变化示例中,所述有源层30可以只包括：位于底层的沟道层32、位于所述沟道层32上的源极领域结33;欧姆接触层34的作用是与源极层60产生欧姆接触的结合,具有与沟道层32相同但是浓度较低的反型掺杂,这是为了避免沟道层32受到源极领域结33正型掺杂的影响而过度改变电性能。示例中,沟道层32的厚度介于 0.1～2um ,源极领域结33的厚度介于0.05～1um,欧姆接触层34的厚度介于 0.05 ～ 1um。Regarding a more specific embodiment of theactive layer 30, in a preferred example, theactive layer 30 further includes anohmic contact layer 34 on the top layer, separated between thesource field junctions 33 and exposed on theprocessing surface 11. The thickness of theohmic contact layer 34 is smaller than the sinking depth of thesource field junction 33. Theohmic contact layer 34 on the top layer of theactive layer 30 is used for direct bonding of thesource layer 60 and effectively defines the exposed area of thesource field junction 33 on theprocessing surface 11 . In the example structure of the N-type transistor, thechannel layer 32 is a P-type doped region, thesource field junction 33 is an N+-type doped region, and theohmic contact layer 34 is a P+-type doped region, wherein the P-type doped region is In terms of concentration, theohmic contact layer 34 is higher than thechannel layer 32; therefore, thechannel layer 32 will have a transistor channel effect on both sides of thegates 41 and 42, and theohmic contact layer 34 will not have transistors on the surface of thesource layer 60. Due to the channel effect, theohmic contact layer 34 tends to have conductivity. The P-type dopant material of thechannel layer 32 may be boron (B) specifically, and the channel effect of thechannel layer 32 is generated in the thickness direction, not in the same or parallel surface direction as theprocessing surface 11 . In another variation example, theactive layer 30 may only include: achannel layer 32 located at the bottom layer, and asource field junction 33 located on thechannel layer 32; the function of theohmic contact layer 34 is to connect with thesource electrode Layer 60 produces a combination of ohmic contacts and has the same inversion doping aschannel layer 32 but with a lower concentration, in order to avoid excessive changes in electrical properties ofchannel layer 32 due to the positive doping ofsource field junction 33 . In an example, the thickness of thechannel layer 32 is between 0.1-2 μm, the thickness of thesource field junction 33 is between 0.05-1 μm, and the thickness of theohmic contact layer 34 is between 0.05-1 μm.

关于第一沟槽13与第二沟槽31的绝缘具体化,在较佳示例中,所述第一沟槽13的底部经过厚氧化处理，所述源极延伸倒鳍20与所述衬底外延层10之间的绝缘厚度大于所述第一栅极41或/与所述第二栅极42的表面至所述衬底外延层10的栅氧厚度,即第一效应氧化层91的厚度大于第二效应氧化层92的厚度;利用源极延伸倒鳍20的绝缘厚度大于所述第一栅极41或/与所述第二栅极42的栅氧厚度，使源极延伸倒鳍20具有电子流隔离分区作用但不具有栅极的场效应开关作用。Regarding the insulation of thefirst trench 13 and thesecond trench 31, in a preferred example, the bottom of thefirst trench 13 is subjected to a thick oxidation process, and the source extends theback fin 20 and the substrate. The insulating thickness between theepitaxial layers 10 is greater than the gate oxide thickness from the surface of thefirst gate 41 or/and thesecond gate 42 to thesubstrate epitaxial layer 10 , that is, the thickness of the firsteffect oxide layer 91 Greater than the thickness of the secondeffect oxide layer 92; the insulating thickness of the source extendinginverted fin 20 is greater than the gate oxide thickness of thefirst gate 41 or/and thesecond gate 42, so that the source extends theinverted fin 20 Field effect switching with electron flow isolation and partition without gate.

关于第一沟槽13内部叠加结构的具体化,在较佳示例中,所述第二栅极42的底部与所述源极延伸倒鳍20之间形成有第一隔离氧化层81,所述第二栅极42的顶部与所述源极层60之间形成有第二隔离氧化层82,以增加埋入式栅极与源极的隔离厚度,所述第二隔离氧化层82还形成并覆盖于所述第一栅极41的顶部。优选配合第二栅极42的底部与顶部形成的第一隔离氧化81层与第二隔离氧化层82，第二栅极42的栅极场效应只作用于第二栅极42的两侧,叠加态的源极延伸倒鳍20与第二栅极42之前产生效应隔离作用。Regarding the embodiment of the superimposed structure inside thefirst trench 13, in a preferred example, a firstisolation oxide layer 81 is formed between the bottom of thesecond gate 42 and thesource extension fin 20, and the A secondisolation oxide layer 82 is formed between the top of thesecond gate 42 and thesource layer 60 to increase the isolation thickness between the buried gate and the source, and the secondisolation oxide layer 82 is also formed and covering the top of thefirst gate 41 . It is preferable to cooperate with the firstisolation oxide layer 81 and the secondisolation oxide layer 82 formed at the bottom and top of thesecond gate 42, and the gate field effect of thesecond gate 42 only acts on both sides of thesecond gate 42, superimposed The source of the state extends theinverted fin 20 and thesecond gate 42 before effect isolation.

关于漏极外延层10内部结构的一种具体化，在较佳示例中,所述漏极外延层10在对应所述第一沟槽13底部的部位还形成有深植入区，以形成屏蔽栅底部浮空反极型柱底结70。屏蔽栅底部浮空反极型柱底结70由所述源极延伸倒鳍20的底部透出,以增加浮空反极型柱对临近的极型柱的电荷平衡,避免不同区所述源极延伸倒鳍20之间的电子流提早汇集,在制作上可以减少所述第一沟槽13的深度,底部绝缘层厚度也能减少,也有利于所述源极延伸倒鳍20的填充形成。示例中，反极型柱底结70为P型掺杂;反极型柱底结70是作用于提高源极延伸倒鳍20的分流隔离作用,防止电子流在漏极外延层10内提早汇集;故相同性能下第一沟槽13的槽深度可以减少,降低源极延伸倒鳍20填槽的填充难度。示例中，反极型柱底结70的底部深度不超过所述漏极外延层10的厚度，使所述漏极外延层10在所述第一沟槽13之间不被所述反极型柱底结70完全阻隔，反极型参杂物质不会进入漏极衬底1，在制造工艺中保持图中参杂浓度清晰变化水平面17的存在，使竖立沟道式场效晶体管具有较好的产品稳定性。Regarding an embodiment of the internal structure of thedrain epitaxial layer 10, in a preferred example, thedrain epitaxial layer 10 is further formed with a deep implantation region at a portion corresponding to the bottom of thefirst trench 13 to form a shield The bottom of the gate floats an inversion-type post-bottom junction 70 . Thebottom junction 70 of the floating inversion column at the bottom of the shielded gate is exposed from the bottom of the source extendinginverted fin 20, so as to increase the charge balance of the floating inversion column to the adjacent column, and avoid the source in different regions. The electron current between the pole-extendinginverted fins 20 is collected in advance, the depth of thefirst trench 13 can be reduced, and the thickness of the bottom insulating layer can also be reduced, which is also conducive to the filling and formation of the source-extendinginverted fins 20 . In the example, the reversepole bottom junction 70 is P-type doped; the reverse polepole bottom junction 70 is used to improve the shunting and isolation effect of the source extension backfin 20 to prevent the electron flow from condensing in thedrain epitaxial layer 10 in advance. Therefore, under the same performance, the groove depth of thefirst trench 13 can be reduced, and the filling difficulty of the source extension backfin 20 can be reduced. In the example, the depth of the bottom of the reversepole bottom junction 70 does not exceed the thickness of thedrain epitaxial layer 10 , so that thedrain epitaxial layer 10 is not affected by the reverse pole type between thefirst trenches 13 . Thecolumn bottom junction 70 is completely blocked, and the inverse type impurity substance will not enter the drain substrate 1. During the manufacturing process, the existence of thelevel surface 17 in the figure with a clear change in the impurity concentration is maintained, so that the vertical channel field effect transistor has better performance. product stability.

参阅图21，在较佳示例的使用过程,以所述第一栅极41与第二栅极42等电位连接下的电场效应，来自所述源极层60的电子流在所述处理表面11上分流沿着所述第二沟槽31与所述第一沟槽13上半部的侧壁轮廓的对称侧移动到所述第一沟槽13下半部之间的所述漏极衬底1，均匀在所述漏极衬底1的所述背面12或设置于该背面12的漏极金属垫16，实现电子流由顶面至底面的在所述漏极外延层10的所述第一沟槽13之间的分区均匀化。Referring to FIG. 21, in the use process of the preferred example, with the electric field effect under the equipotential connection of thefirst gate 41 and thesecond gate 42, the electrons from thesource layer 60 flow on the treatedsurface 11 The upper shunt moves along the symmetrical sides of the sidewall profiles of thesecond trench 31 and the upper half of thefirst trench 13 to the drain substrate between the lower half of thefirst trench 13 1. Evenly on theback surface 12 of the drain substrate 1 or thedrain metal pad 16 disposed on theback surface 12 to realize the electron flow from the top surface to the bottom surface on the first surface of the drain epitaxial layer 10 A division betweentrenches 13 is uniform.

此外，配合参阅图2至图20,本发明另一些实施例提出一种多栅极变化的场效晶体管结构的制造方法，用于制造上述任意技术方案组合的场效晶体管结构,工艺步骤S2至S20采用与附图标号相同对应的方式以方便理解并说明如后。In addition, referring to FIG. 2 to FIG. 20 , other embodiments of the present invention provide a method for manufacturing a field effect transistor structure with multi-gate variation, which is used to manufacture a field effect transistor structure combined with any of the above technical solutions. Process steps S2 to S20 adopts the same corresponding manner as the reference numerals to facilitate understanding and to be described as follows.

首先参照图2，对应步骤S2是提供漏极衬底1，具有由漏极外延层10提供的处理表面11与对应的背面12;该步骤中，漏极衬底1通常为晶圆形态,具体是硅晶圆。漏极外延层10的处理表面11上形成有一表面酸化膜14,具有硬掩膜的作用，以利后工艺中第一沟槽13的形成。示例中,具有漏极外延层10的漏极衬底1具体是EPI晶圆(Epitaxy wafer),基于半导体生产链的分工,EPI漏极衬底1是能直接购买而得,漏极衬底1的基础层具体是硅衬底,即图2中的主体区15,主体区15以上至处理表面11是外延生长的磊晶结构,即漏极外延层10,使得漏极外延层10作为处理表面11与背面12之间的外延结构部位具有功能性导电并具备如硅衬底晶圆一样的单晶结构与晶向,而主体区15为半导体材质的导电性。在N型场效晶体管结构中,主体区15具体是N+单晶硅,漏极外延层10具体是N-单晶硅,所述漏极外延层10的具体如N型的正向型特性是外延生长时即加入正向型物质生长形成。主体区15与漏极外延层10之间形成一个参杂浓度清晰变化水平面17,与处理表面11平行向,以利于保持竖立向沟道的产率与良率。此外,所述表面酸化膜14具体可以是表面淀积掩蔽膜层,其材质可以是但不限于SIO₂或SIN,其厚度介于1000A～8000A,表面酸化膜14的一种具体制造方法可以是先生长200A～1000A热氧厚度层,然后淀积厚度不大于7000A的叠加膜层;当热氧厚度层的厚度足够(至少大于1000A),叠加膜层的淀积可以不实施,使所述表面酸化膜14具有挖设第一沟槽的掩膜作用。Referring first to FIG. 2, the corresponding step S2 is to provide a drain substrate 1, which has a processedsurface 11 provided by thedrain epitaxial layer 10 and acorresponding back surface 12; in this step, the drain substrate 1 is usually in the form of a wafer, specifically is a silicon wafer. Asurface acidification film 14 is formed on the treatedsurface 11 of thedrain epitaxial layer 10, and has the function of a hard mask, so as to facilitate the formation of thefirst trench 13 in the subsequent process. In the example, the drain substrate 1 having thedrain epitaxial layer 10 is specifically an EPI wafer (Epitaxy wafer). Based on the division of labor in the semiconductor production chain, the EPI drain substrate 1 can be directly purchased, and the drain substrate 1 The base layer is specifically a silicon substrate, that is, thebody region 15 in FIG. 2 , and the epitaxial structure above thebody region 15 to thetreatment surface 11 is the epitaxial structure of epitaxial growth, that is, thedrain epitaxial layer 10, so that thedrain epitaxial layer 10 is used as the treatment surface. The epitaxial structure part between 11 and theback surface 12 has functional conductivity and has the same single crystal structure and crystal orientation as a silicon substrate wafer, and themain body region 15 is conductive of semiconductor material. In the N-type field effect transistor structure, thebody region 15 is specifically N+ single crystal silicon, and thedrain epitaxial layer 10 is specifically N- single crystal silicon. The specific characteristics of thedrain epitaxial layer 10, such as the N-type forward type, are: It is formed by adding forward-type material during epitaxial growth. Between themain body region 15 and thedrain epitaxial layer 10 is formed alevel surface 17 with a clearly variable dopant concentration, parallel to theprocessing surface 11, so as to maintain the productivity and yield of the vertical channel. In addition, thesurface acidifying film 14 can be specifically a surface deposition masking film, and its material can be but not limited to SIO₂ or SIN, and its thickness is between 1000A～8000A, and a specific manufacturing method of thesurface acidizing film 14 can be: First grow the thermal oxygen thickness layer of 200A~1000A, and then deposit the superimposed film layer with a thickness of not more than 7000A; when the thickness of the thermal oxygen thickness layer is sufficient (at least greater than 1000A), the deposition of the superimposed film layer may not be implemented, so that the surface The acidifiedfilm 14 has a mask function for digging the first trench.

图3至图20的后续工艺至晶背研磨之前都具有主体区15,但图中是省略表现,主体区15的存在是维持衬底作为制程载体的基础物理结构,晶背研磨之后主体区15的厚度大幅减少,但不损及所述漏极外延层10,芯片产品中减薄后的主体区15可以保留也可以不保留。根据器件阻断电压和器件参数要求选择合适的上述外延结构，该外延结构是N型但不限于N型，晶向<100>但不限于此晶向。The subsequent processes in FIGS. 3 to 20 have themain body region 15 before back grinding, but the figures are omitted. The existence of themain body region 15 is to maintain the basic physical structure of the substrate as a process carrier. After the back grinding, themain body region 15 The thickness of the chip is greatly reduced, but thedrain epitaxial layer 10 is not damaged, and the thinnedbody region 15 in the chip product may or may not be retained. Select the appropriate epitaxial structure according to the device blocking voltage and device parameter requirements, the epitaxial structure is N-type but not limited to N-type, and crystal orientation <100> but not limited to this crystal orientation.

参照图3，对应步骤S3是由所述处理表面11刻蚀形成相互平行的第一沟槽13,第一沟槽13形成后移除表面酸化膜14。以光刻与刻蚀方式选定区域掩蔽膜的图案,屏蔽体场板沟槽刻蚀，根据器件的特性不同，由处理表面11往内计算，第一沟槽13刻蚀深度具体介于1.0～10um。在第一沟槽13的形成过程,表面酸化膜14有可能被部分消耗。3, corresponding to step S3,first trenches 13 parallel to each other are formed by etching theprocessing surface 11, and thesurface acidizing film 14 is removed after thefirst trenches 13 are formed. The pattern of the masking film in the region is selected by photolithography and etching, and the trenches of the shielding body field plate are etched. According to the characteristics of the device, calculated from thetreatment surface 11 inward, the etching depth of thefirst trench 13 is specifically 1.0 ~10um. During the formation of thefirst trench 13, thesurface acidizing film 14 may be partially consumed.

参照图4，作为一个选置步骤S4，在提供所述漏极衬底1与形成第一沟槽13的步骤后,还包括：以离子植入方式在所述漏极外延层10在对应所述第一沟槽13底部的部位形成屏蔽栅底部浮空反极型柱底结70。S4具体示例的次步骤包括：S41、注入屏蔽栅底部浮空反极型柱底结70之前,先将掩蔽氧化层生长，生长厚度200～800A;S42、P柱注入，注入B11可包括含有多次注入，注入能量20k-2Mev，注入剂量10¹¹～ 10¹⁴ ions/cm²，以形成如图4所示的屏蔽栅底部浮空反极型柱底结70，柱底结的深度长0.2～5um;S43、形成牺牲氧化层，氧化温度700～1100℃，厚度300～1000A;S44、以选择性干刻蚀方式去掉牺牲氧化层;S45、清洗所述漏极外延层10。以上步骤是用于形成反极型柱底结70并将第一沟槽13清洁化，避免注入参杂物对第一沟槽13绝缘处理的不利影响，并有利于后续形成第一效应氧化层91的厚度一致化。或者/以及，在屏蔽栅底部浮空反极型柱底结70形成后,才完全去除表面酸化膜14,表面酸化膜14除了具有形成第一沟槽13的掩膜作用,优选还具有浮空反极型柱底结70图案形成的遮挡作用。4, as an optional step S4, after the step of providing the drain substrate 1 and forming thefirst trench 13, it further includes: ion implantation in thedrain epitaxial layer 10 in a corresponding place The bottom portion of thefirst trench 13 forms a floating inversion pillarbottom junction 70 at the bottom of the shield gate. The sub-steps of the specific example of S4 include: S41, before implanting the floating inversioncolumn bottom junction 70 at the bottom of the shielding gate, firstly grow the masking oxide layer, and the growth thickness is 200-800A; The second implantation, the implantation energy is 20k-2Mev, and the implantation dose is 10¹¹ ～ 10¹⁴ ions/cm² to form the floatinginversion post-bottom junction 70 at the bottom of the shielded gate as shown in FIG. 4 , and the depth of the post-bottom junction is 0.2～ 5um; S43, forming a sacrificial oxide layer with an oxidation temperature of 700-1100°C and a thickness of 300-1000A; S44, removing the sacrificial oxide layer by selective dry etching; S45, cleaning thedrain epitaxial layer 10. The above steps are used to form the reversepole bottom junction 70 and clean thefirst trench 13, so as to avoid the adverse effect of implantation of impurities on the insulation treatment of thefirst trench 13, and to facilitate the subsequent formation of the first effect oxide layer The thickness of 91 is uniform. Or/and, after the floating inversioncolumn bottom junction 70 at the bottom of the shielded gate is formed, thesurface acidizing film 14 is completely removed, and thesurface acidizing film 14 not only has a mask function for forming thefirst trench 13, but also has a floating function. The shielding effect formed by the pattern of the reversepole bottom junction 70 .

参照图5，对应步骤S5是在所述处理表面11与所述第一沟槽13内形成第一效应氧化层91，使所述第一沟槽13的内壁绝缘处理。第一效应氧化层91具体是热氧化层或/与淀积氧化层，但不限于此两种，氧化层厚度根据器件参数要求可以介于500～13000A。第一效应氧化层91的隔离作用是隔离反向于沟道的较弱场效应,不需要薄至栅氧厚度,通常第一效应氧化层91的隔离厚度通常大于第二效应氧化层92的栅氧厚度(如图11所示)。S5具体示例但不限于的次步骤包括：S51、形成厚度在200～7000A的热氧化层;S52、若热氧化层的厚度未达到第一效应氧化层91的目标厚度值,则再淀积厚度在100～12000A的淀积氧化层。Referring to FIG. 5 , corresponding to step S5 , a firsteffect oxide layer 91 is formed on the treatedsurface 11 and thefirst trench 13 , and the inner wall of thefirst trench 13 is insulated. The firsteffect oxide layer 91 is specifically a thermal oxide layer or/and a deposition oxide layer, but is not limited to these two types, and the thickness of the oxide layer may range from 500 to 13000A according to device parameter requirements. The isolation function of the firsteffect oxide layer 91 is to isolate the weaker field effect opposite to the channel, and it does not need to be as thin as the gate oxide thickness. Usually, the isolation thickness of the firsteffect oxide layer 91 is usually larger than the gate oxide thickness of the secondeffect oxide layer 92. Oxygen thickness (as shown in Figure 11). Specific examples of but not limited to sub-steps of S5 include: S51, forming a thermal oxide layer with a thickness of 200-7000A; S52, if the thickness of the thermal oxide layer does not reach the target thickness value of the firsteffect oxide layer 91, then deposit the thickness again Deposit oxide layer at 100~12000A.

参照图6与图7，以沉淀填充方式在所述第一沟槽13内设置源极延伸倒鳍20，所述第一沟槽13的深度不超过所述漏极外延层10的厚度，并去除所述源极延伸倒鳍20与所述第一效应氧化层91在所述处理表面11上的部位。图6对应步骤S6是源极延伸倒鳍20的大面积形成,图7对应步骤S7是源极延伸倒鳍20的形状修整。步骤S6的一种示例但不限于的工艺条件包括：S61、以例如LPCVD(低压力化学气相沉积法)方式多晶硅(Poly)淀积于所述第一沟槽13内并形成于处理表面11上,多晶硅在处理表面11上的厚度介于1000～15000A;S62、in-stu掺杂(In-situ doping,原位掺杂)方式或注入掺杂物(implant doping)方式，致使多晶硅具有导电性，掺杂浓度介于10¹⁸～ 10²¹ ions/cm³，掺杂类型示例是N型,但也可以是P型。多晶硅能填满所述第一沟槽13，浮空反极型柱底结70的优选导入能在相同隔离栅作用下缩短第一沟槽13的深度,也有利于多晶硅的填满。多晶硅在第一沟槽13底部的部分即构成所述源极延伸倒鳍20。Referring to FIGS. 6 and 7 , thesource extension fins 20 are disposed in thefirst trenches 13 by means of precipitation filling, the depth of thefirst trenches 13 does not exceed the thickness of thedrain epitaxial layer 10 , and The portion of the source extension backfin 20 and the firsteffect oxide layer 91 on theprocessing surface 11 is removed. FIG. 6 corresponds to step S6 of forming a large area of the source extended backfin 20 , and FIG. 7 corresponds to step S7 of shape trimming of the source extended backfin 20 . An example but not limited process condition of step S6 includes: S61, polysilicon (Poly) is deposited in thefirst trench 13 by, for example, LPCVD (low pressure chemical vapor deposition) and formed on theprocessing surface 11 , the thickness of polysilicon on theprocessing surface 11 is between 1000-15000A; S62, in-stu doping (In-situ doping, in-situ doping) method or implant doping (implant doping) method, resulting in polysilicon with conductivity , the doping concentration is between 10¹⁸ and 10²¹ ions/cm³ , and an example of the doping type is N-type, but it can also be P-type. The polysilicon can fill thefirst trench 13, and the preferred introduction of the floating inversioncolumn bottom junction 70 can shorten the depth of thefirst trench 13 under the same isolation gate effect, which is also beneficial to the filling of the polysilicon. The portion of the polysilicon at the bottom of thefirst trench 13 constitutes thesource extension fin 20 .

参照图7，作为一个衔接步骤S6的后续步骤S7，在设置所述源极延伸倒鳍20的步骤中,所述源极延伸倒鳍20与所述第一效应氧化层91在所述处理表面11上的部位予以去除,去除方法包括化学机械研磨(CMP)与回刻蚀(etch back);优选的,所述源极延伸倒鳍20的材质包括导电多晶硅。虽然源极延伸倒鳍20的基础材质与漏极外延层10的基础材质相同,但是两者之间图6结构中间隔了第一效应氧化层91,在不破坏漏极外延层10的情况下能够以选择刻蚀方式分别对源极延伸倒鳍20与第一效应氧化层91进行图案化处理。S7处理后,对应槽深方向,所述源极延伸倒鳍20的纵向长度可介于0.3～10um,所述第一效应氧化层91的顶端高度可高于、等于或低于所述源极延伸倒鳍20的顶端高度,优选是高于,使源极延伸倒鳍20两侧受到第一效应氧化层91较为完整的侧边隔离保护。不同示例中,也能等于或低于,这是因为使用了第一隔离氧化层81覆盖源极延伸倒鳍20的顶面且侧边连接第一效应氧化层91(如图12所示),故对于所述第一效应氧化层91的顶端高度相对于所述源极延伸倒鳍20的顶端高度的高度差没有限制。而且,利用所述第一效应氧化层91的顶端高度相对于所述源极延伸倒鳍20的顶端高度的高度差调整,能改变第二栅极42的底部形状。7, as a subsequent step S7 following step S6, in the step of disposing the source extension backfin 20, the source extension backfin 20 and the firsteffect oxide layer 91 are on the processing surface The parts on 11 are removed, and the removal method includes chemical mechanical polishing (CMP) and etch back (etch back); preferably, the material of the source extension backfin 20 includes conductive polysilicon. Although the base material of the source extension invertedfin 20 is the same as the base material of thedrain epitaxial layer 10 , the firsteffect oxide layer 91 is spaced between the two in the structure of FIG. 6 , without damaging thedrain epitaxial layer 10 . The source extension backfin 20 and the firsteffect oxide layer 91 can be patterned respectively by selective etching. After the S7 process, corresponding to the groove depth direction, the longitudinal length of the source extending backfin 20 can be between 0.3-10um, and the top height of the firsteffect oxide layer 91 can be higher than, equal to or lower than the source electrode The height of the top of the extendedinverted fin 20 is preferably higher than that, so that the two sides of the source extendedinverted fin 20 are protected by relatively complete side isolation of the firsteffect oxide layer 91 . In different examples, it can also be equal to or lower than that because the firstisolation oxide layer 81 is used to cover the top surface of thesource extension fin 20 and the side is connected to the first effect oxide layer 91 (as shown in FIG. 12 ), Therefore, there is no limit to the height difference between the top height of the firsteffect oxide layer 91 and the top height of the source extending backfin 20 . Moreover, the bottom shape of thesecond gate 42 can be changed by adjusting the height difference between the top of the firsteffect oxide layer 91 and the top of the source extending backfin 20 .

参照图8，作为一个在形成第二沟槽31的步骤中,包括的前置步骤S8是：形成第一硬掩膜层81A在所述处理表面11上,以遮盖所述处理表面11以及所述源极延伸倒鳍20的顶部。第一硬掩膜层81A作为表面淀积掩蔽膜层,材质具体是但不限于氧化硅(SIO₂)，厚度介于1000A～8000A。第一硬掩膜层81A的优选形成方法是高密度等离子化学气相淀积法（HDP-CVD）,使第一硬掩膜层81A能填满第一沟槽13内的剩余空间。8 , as a step of forming thesecond trench 31, the pre-step S8 included is: forming a firsthard mask layer 81A on theprocessing surface 11 to cover theprocessing surface 11 and all The source electrode extends to the top of theinverted fin 20 . The firsthard mask layer 81A is used as a surface-deposited mask layer, and the material is specifically, but not limited to, silicon oxide (SIO₂ ), and the thickness ranges from 1000A to 8000A. A preferred method for forming the firsthard mask layer 81A is high-density plasma chemical vapor deposition (HDP-CVD), so that the firsthard mask layer 81A can fill the remaining space in thefirst trench 13 .

参照图9，对应步骤S9是利用所述第一硬掩膜层81A的图案化由所述处理表面11刻蚀形成位于所述第一沟槽13之间的第二沟槽31，所述第二沟槽31的第二深度小于所述第一沟槽13的第一深度，第二沟槽31的第二深度具体介于0.3～2um，第二沟槽31在两个相邻所述第一沟槽13之间的数量可以是一个或多个,当只有一个,第二沟槽31位于所述第一沟槽13之间的中间部位。在本步骤S9中包括:S91,可先通过光刻定义第二沟槽31的反向图形;S92，刻蚀第一硬掩膜层81A以形成第二沟槽刻蚀区;S93，去掉光刻胶，然后在第一硬掩膜层81A遮挡下刻蚀形成第二沟槽31。此外,第二沟槽31的第二深度相比于所述第一沟槽13内剩余空间的深度(相当于第一深度减去源极延伸倒鳍20与第一效应氧化层91的厚度值和)可以是相同但不限于相同,不同变化例中,第二沟槽31可以较深也可以较浅。优选示例中,为了保持后续形成的第一栅极41与第二栅极42在相同高度水平,第二沟槽31的第二深度与所述第一硬掩膜层81A在第一沟槽13的剩余厚度(即第一隔离氧化层81的厚度)可以相互对应调整。Referring to FIG. 9 , the corresponding step S9 is to use the patterning of the firsthard mask layer 81A to etch from theprocessing surface 11 to formsecond trenches 31 between thefirst trenches 13 . The second depth of the twotrenches 31 is smaller than the first depth of thefirst trench 13 , and the second depth of thesecond trench 31 is specifically 0.3˜2 μm. The number ofgrooves 13 can be one or more, and when there is only one groove, thesecond groove 31 is located in the middle part between thefirst grooves 13 . In this step S9, include: S91, can first define the reverse pattern of thesecond trench 31 by photolithography; S92, etch the firsthard mask layer 81A to form the second trench etching region; S93, remove the light Then, thesecond trench 31 is formed by etching under the shielding of the firsthard mask layer 81A. In addition, the second depth of thesecond trench 31 is compared with the depth of the remaining space in the first trench 13 (equivalent to the first depth minus the thickness of the source extension backfin 20 and the first effect oxide layer 91 ) and ) may be the same but not limited to the same, and in different variations, thesecond trench 31 may be deeper or shallower. In a preferred example, in order to keep the subsequently formedfirst gate 41 and thesecond gate 42 at the same height level, the second depth of thesecond trench 31 is the same as that of the firsthard mask layer 81A in thefirst trench 13 The remaining thickness of , (ie, the thickness of the first isolation oxide layer 81 ) can be adjusted corresponding to each other.

参照图10，对应步骤S10是选置步骤,作为形成所述第二沟槽31的步骤后的后置步骤,具体是刻蚀处理表面11上的第一硬掩膜层81A形成为源极延伸倒鳍20上的第一隔离氧化层81。再参照图10，可利用氧化物刻蚀方式使第一沟槽13内的第一硬掩膜层81A也大部分被去除，被保留在第一沟槽13内的第一硬掩膜层81A作为第一隔离氧化层81，第一隔离氧化层81的厚度具体介于500A～8000A;在第一隔离氧化层81成形后,将漏极衬底1经过湿 式工艺的清洗,以清除表面的氧化物残渣,通常使用的清洗液是氟化氢的水溶液(HF:H₂O=1：50),最后以去离子水清洗并甩干。Referring to FIG. 10 , the corresponding step S10 is a selection step, which is a post-step after the step of forming thesecond trench 31 , specifically, the firsthard mask layer 81A on the etchedsurface 11 is formed as a source extension The firstisolation oxide layer 81 on theinverted fin 20 . Referring to FIG. 10 again, most of the firsthard mask layer 81A in thefirst trench 13 can be removed by oxide etching, and the firsthard mask layer 81A in thefirst trench 13 is retained. As the firstisolation oxide layer 81, the thickness of the firstisolation oxide layer 81 is specifically between 500A and 8000A; after the firstisolation oxide layer 81 is formed, the drain substrate 1 is cleaned by a wet process to remove surface oxidation To remove the residue, the commonly used cleaning solution is an aqueous solution of hydrogen fluoride (HF:H₂ O=1:50), and finally washed with deionized water and dried.

参照图11，对应步骤S11是在所述处理表面11上、所述第二沟槽31内与所述第一沟槽13的剩余空间内形成第二效应氧化层92，使所述第二沟槽31的内壁与所述第一沟槽13剩余空间的内壁绝缘处理。在形成所述第二效应氧化层92的步骤中,所述第二效应氧化层92具体为栅氧化层,以热氧化或热氧化加上淀积方式形成所述栅氧化层于所述第二沟槽31的内壁、所述第一沟槽13剩余空间的内壁与所述处理表面11上;栅氧化层的氧化温度700～1100℃，第二效应氧化层92的厚度介于200～1500A。Referring to FIG. 11 , corresponding to step S11 , a secondeffect oxide layer 92 is formed on theprocessing surface 11 , in thesecond trench 31 and in the remaining space of thefirst trench 13 , so that the second trench is formed. The inner wall of thegroove 31 is insulated from the inner wall of the remaining space of thefirst trench 13 . In the step of forming the secondeffect oxide layer 92, the secondeffect oxide layer 92 is specifically a gate oxide layer, and the gate oxide layer is formed on the second effect oxide layer by thermal oxidation or thermal oxidation plus deposition. The inner wall of thetrench 31, the inner wall of the remaining space of thefirst trench 13 and theprocessing surface 11; the oxidation temperature of the gate oxide layer is 700-1100°C, and the thickness of the secondeffect oxide layer 92 is 200-1500A.

参照图12，对应步骤S12是以沉淀填充方式在所述第二沟槽31内设置第一栅极41以及在所述第一沟槽13剩余空间内设置第二栅极42，所述第二栅极42位于所述源极延伸倒鳍20上;所述第二栅极42与所述第一栅极41具有不同的形状轮廓，所述的不同形状轮廓包括所述第二栅极42与所述第一栅极41的底部形状不同、宽度不相同的至少一种。步骤S12中，第一栅极41与第二栅极42一体相接在处理表面11上。优选的,所述第一栅极41与第二栅极42的材质包括导电多晶硅,含有掺杂离子。步骤S12的一种示例但不限于的工艺条件包括：S121、以LPCVD方式将多晶硅(Poly)淀积于所述第二沟槽31与第一沟槽13的剩余空间内并形成于处理表面11上;S122、in-stu方式掺杂或/和注入掺杂物，足以使多晶硅具有导电性，掺杂浓度介于10¹⁸～ 10²¹ ions/cm³,厚度介于1000～15000A。根据半导体器件的类型掺杂物可以为N型或P型，如果是P型多晶硅通常通过注入进行掺杂。Referring to FIG. 12 , corresponding to step S12 , afirst gate electrode 41 is provided in thesecond trench 31 by a precipitation filling method, and asecond gate electrode 42 is provided in the remaining space of thefirst trench 13 . Thegate 42 is located on the source extendinginverted fin 20; thesecond gate 42 and thefirst gate 41 have different shape profiles, and the different shape profiles include thesecond gate 42 and thefirst gate 41. At least one of the bottom shape and width of thefirst gate 41 is different. In step S12 , thefirst grid electrode 41 and thesecond grid electrode 42 are integrally connected to theprocessing surface 11 . Preferably, the material of thefirst gate 41 and thesecond gate 42 includes conductive polysilicon and contains dopant ions. An example but not limited process condition of step S12 includes: S121 , polysilicon (Poly) is deposited in the remaining space of thesecond trench 31 and thefirst trench 13 by LPCVD and formed on theprocessing surface 11 On; S122, in-stu doping or/and implanting dopants are sufficient to make the polysilicon conductive, the doping concentration is between 10¹⁸ and 10²¹ ions/cm³ , and the thickness is between 1000 and 15000A. The dopant can be N-type or P-type depending on the type of semiconductor device, and if it is P-type polysilicon is usually doped by implantation.

参照图13，对应步骤S13是去除所述第一栅极41与第二栅极42在所述处理表面11上的相接部位,去除方法包括选择性刻蚀或是化学机械研磨与回刻蚀,使所述第一栅极41与第二栅极42的顶面凹陷于所述处理表面11。步骤S13的一种示例但不限于的工艺条件包括：S131、进行多晶硅刻蚀,使得第一沟槽13与第二沟槽31的槽内刻蚀深度介于0.1～1.5um，凹陷区的深度小于第二沟槽31的第二深度。具体的,所述第一栅极41的顶面与第二栅极42的顶面凹陷于所述处理表面11的深度为一致。13, the corresponding step S13 is to remove the contact portion of thefirst gate 41 and thesecond gate 42 on theprocessing surface 11, and the removal method includes selective etching or chemical mechanical polishing and etch back , so that the top surfaces of thefirst gate 41 and thesecond gate 42 are recessed in theprocessing surface 11 . An example but not limited process condition of step S13 includes: S131, performing polysilicon etching, so that the etching depth in thefirst trench 13 and thesecond trench 31 is between 0.1-1.5um, and the depth of the recessed region is less than the second depth of thesecond trench 31 . Specifically, the top surface of thefirst gate 41 and the top surface of thesecond gate 42 are recessed to the same depth in theprocessing surface 11 .

参照图14，对应步骤S14是在所述漏极外延层10的所述处理表面11下以反型能量注入方式形成有源层30，所述有源层30的厚度与深度在所述第二沟槽31的第二深度与所述第一沟槽13剩余空间能贯穿的范围内。在形成所述有源层30的步骤中,所述有源层30由所述漏极外延层10的所述处理表面11内化形成;所述有源层30主要包括作为底层主结构的沟道层32。步骤S14的一种示例但不限于的工艺条件是：S141、由处理表面11注入B11等P型掺杂物,可含多次注入,以形成P-body区，注入能量20～800kev，注入剂量10¹²～10¹⁴ ions/cm²，以形成有源层30。Referring to FIG. 14 , corresponding to step S14 , anactive layer 30 is formed under thetreatment surface 11 of thedrain epitaxial layer 10 by an inversion energy implantation method, and the thickness and depth of theactive layer 30 are the same as those of the second The second depth of thetrench 31 is within the range that the remaining space of thefirst trench 13 can penetrate. In the step of forming theactive layer 30, theactive layer 30 is formed by internalization of the treatedsurface 11 of thedrain epitaxial layer 10; theactive layer 30 mainly includes trenches as an underlying mainstructure Road layer 32. An example but not limited process condition of step S14 is: S141, implanting P-type dopants such as B11 from theprocessing surface 11, which may include multiple implants to form a P-body region, the implantation energy is 20-800kev, and theimplantation dose 10¹² to 10¹⁴ ions/cm² to form theactive layer 30 .

参照图15，作为一个选置步骤S15，先在所述第一栅极41、所述第二栅极42上与所述处理表面11上形成第二硬掩膜沉淀,具体是HDP-CVD方式淀积形成的氧化层;在淀积的同时进行斜角刻蚀,刻蚀角度约为10～80度,所述第二硬掩膜沉淀工艺自然形成为在所述第一栅极41与所述第二栅极42上的第二隔离氧化层82以及在所述处理表面11上的自对准掩膜体82B。所述自对准掩膜体82B具有两侧斜边,所述自对准掩膜体82B与邻近的所述第二隔离氧化层82之间产生供离子注入的空隙,该空隙位于所述第一沟槽13与所述第二沟槽31两侧开口边缘。在本示例的步骤S15中,所述第二隔离氧化层82的厚度介于200～5000A,所述自对准掩膜体82B由处理表面11上凸起的切面形状约为三角形,该空隙处的所述第二效应氧化层92的厚度也被减薄到小于1500A,以利于沟槽开口两侧的正型注入。更具体的,所述第二效应氧化层92在该空隙处的部位被淀积的同时进行的斜角刻蚀所移除。Referring to FIG. 15 , as an optional step S15 , firstly, a second hard mask deposit is formed on thefirst gate 41 , thesecond gate 42 and theprocessing surface 11 , specifically by HDP-CVD method The oxide layer formed by deposition; bevel etching is performed at the same time of deposition, and the etching angle is about 10 to 80 degrees, and the second hard mask deposition process is naturally formed in thefirst gate 41 and all The secondisolation oxide layer 82 on thesecond gate 42 and the self-alignedmask body 82B on theprocessing surface 11 are formed. The self-alignedmask body 82B has two oblique edges, and a gap for ion implantation is formed between the self-alignedmask body 82B and the adjacent secondisolation oxide layer 82, and the gap is located in the secondisolation oxide layer 82. Agroove 13 and the opening edges on both sides of thesecond groove 31 . In step S15 of this example, the thickness of the secondisolation oxide layer 82 is between 200 and 5000 Å, and the shape of the raised cut surface of the self-alignedmask body 82B from theprocessing surface 11 is approximately a triangle. The thickness of the secondeffect oxide layer 92 is also reduced to less than 1500 Å to facilitate positive implantation on both sides of the trench opening. More specifically, the portion of the secondeffect oxide layer 92 at the void is removed by bevel etching performed at the same time as the deposition.

参照图16，作为一个选置步骤S16，在有源层30中进行正极型注入,以形成有源层30中的源极领域结33，在位于所述处理表面11上的自对准掩膜体82B的遮挡下斜角离子注入用于形成源极领域结33的掺杂物。源极领域结33位于所述沟道层32上且在第一沟槽13与第二沟槽31的开口两侧。所述斜角离子注入为正型注入,例如示例的N+注入,注入掺杂物具体为砷(As)或磷(P)等VA族元素,可包括多次注入,源极领域结33具体为有斜边朝向沟槽内部逐渐收敛的N+型源极层,源极领域结33收敛底部的深度应下沉深入到超过所述第一栅极41的顶部与第二栅极42的顶部。步骤S16的注入能量20～100kev，注入角度5～85°，注入剂量10¹⁴～10¹⁶ ions/cm²。在自对准掩膜体82B的遮挡下，第一沟槽13与第二沟槽31开口侧的两相邻源极领域结33不会相接,这两相邻源极领域结33之间有一个位于自对准掩膜体82B下的分隔区。Referring to FIG. 16, as an optional step S16, a positive type implant is performed in theactive layer 30 to form asource field junction 33 in theactive layer 30, and a self-aligned mask located on theprocessing surface 11 Oblique ion implantation of dopants used to formsource field junction 33 is performed under the shading ofbody 82B. Thesource field junction 33 is located on thechannel layer 32 and on both sides of the openings of thefirst trench 13 and thesecond trench 31 . The oblique-angle ion implantation is a positive type implantation, such as an example N+ implantation, and the implanted dopant is specifically a group VA element such as arsenic (As) or phosphorus (P), which may include multiple implantations, and thesource region junction 33 is specifically: There is an N+ type source layer with a beveled edge gradually converging toward the inside of the trench, and the depth of the convergent bottom of thesource field junction 33 should sink deeper than the top of thefirst gate 41 and the top of thesecond gate 42 . In step S16, the implantation energy is^20-100kev , the implantation angle is 5-85°, and the implantation dose is^1014-1016 ions/^cm2 . Under the shielding of the self-alignedmask body 82B, the two adjacentsource field junctions 33 on the opening sides of thefirst trench 13 and thesecond trench 31 will not be in contact, and between the two adjacentsource field junctions 33 There is a separation area under the self-alignedmask body 82B.

参照图17，步骤S17包括以沉淀覆盖方式在所述第一栅极41与所述第二栅极42上形成内介电层50,使所述第一栅极41与所述第二栅极42为嵌埋结构。步骤S17中,内介电层50还沉淀覆盖方式在所述有源层30上,并包覆了自对准掩膜体82B。内介电层50的一种示例但不限定的形成方式是CVD氧化层淀积,淀积介质层具体为LTO(低温氧化硅)或HTO(高温氧化硅)加上BPSG(硼磷硅玻璃)或PSG(磷硅玻璃)的组合。Referring to FIG. 17, step S17 includes forming aninner dielectric layer 50 on thefirst gate 41 and thesecond gate 42 by means of deposition covering, so that thefirst gate 41 and the second gate are formed 42 is an embedded structure. In step S17, theinner dielectric layer 50 is also deposited and covered on theactive layer 30, and the self-alignedmask body 82B is covered. An exemplary but non-limiting formation method of theinner dielectric layer 50 is CVD oxide deposition, and the deposition dielectric layer is specifically LTO (low temperature silicon oxide) or HTO (high temperature silicon oxide) plus BPSG (borophosphosilicate glass) Or a combination of PSG (phosphosilicate glass).

参照图18，步骤S18作为一个选置步骤，包括对内介电层50的形状加工，以露出源极领域结33;优选的，内介电层50的顶面不超过所述处理表面11。步骤S18的一种示例但不限定的方法包括：S181、CMP(化学机械研磨)去掉所述处理表面11上的内介电层50与自对准掩膜体82B，除了CMP也可以使用或还包括干法刻蚀或湿法刻蚀的方法;S182、局部刻蚀所述处理表面11以下的内介电层50,使内介电层50的上表面低于所述处理表面11,最终得到的内介电层50还具有不低于300A的厚度且其表面凹陷于对应的所述第一沟槽13与所述沟槽31中。在步骤S18后,所述有源区30的上表面为露出。18, step S18, as an optional step, includes processing the shape of theinner dielectric layer 50 to expose thesource field junction 33; preferably, the top surface of theinner dielectric layer 50 does not exceed theprocessing surface 11. An exemplary but non-limiting method of step S18 includes: S181, CMP (chemical mechanical polishing) to remove theinner dielectric layer 50 and the self-alignedmask body 82B on theprocessing surface 11, in addition to CMP, it can also be used or also A method including dry etching or wet etching; S182, partially etching theinner dielectric layer 50 below thetreatment surface 11, so that the upper surface of theinner dielectric layer 50 is lower than thetreatment surface 11, and finally obtain Theinner dielectric layer 50 also has a thickness of not less than 300A and its surface is recessed into the correspondingfirst trenches 13 and thetrenches 31 . After step S18, the upper surface of theactive region 30 is exposed.

参照图19，步骤S19作为一个选置步骤，用于形成有源区30中的欧姆接触层34,以利与源极层60的结合。欧姆接触层34位于有源区30的顶层,分隔于所述源极领域结33之间且显露于所述处理表面11。步骤S19的一种示例但不限定的方法包括：S191、以注入BF₂或B11等反型掺杂物在所述源极领域结33之间形成P+区域，此作为欧姆接触层34的一种示例具体化;S192、光刻定义连接栅极41,42的第一接触孔与连接隔离栅作用的源极延伸倒鳍20的第二接触孔(在器件区之外,图未示出)，以氧化层刻蚀去除其接点表面残留的氧化层,在栅极41,42和源极延伸倒鳍20的源极接触孔区域氧化层并露出个别的导电表面,源极延伸倒鳍20的第二接触孔在结构上可能穿过对应位置上的第二栅极42,对第二接触孔贯穿第二栅极42的侧表面形成氧化即可,或者源极延伸倒鳍20延伸长于第二栅极42,又或者源极延伸倒鳍20的延伸段与第二栅极42的延伸段形成错位,使第二接触孔不会贯穿第二栅极42,达到第二栅极42与源极延伸倒鳍20的讯号分离连接。另外,关于欧姆接触层34的自对准图形化有多种的实施方法,一种是在利用处理表面11上内介电层50与自对准掩膜体82B的刻蚀选择比,在自对准掩膜体82B外露于内介电层50之后先刻蚀掉自对准掩膜体82B,在处理表面11上的剩余内介电层50便能作为用于形成欧姆接触层34的自对准硬掩膜层;另一种是在内介电层50沉淀覆盖之前,将掩膜层涂覆在处理表面11上,刻蚀掉自对准掩膜体82B,图案化掩膜层便能作为用于形成欧姆接触层34的自对准掩膜层;还有一种示例方法是在处理表面11上全表面能量注入P-层掺杂,有源区30的主体层原本就是P-body区,其表面就会有较高的P型特性,而源极领域结33是N+能量注入,其表面的浅局部反向注入不影响整体电传导的作用。19, step S19 is used as an optional step for forming theohmic contact layer 34 in theactive region 30 to facilitate the combination with thesource layer 60. Anohmic contact layer 34 is located on the top layer of theactive region 30 , separated between thesource field junctions 33 and exposed to theprocessing surface 11 . An exemplary but non-limiting method of step S19 includes: S191, forming a P+ region between thesource field junctions 33 by implanting inversion dopants such as BF₂ or B11, which is a kind ofohmic contact layer 34 The example is embodied; S192, lithography defines the first contact hole connecting thegates 41, 42 and the second contact hole (outside the device area, not shown in the figure) of the source extension invertedfin 20 connected to the isolation barrier, The remaining oxide layer on the contact surface is removed by oxide layer etching, and the oxide layer is exposed in the source contact hole region of thegate electrode 41, 42 and the source electrode extendinginverted fin 20 to expose the individual conductive surfaces. The two contact holes may pass through thesecond gate 42 at the corresponding position in structure, and the side surface of the second contact hole penetrating thesecond gate 42 may be oxidized, or thesource extension fin 20 may extend longer than the second gate Theelectrode 42, or the extension of thesource extension fin 20 and the extension of thesecond gate 42 form a dislocation, so that the second contact hole does not penetrate thesecond gate 42, and thesecond gate 42 and the source extend The signals of theinverted fins 20 are separated and connected. In addition, there are various implementation methods for the self-aligned patterning of theohmic contact layer 34. One is to use the etching selectivity ratio between theinner dielectric layer 50 and the self-alignedmask body 82B on theprocessing surface 11, and in the self-aligned patterning After thealignment mask body 82B is exposed to theinner dielectric layer 50, the self-alignment mask body 82B is etched away first, and the remaininginner dielectric layer 50 on theprocessing surface 11 can be used as a self-alignment layer for forming theohmic contact layer 34. A quasi-hard mask layer; the other is to coat the mask layer on theprocessing surface 11 before the deposition and covering of theinner dielectric layer 50, and etch away the self-alignedmask body 82B, and the patterned mask layer can be As a self-aligned mask layer for forming theohmic contact layer 34; there is also an example method of full surface energy implantation of P-layer doping on the treatedsurface 11, and the body layer of theactive region 30 is originally the P-body region , its surface will have higher P-type characteristics, and thesource field junction 33 is N+ energy injection, and the shallow local reverse injection on its surface does not affect the overall electrical conduction.

参照图20，对应步骤S20是在所述漏极外延层10上形成源极层60，所述源极层60如上所述源极接触孔连接方式能等电位连接所述源极延伸倒鳍20，所述场效晶体管的沟道分别位于所述第一栅极41的两侧与所述第二栅极42的两侧。在两个相邻的源极延伸倒鳍20之间,纵向沟道数量为2+2×N,N为第一栅极41在两个相邻的源极延伸倒鳍20之间的数量。在形成所述源极层60的步骤S20中，所述源极层60除了覆盖所述内介电层50，还与欧姆接触层34产生结合,更导电连接至所述源极领域结33，所述源极层60的材质为金属;所述源极层60由淀积金属层形成，具体可包括但不限于金属阻挡层和导电金属层两层，具体金属材料可以是但不限于以下的选择组合:Ti\TiN\Ta\TaN\TiW\W与AL\AlCu\AlSiCu等，步骤S20包括：S201,形成包括源极层60的淀积金属层，金属层厚度可介于1～10um;S202，经过退火淀积金属层与欧姆接触层34形成欧姆接触;之后S203，通过光刻定义出顶面上的源极接触区和栅极接触区;S204,再以刻蚀方式形成源极接触区和栅极接触区的金属层,其中源极接触区的金属层具体如图1中的源极层60,栅极接触区的金属层图未示出。Referring to FIG. 20 , corresponding to step S20 , asource layer 60 is formed on thedrain epitaxial layer 10 , and thesource layer 60 can be connected to thesource extension fins 20 in an equipotential manner as described above. , the channels of the field effect transistors are respectively located on both sides of thefirst gate 41 and on both sides of thesecond gate 42 . Between two adjacent source extension invertedfins 20 , the number of vertical channels is 2+2×N, where N is the number of thefirst gate 41 between two adjacent source extension invertedfins 20 . In the step S20 of forming thesource layer 60, thesource layer 60 not only covers theinner dielectric layer 50, but also combines with theohmic contact layer 34, and is more conductively connected to thesource field junction 33, The material of thesource electrode layer 60 is metal; thesource electrode layer 60 is formed by depositing a metal layer, which may specifically include but not limited to a metal barrier layer and a conductive metal layer, and the specific metal material may be but not limited to the following Select the combination: Ti\TiN\Ta\TaN\TiW\W and AL\AlCu\AlSiCu, etc. Step S20 includes: S201, forming a deposited metal layer including thesource layer 60, the thickness of the metal layer can be between 1 ~ 10um; S202, annealing and depositing a metal layer to form an ohmic contact with theohmic contact layer 34; then S203, defining a source contact region and a gate contact region on the top surface by photolithography; S204, forming a source contact by etching region and the metal layer of the gate contact region, wherein the metal layer of the source contact region is specifically thesource layer 60 in FIG. 1 , and the metal layer of the gate contact region is not shown.

在形成所述源极层60的步骤后，对所述漏极衬底1的背面12进行晶背减薄与晶背金属化。源极层60具体是金属材质,最终制得的场效晶体管的上方是源极接触垫,可由所述源极层60的上表面提供,场效晶体管的下方是漏极接触垫16,由背面12金属化形成,场效晶体管的结构即位于源漏极的金属垫之间,如图1所示。After the step of forming thesource layer 60 , backside thinning and backside metallization are performed on thebackside 12 of the drain substrate 1 . Thesource layer 60 is specifically made of a metal material, the source contact pad is located above the final field effect transistor, which can be provided by the upper surface of thesource layer 60, and thedrain contact pad 16 is located below the field effect transistor. 12 Metallization is formed, and the structure of the field effect transistor is located between the metal pads of the source and drain, as shown in Figure 1.

方法实施例的基础原理为：利用源极延伸倒鳍20之间的第一栅极41与源极延伸倒鳍20上的第二栅极42的嵌埋制作,减少半导体制程中在漏极外延层10制作多沟槽的工艺次数,且沟道密集化，最终制得电子流区间均匀化化的场效晶体管。The basic principle of the method embodiment is as follows: utilizing the embedded fabrication of thefirst gate 41 between the source extendedinverted fins 20 and thesecond gate 42 on the source extendedinverted fin 20 to reduce drain epitaxy in the semiconductor process The number of processes required to fabricate multiple trenches forlayer 10 and the channels are dense, and finally a field effect transistor with uniform electron flow interval is fabricated.

本发明的实施例还提出一种半导体芯片装置，包括：如上所述任意技术方案可能组合的场效晶体管结构,或者,配合参阅图21使用的场效晶体管结构包括:位于处理表面11下的漏极外延层10、位于所述处理表面11上的源极层60以及嵌入于所述漏极外延层10内的源极延伸倒鳍20、第一栅极41与第二栅极42;所述第一栅极41排列在所述源极延伸倒鳍20之间,所述第二栅极42对准在所述源极延伸倒鳍20上,所述第一栅极41与所述第二栅极42的两侧各形成有成对由所述源极层60至所述漏极外延层10内部并联的对称型沟道;优选的,所述漏极外延层10在对应所述源极延伸倒鳍20的底部部位形成屏蔽栅底部浮空反极型柱底结70。An embodiment of the present invention also provides a semiconductor chip device, comprising: a field effect transistor structure that may be combined with any of the above technical solutions, or, the field effect transistor structure used in conjunction with FIG. 21 includes: a drain located under theprocessing surface 11 Theelectrode epitaxial layer 10, thesource electrode layer 60 on theprocessing surface 11, and the sourceelectrode extension fins 20, thefirst gate electrode 41 and thesecond gate electrode 42 embedded in thedrain epitaxial layer 10; the Thefirst gate 41 is arranged between the source extended backfins 20, thesecond gate 42 is aligned on the source extended backfin 20, thefirst gate 41 and the second gate Two sides of thegate electrode 42 are respectively formed with pairs of symmetrical channels connected in parallel from thesource electrode layer 60 to thedrain epitaxial layer 10; preferably, thedrain epitaxial layer 10 is corresponding to the source electrode. The bottom portion of the extendedinverted fin 20 forms a floatinginversion post-bottom junction 70 at the bottom of the shield gate.

实施例的基础原理为：位于处理表面11上的源极层60以及嵌埋于漏极外延层10的第一栅极41与第二栅极,建立以有源层30厚度方向定义的多个竖立并联沟道，电子流能分区均匀输出(或输入)在漏极衬底1的背面12,每一分区对应在源极延伸倒鳍20之间。当半导体芯片装置安装在载板上即完成源极或/与漏极接触连接,能节省一个或所有电极位的连接操作，安装方式可以覆晶方式或是正向安装方式，处理表面11朝向载板的覆晶方式能节省源极或/源极与栅极接触的连接,处理表面11背离载板的正向安装方式能节省漏极接触的连接。随着芯片越来越薄,不需要考虑芯片背面漏电流的问题。电子流由源极层60进行分流,在第一栅极41与第一栅极42的电场效应以及源极延伸倒鳍20分区隔离作用下,沟道层32纵向导通,电子流分区且区域均匀化到达漏极衬底1的背面12,源极延伸倒鳍20能避免电子流在漏极外延层10内提前汇集,由源极层60与背面12之间为分流交错隔离栅的形态,以形成较均匀的电子流分布,特别适用于半导体功率器件的应用。The basic principle of the embodiment is: thesource layer 60 located on theprocessing surface 11 and thefirst gate 41 and the second gate embedded in thedrain epitaxial layer 10 create a plurality of gate electrodes defined in the thickness direction of theactive layer 30 . The parallel channels are erected, and the electron current can be divided into uniform output (or input) on theback surface 12 of the drain substrate 1, and each division corresponds to the source extending between theinverted fins 20. When the semiconductor chip device is mounted on the carrier board, the source or/and drain contact connection is completed, which can save the connection operation of one or all electrode positions. The mounting method can be flip-chip or forward mounting, and theprocessing surface 11 faces the carrier board. The flip-chip method can save the connection of the source or/or source and gate contacts, and the forward mounting method in which thetreatment surface 11 faces away from the carrier can save the connection of the drain contact. As the chip gets thinner and thinner, there is no need to consider the problem of leakage current on the backside of the chip. The electron flow is shunted by thesource layer 60. Under the effect of the electric field between thefirst gate 41 and thefirst gate 42 and the partition isolation of the source extension andinverted fin 20, thechannel layer 32 is longitudinally conductive, and the electron flow is divided into different regions. The uniformity reaches thebackside 12 of the drain substrate 1, and the source extends theinverted fin 20 to prevent the electron flow from gathering in advance in thedrain epitaxial layer 10, and thesource layer 60 and thebackside 12 are in the form of shunt and staggered isolation gates. In order to form a more uniform electron current distribution, it is especially suitable for the application of semiconductor power devices.

本具体实施方式的实施例均作为方便理解或实施本发明技术方案的较佳实施例，并非依此限制本发明的保护范围，凡依本发明的结构、形状、原理所做的等效变化，均应被涵盖于本发明的请求保护范围内。The examples of this specific embodiment are all preferred examples for the convenience of understanding or implementing the technical solutions of the present invention, and are not intended to limit the protection scope of the present invention. All should be covered within the claimed protection scope of the present invention.

Claims (5)

Translated fromChinese

1.一种多栅极变化的场效晶体管结构的制造方法，其特征在于，包括：1. a manufacturing method of a field effect transistor structure with multi-gate variation, is characterized in that, comprising:提供漏极衬底(1)，具有由漏极外延层(10)提供的处理表面(11)与对应的背面(12)，由所述处理表面(11)刻蚀形成相互平行的第一沟槽(13);A drain substrate (1) is provided, having a treated surface (11) provided by the drain epitaxial layer (10) and a corresponding back surface (12), and mutually parallel first trenches are formed by etching the treated surface (11) slot(13);在所述处理表面(11)与所述第一沟槽(13)内形成第一效应氧化层(91)，使所述第一沟槽(13)的内壁绝缘处理;A first effect oxide layer (91) is formed in the treated surface (11) and the first trench (13), so that the inner wall of the first trench (13) is insulated;以沉淀填充方式在所述第一沟槽(13)的底部内设置源极延伸倒鳍(20)，并去除所述源极延伸倒鳍(20)与所述第一效应氧化层(91)在所述处理表面(11)上的部位，所述第一沟槽(13)的深度不超过所述漏极外延层(10)的厚度;A source extension back fin (20) is provided in the bottom of the first trench (13) by means of precipitation filling, and the source extension back fin (20) and the first effect oxide layer (91) are removed At the position on the treated surface (11), the depth of the first trench (13) does not exceed the thickness of the drain epitaxial layer (10);由所述处理表面(11)刻蚀形成位于所述第一沟槽(13)之间的第二沟槽(31);A second trench (31) located between the first trenches (13) is formed by etching the treated surface (11);在所述处理表面(11)上、所述第二沟槽(31)内与所述第一沟槽(13)的剩余空间内形成第二效应氧化层(92)，使所述第二沟槽(31)的内壁与所述第一沟槽(13)剩余空间的内壁绝缘处理;A second effect oxide layer (92) is formed on the treated surface (11), in the second trench (31) and in the remaining space of the first trench (13), so that the second trench (13) The inner wall of the groove (31) is insulated from the inner wall of the remaining space of the first groove (13);以沉淀填充方式在所述第二沟槽(31)内设置第一栅极(41)以及在所述第一沟槽(13)剩余空间内设置第二栅极(42)，所述第二栅极(42)位于所述源极延伸倒鳍(20)上;所述第二栅极(42)与所述第一栅极(41)具有不同的形状轮廓;A first gate electrode (41) is arranged in the second trench (31) and a second gate electrode (42) is arranged in the remaining space of the first trench (13) by means of deposition and filling, and the second gate electrode (42) is arranged in the remaining space of the first trench (13). A gate (42) is located on the source extending inverted fin (20); the second gate (42) and the first gate (41) have different shape profiles;在所述漏极外延层(10)的所述处理表面(11)下以能量注入方式形成有源层(30)，所述有源层(30)的底面在所述第二沟槽(31)与所述第一沟槽(13)剩余空间能贯穿的范围内;An active layer (30) is formed under the treatment surface (11) of the drain epitaxial layer (10) by means of energy injection, and the bottom surface of the active layer (30) is in the second trench (31). ) within the range that the remaining space of the first groove (13) can penetrate;以沉淀覆盖方式在所述第一栅极(41)与所述第二栅极(42)上形成内介电层(50),使所述第一栅极(41)与所述第二栅极(42)为嵌埋结构;An inner dielectric layer (50) is formed on the first gate electrode (41) and the second gate electrode (42) in a deposition covering manner, so that the first gate electrode (41) and the second gate electrode are formed The pole (42) is an embedded structure;在所述漏极外延层(10)上形成源极层(60)，所述源极层(60)等电位连接所述源极延伸倒鳍(20)，所述场效晶体管的沟道分别位于所述第一栅极(41)的两侧与所述第二栅极(42)的两侧;A source layer (60) is formed on the drain epitaxial layer (10), the source layer (60) is equipotentially connected to the source extension back fin (20), and the channels of the field effect transistors are respectively on both sides of the first grid (41) and on both sides of the second grid (42);其中,在形成所述源极层(60)的步骤中，所述源极层(60)还覆盖于所述内介电层(50)上;在形成所述有源层(30)的步骤中,所述有源层(30)由所述漏极外延层(10)的所述处理表面(11)内化形成，所述内介电层(50)凹陷于所述处理表面(11),以利所述源极层(60)与所述有源区的欧姆接触的结合;Wherein, in the step of forming the source layer (60), the source layer (60) is also covered on the inner dielectric layer (50); in the step of forming the active layer (30) In the above, the active layer (30) is formed by internalization of the treated surface (11) of the drain epitaxial layer (10), and the inner dielectric layer (50) is recessed in the treated surface (11) , in order to facilitate the combination of the ohmic contact between the source layer (60) and the active region;其中,所述有源层(30)包括位于底层的沟道层(32)、位于所述沟道层(32)上且在沟槽开口两侧的源极领域结(33)以及位于顶层的欧姆接触层(34),所述欧姆接触层(34)分隔于所述源极领域结(33)之间且显露于所述处理表面(11),所述欧姆接触层(34)的厚度小于所述源极领域结(33)的下沉深度;所述源极领域结(33)具有朝向沟槽内部逐渐收敛的斜边,所述源极领域结(33)收敛底部的深度下沉深入到超过所述第一栅极(41)的顶部与第二栅极(42)的顶部;Wherein, the active layer (30) comprises a channel layer (32) located on the bottom layer, a source field junction (33) located on the channel layer (32) and on both sides of the trench opening, and a source region junction (33) located on the top layer. An ohmic contact layer (34), the ohmic contact layer (34) is separated between the source field junctions (33) and exposed on the treated surface (11), the thickness of the ohmic contact layer (34) is less than The sinking depth of the source field junction (33); the source field junction (33) has a hypotenuse that gradually converges toward the inside of the trench, and the depth of the convergent bottom of the source field junction (33) sinks deep to beyond the top of the first gate (41) and the top of the second gate (42);所述源极领域结(33)的形成方法包括：先在所述第一栅极(41)、所述第二栅极(42)上与所述处理表面(11)上形成第二硬掩膜沉淀;经过斜角刻蚀,所述第二硬掩膜沉淀形成为在所述第一栅极(41)与所述第二栅极(42)上的第二隔离氧化层(82)以及在所述处理表面(11)上的自对准掩膜体(82B);在位于所述处理表面(11)上的自对准掩膜体(82B)的遮挡下斜角离子注入用于形成所述源极领域结(33)的掺杂物;The method for forming the source field junction (33) includes: firstly forming a second hard mask on the first gate (41), the second gate (42) and the processing surface (11). film deposition; after bevel etching, the second hard mask deposition is formed as a second isolation oxide layer (82) on the first gate electrode (41) and the second gate electrode (42) and Self-aligned mask body (82B) on said processing surface (11); oblique ion implantation under the occlusion of self-aligned mask body (82B) on said processing surface (11) for forming a dopant of the source field junction (33);其中斜角离子注入为在有源层(30)中进行正极型注入,以形成有源层(30)中的源极领域结(33)，在位于所述处理表面(11)上的自对准掩膜体(82B)的遮挡下斜角离子注入用于形成源极领域结(33)的掺杂物;注入能量20～100kev，注入角度5～85°，注入剂量10¹⁴ ～10¹⁶ ions/cm²;在自对准掩膜体(82B)的遮挡下，第一沟槽(13)与第二沟槽(31)开口侧的两相邻源极领域结(33)不会相接,这两相邻源极领域结(33)之间有一个位于自对准掩膜体(82B)下的分隔区;The oblique ion implantation is a positive type implantation in the active layer (30) to form a source field junction (33) in the active layer (30), and a self-aligned junction on the processing surface (11) is formed. The oblique angle ion implantation is used to form the source field junction (33) dopant under the shielding of the quasi-mask body (82B); the implantation energy is 20-100kev, the implantation angle is 5-85°, and the implantation dose is 10¹⁴ ～ 10¹⁶ ions /cm² ; under the shielding of the self-aligned mask body (82B), the two adjacent source field junctions (33) on the opening side of the first trench (13) and the second trench (31) will not be in contact , between these two adjacent source field junctions (33) there is a separation region located under the self-aligned mask body (82B);所述欧姆接触层(34)的形成方法包括：在处理表面(11)上全表面能量注入P-层掺杂,有源区(30)的主体层原本就是P-body区,表面会有较高的P型特性,而源极领域结(33)是N+能量注入。The method for forming the ohmic contact layer (34) includes: injecting full-surface energy into the P-layer doping on the treatment surface (11), the main body layer of the active region (30) is originally the P-body region, and the surface will have a relatively high density. High P-type characteristics, while the source field junction (33) is N+ energy injected.2.根据权利要求1所述的场效晶体管结构的制造方法，其特征在于，2. The method for manufacturing a field effect transistor structure according to claim 1, wherein,在提供所述漏极衬底(1)的步骤后,还包括：以离子植入方式在所述漏极外延层(10)在对应所述第一沟槽(13)底部的部位形成屏蔽栅底部浮空反极型柱底结;具体的,所述漏极衬底(1)为导电型半导体晶圆;After the step of providing the drain substrate (1), the method further includes: forming a shielding gate on the drain epitaxial layer (10) at a portion corresponding to the bottom of the first trench (13) by means of ion implantation A bottom-floating inverse pole-bottom junction; specifically, the drain substrate (1) is a conductive semiconductor wafer;或/与,在形成所述第一效应氧化层(91)的步骤中,包括：以热氧化方式在所述第一沟槽(13)内形成所述第一效应氧化层(91)的氧化层;之后以沉淀方式在所述第一沟槽(13)内形成所述第一效应氧化层(91)的淀积层;具体的，所述第一效应氧化层(91)的材质包括氧化硅;Or/and, in the step of forming the first effect oxide layer (91), comprising: forming an oxidation of the first effect oxide layer (91) in the first trench (13) by thermal oxidation layer; then a deposition layer of the first effect oxide layer (91) is formed in the first trench (13) by precipitation; specifically, the material of the first effect oxide layer (91) includes oxide silicon;或/与,在设置所述源极延伸倒鳍(20)的步骤中,所述源极延伸倒鳍(20)与所述第一效应氧化层(91)在所述处理表面(11)上的部位去除方法包括选择性刻蚀或是化学机械研磨与回刻蚀;所述源极延伸倒鳍(20)的材质包括导电多晶硅;Or/and, in the step of disposing the source extension back fin (20), the source extension back fin (20) and the first effect oxide layer (91) are on the processing surface (11) The part removal method includes selective etching or chemical mechanical polishing and etching back; the material of the source extension back fin (20) includes conductive polysilicon;或/与,在形成所述第二沟槽(31)的步骤中,包括的前置步骤是：在所述处理表面(11)上形成第一硬掩膜层,以遮盖所述处理表面(11)以及所述源极延伸倒鳍(20)的顶部;在形成所述第二沟槽(31)的步骤后,包括的后置步骤是：刻蚀在所述处理表面(11)上的所述第一硬掩膜层,在所述源极延伸倒鳍(20)上的所述第一硬掩膜层被保留形成为第一隔离氧化层;在所述第二沟槽(31)形成之后,以离子植入方式在所述漏极外延层(10)在对应所述第二沟槽(31)底部的部位形成栅下浮空反极型结;Or/and, in the step of forming the second trench (31), the included pre-step is: forming a first hard mask layer on the processing surface (11) to cover the processing surface (11). 11) and the top of the source extending inverted fin (20); after the step of forming the second trench (31), the post-step included is: etching the surface on the processing surface (11) For the first hard mask layer, the first hard mask layer on the source extension inverted fin (20) is retained to form a first isolation oxide layer; in the second trench (31) After the formation, a floating inversion junction under the gate is formed on the drain epitaxial layer (10) at a position corresponding to the bottom of the second trench (31) by means of ion implantation;或/与,在形成所述第二效应氧化层(92)的步骤中,所述第二效应氧化层(92)具体为栅氧化层,以热氧化或热氧化加上淀积方式形成所述栅氧化层于所述第二沟槽(31)与所述第一沟槽(13)剩余空间的内壁与所述处理表面(11)上;Or/and, in the step of forming the second effect oxide layer (92), the second effect oxide layer (92) is specifically a gate oxide layer, and the second effect oxide layer (92) is formed by thermal oxidation or thermal oxidation plus deposition. a gate oxide layer on the inner wall of the remaining space of the second trench (31) and the first trench (13) and the processing surface (11);或/与,在设置所述第一栅极(41)与第二栅极(42)的步骤中,去除所述第一栅极(41)与第二栅极(42)在所述处理表面(11)上的相接部位,去除方法包括选择性刻蚀或是化学机械研磨与回刻蚀,使所述第一栅极(41)与第二栅极(42)的顶面凹陷于所述处理表面(11);所述栅极的材质包括导电多晶硅,含有掺杂离子。Or/and, in the step of disposing the first gate (41) and the second gate (42), removing the first gate (41) and the second gate (42) on the treated surface (11), the removal method includes selective etching or chemical mechanical polishing and etching back, so that the top surfaces of the first gate (41) and the second gate (42) are recessed in the The treated surface (11) is provided; the material of the gate comprises conductive polysilicon and contains dopant ions.3.根据权利要求1所述的场效晶体管结构的制造方法，其特征在于，在形成所述源极层(60)的步骤中，所述源极层(60)的材质为金属;在形成所述源极层(60)的步骤后，对所述漏极衬底(1)的背面(12)进行晶背减薄与晶背金属化。3. The method for manufacturing a field effect transistor structure according to claim 1, wherein in the step of forming the source layer (60), the material of the source layer (60) is metal; After the step of the source layer (60), backside thinning and backside metallization are performed on the backside (12) of the drain substrate (1).4.一种多栅极变化的场效晶体管结构，其特征在于，基于如权利要求1所述的多栅极变化的场效晶体管结构的制造方法制得。4 . A field effect transistor structure with multi-gate variation, characterized in that, it is prepared based on the manufacturing method of the multi-gate variation field effect transistor structure as claimed in claim 1 .5.一种半导体芯片装置，其特征在于，包括：如权利要求4所述的一种多栅极变化的场效晶体管结构。5 . A semiconductor chip device, characterized in that , comprising: a multi-gate variation field effect transistor structure as claimed in claim 4 . 6 .

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