CN113223597A

Movatterモバイル変換

Info

Publication number: CN113223597A
Application number: CN202110591310.5A
Authority: CN
Inventors: 李士达; 雍尚刚; 武甲东
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2021-05-28
Filing date: 2021-05-28
Publication date: 2021-08-06
Anticipated expiration: 2041-05-28
Also published as: CN113223597B

Abstract

The disclosure relates to a flash memory testing method, a flash memory testing device, a storage medium and a terminal device, wherein the method comprises the following steps: reading first data from a region to be tested of a flash memory; generating a test vector according to the first data; performing data writing operation on the flash memory according to the test vector to enable second data to be stored in the area to be tested; and reading the second data from the area to be tested, and determining a test result aiming at the area to be tested according to whether the second data is consistent with the test vector. According to the embodiment of the application, the flash memory erasing times can be reduced when the function of the area to be tested is tested, the time is saved, the service life of the flash memory is prolonged, and the data of the area not to be tested can be prevented from being modified by mistake.

Description

Flash memory testing method and device, storage medium and terminal equipment

Technical Field

The present disclosure relates to the field of terminal devices, and in particular, to a flash memory testing method and apparatus, a storage medium, and a terminal device.

Background

In mobile communication devices, Flash memory (Flash) is generally used as a storage medium. A flash memory is a non-volatile random access memory (NVRAM), which is a type of ROM and can perform more than ten thousand erase/write operations.

In the prior art, the minimum unit of flash memory erase is generally a block (block) or a sector (sector), and if a page (page) in a flash memory needs to be tested to determine whether the function of the page is normal, most of data corresponding to the page that does not need to be tested needs to be erased, which wastes a lot of time and resources, and thus a more efficient flash memory test method is urgently needed.

Disclosure of Invention

In view of this, the present disclosure provides a flash memory testing method, apparatus, storage medium, and terminal device.

According to an aspect of the present disclosure, there is provided a flash memory testing method, the method including: reading first data from a region to be tested of a flash memory; generating a test vector according to the first data; performing data writing operation on the flash memory according to the test vector to enable second data to be stored in the area to be tested; and reading the second data from the area to be tested, and determining a test result aiming at the area to be tested according to whether the second data is consistent with the test vector.

According to the embodiment of the application, the first data are read from the area to be tested of the flash memory; generating a test vector according to the first data; performing data writing operation on the flash memory according to the test vector to enable second data to be stored in the area to be tested; the second data are read from the area to be tested, the test result aiming at the area to be tested is determined according to whether the second data are consistent with the test vector or not, the test vector used for testing can be flexibly determined according to the condition that the first data are stored in the area to be tested when the function of the area to be tested is tested, meanwhile, the flash memory erasing times can be reduced, the time is saved, the service life of the flash memory is prolonged, and the data of the area not to be tested are prevented from being mistakenly modified.

In one possible implementation manner, performing a data write operation on the flash memory according to the test vector includes: and under the condition of not carrying out erasing operation, carrying out data writing operation on the flash memory according to the test vector.

According to the embodiment of the application, under the condition that the erasing operation is not carried out, the data writing operation is carried out on the flash memory according to the test vector, so that the whole block or sector in the flash memory does not need to be erased when the function of the area to be tested is tested, the data loss of a non-test area is prevented, and the service life of the flash memory is prolonged.

In one possible implementation, generating a test vector according to the first data includes: and under the condition that all or part of bits in the area to be tested can be rewritten with data before erasing according to the first data, generating a test vector aiming at all or part of bits.

According to the embodiment of the application, the method comprises the following steps: and generating a test vector aiming at all or part of the bits under the condition that all or part of the bits in the area to be tested can be rewritten with data before erasing according to the first data, so that the area to be tested without data can be tested when the function of the area to be tested is tested, and all or part of the bits in the area to be tested with data written and capable of rewriting with data before erasing can be tested, so that the test is more free and flexible.

In one possible implementation, the vector type of the test vector corresponds to the function of the test.

Therefore, the type of the test vector can be flexibly selected according to the test requirement so as to test whether the corresponding function is normal or not.

In one possible implementation, the vector types may include one or more of all 0 vectors, all 1 vectors, checkerboard vectors, march pattern vectors, and gapping pattern vectors.

In one possible implementation, the testing may include one or more of a short circuit test, an open circuit test, a disturb test, an address error test for the area to be tested.

Therefore, different functions of the area to be tested can be tested according to the test requirements, and the test content is more flexible and richer.

In one possible implementation, each of the regions to be tested is one byte.

According to an aspect of the present disclosure, there is provided a flash memory testing apparatus, the apparatus including: the first module is used for reading first data from a to-be-tested area of the flash memory; a second module for generating a test vector according to the first data; the third module is used for carrying out data writing operation on the flash memory according to the test vector so that second data are stored in the area to be tested; and the fourth module is used for reading the second data from the area to be tested and determining a test result aiming at the area to be tested according to whether the second data is consistent with the test vector.

In one possible implementation, each of the regions to be tested is one byte.

According to another aspect of the present disclosure, a terminal device is provided, wherein the terminal device includes a flash memory controller, and the flash memory controller is configured to execute the method described above.

According to another aspect of the present disclosure, there is provided a flash memory testing apparatus including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the above method.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a block diagram illustrating a flash memory storage system according to an embodiment of the present application.

FIG. 2 shows a schematic diagram of a test site in a flash memory according to an embodiment of the present application.

FIG. 3 shows a flow chart of a flash memory testing method according to an embodiment of the present application.

FIG. 4 shows a flow chart of a flash memory testing method according to an embodiment of the present application.

Fig. 5 is a block diagram illustrating a flash memory test apparatus according to an embodiment of the present application.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Fig. 1 is a block diagram illustrating a flash memory storage system according to an embodiment of the present application. Those skilled in the art should understand that the structure in fig. 1 is only an example, and the embodiment of the present application is not limited to be applied to the exemplary scenario shown in fig. 1. As shown in fig. 1, the flashmemory storage system 100 may include aflash memory controller 110, abus connection interface 120, and aflash memory 130. Theflash memory system 100 may be connected to ahost 200, and data may be written to theflash memory system 100 or read from theflash memory system 100 through thehost 200. The flashmemory storage system 100 may be a portable disk, a memory card or a Solid State Drive (SSD), which is not limited in the present application.

Theflash memory controller 110 may be used to coordinate the overall operations of thebus interface 120 and theflash memory 130, such as data storage, data reading, and data erasing. Theflash controller 110 may include a microprocessor 110a and aflash interface 110 b.

The microprocessor 110a may be used to manage and operate theflash memory 130, such as performing a wear leveling (wear leveling) function, a bad block management function, a mapping table (mapping table), and the like. In the embodiment of the present application, the microprocessor 110a may be configured to perform the steps of the flash memory test method according to the embodiment.

Theflash interface 110b is coupled to the microprocessor 110a and may be used to access theflash memory 130. For example, data to be written by thehost 200 to theflash memory 130 can be converted into a format accepted by theflash memory 130 through theflash memory interface 110 b.

In addition, although not shown in fig. 1, theflash memory controller 110 may further include a memory management module, a buffer memory, a power management module, and other functional modules commonly used in a flash memory.

Thebus connection interface 120 may be used to connect ahost 200. Thebus connection interface 120 may be a USB interface, and thebus connection interface 120 may also be a PCI Express interface, an IEEE 1394 interface, a SATA interface, an MS interface, an MMC interface, an SD interface, a CF interface, an IDE interface, or other suitable data transmission interfaces, which is not limited in this application.

Theflash memory 130 is coupled to theflash controller 110 and may be used for storing data. Theflash memory 130 may be divided into a plurality of physical blocks (physical blocks) 130-0 to 130-N, and the physical blocks are simply referred to as blocks for convenience of description. A block may be the smallest unit of erase in a flash memory. That is, each block contains the minimum number of memory cells that are erased together. In one possible implementation, each block may also be partitioned into sectors (sectors) according to different flash memory designs, in which case the sectors may be the smallest unit of erase in a flash memory. Each block (or sector) may be divided into pages (fig. 1 illustrates an example of how a block may be divided into pages). A page may be a minimum unit of programming (program), that is, a page may be a minimum unit of writing data or reading data. Each page may be partitioned into 256 bytes (bytes), each of which may include 8 bits (bits).

A block (or sector) may be comprised of any number of pages, such as 64 pages, 128 pages, 256 pages, and so on. The blocks 130-0 through 130-N may also be generally grouped into zones (zones) with the zones managing the memory operating somewhat independently of each other to increase the parallelism of operation execution and simplify management complexity.

Some examples of the flash memory test method according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

FIG. 2 shows a schematic diagram of a test site in a flash memory according to an embodiment of the present application. As shown in fig. 2, the whole rectangular box may represent a certain block (or a certain sector) in the flash memory, and here, taking the example of representing block 2 (i.e. 2 nd block), each row in the rectangular box may represent one page in the block (or sector), and n may represent the total number of pages in the block (or sector). The shaded portion in page 2 may represent a byte of written data, such as byte 2 (i.e., the 2 nd byte).

The function of a certain byte in the flash memory can be tested, and the function of a plurality of bytes can also be tested, wherein the plurality of bytes can be distributed in one page or a plurality of pages. The test location (i.e., the memory address of the test) may be a byte of written data or a byte of unwritten data.

As can be seen from the above, the minimum unit of erasing in the flash memory is a block (or sector), and the minimum unit of writing or reading data is a page, for example, in the case that a certain page in the block (or sector) needs to be functionally tested, if the data of other pages in the block (or sector) needs to be erased by the method of erasing first and then testing, a lot of time resources are wasted, and the data in other pages can be lost.

In connection with the exemplary application scenario shown in fig. 1, fig. 3 shows a flowchart of a flash memory testing method according to an embodiment of the present application. As shown in fig. 3, the steps of the flash memory test method include:

in step S301, the microprocessor 110a reads data in a page corresponding to the test position through theflash memory interface 110 b.

In one example, the microprocessor 110a may perform steps S301-S304 according to a test instruction of thehost 200, and feed back a test result to the host.

The page corresponding to the test position may be one page or multiple pages, the corresponding page may only include the test position, and may also include other positions in the page except the test position, the test position may be one byte or multiple bytes, and the multiple bytes may be continuous or non-continuous. The byte corresponding to the test location may be referred to as a region to be tested, and the data of the test location may be referred to as first data.

Taking fig. 2 as an example, if the test locations to be tested are the 2 nd byte and the 10 th byte in page 2, the data read can be all the data in page 2. From the read data, the 2 nd byte and the 10 th byte (i.e., the byte corresponding to the test position) in page 2 can be determined as the first data.

In step S302, the microprocessor 110a determines a test vector according to the read data.

According to the read data, the test vector can be determined according to the test requirement. The bytes in which data is not written at the test position and the bytes in which data is written can be determined according to the read data, which bits can be rewritten before erasing, the test vector corresponds to the bytes in which data is not written and the bits in which data can be rewritten before erasing, the vector type of the test vector may be any one of an all-0 vector, an all-1 vector, a checkerboard (checkerboard) vector, a march pattern vector, and a gaploping pattern vector, and the vector type may also be any other vector, which is not limited in this application.

The functional tests performed for the test locations may include short circuit tests, open circuit tests, disturb tests, address error tests, and the like. The vector type may correspond to a function of the test. For example, in the case where the vector type is all 0 vectors, all 1 vectors, the functional test performed may be a short circuit test or an open circuit test for the test location; in the case where the vector type is a checkerboard vector (or a march pattern vector or a gapping pattern vector), the functional test performed may be an address error test or a disturb test for the test location. Those skilled in the art can combine the prior art to determine the corresponding way of the vector type and the tested function as required.

It should be noted that when a certain byte in which data is not written is included in the test location, the byte may be considered to be re-writable before erasing, and the vector type of the test vector corresponding to the byte may be determined as one or more of the above vector types as needed. In the case where a certain byte of written data is included in the test location, the function of the bit of the byte to which a value cannot be rewritten before erasing (for example, the bit of the byte to which data is written, the bit of which value is 1) cannot be tested, and the function of the bit of the byte to which a value can be rewritten before erasing (for example, the bit of the byte to which data is written, the bit of which value is 0) can be tested, the test vector may correspond to the bit of the byte to which a value can be rewritten, and the vector type refers to, for example, one or more of the above-described vector types.

In step S303, the microprocessor 110a writes the page containing the test vector into the test location in the flash memory through theflash interface 110 b.

Since the flash memory writes data in units of pages and starts to write from the 1 st byte of the corresponding page every time of writing, one or more pages of data containing test vectors can be written into one or more pages of the test location, wherein the length of the written data can be determined according to the number of pages of the byte distribution corresponding to the test location. Taking fig. 2 as an example, if the position of the 2 nd byte and the 10 th byte in page 2 needs to be tested, the length of the write data can be determined to be 1 page, and if the position of the 2 nd byte in page 2 and the 10 th byte in page 3 needs to be tested, the length of the write data is 2 pages.

Meanwhile, if it is desired to perform the test without changing the data in the flash memory except the test location, the values of the bits written in the data except the test vector may be consistent with the values of the corresponding bits of the data read from the one or more pages corresponding to the test location in step S301, so that the original data may not be modified.

The written data can include a plurality of test vectors corresponding to different test positions, and the vector types of the test vectors can be the same or different, so that multi-position and multi-type test tasks can be completed quickly.

In step S304, the microprocessor 110a reads the data in the page corresponding to the test position again through theflash memory interface 110b, and determines whether the function of the test position is normal according to the read data.

Under the condition that the function of the test position is normal, the data corresponding to the read test position in the step are consistent with the data in the test vector corresponding to the written test position; otherwise, it may be confirmed that the test site is not functioning properly.

Taking fig. 2 as an example, if the test location is the 10 th byte in the 2 nd page in the flash memory, and the 10 th byte has no data written before the test starts, if the data value of the read 10 th byte is consistent with the data value of the test vector of the 10 th byte written in step S303, it may be determined that the corresponding functions of the 2 nd page and the 10 th byte in the flash memory are normal, otherwise, if the data value of the read 10 th byte is inconsistent with the data value of the test vector of the 10 th byte written in step S303, it may be determined that the corresponding functions of the 2 nd page and the 10 th byte in the flash memory are not normal.

Still taking fig. 2 as an example, if the test location is the 2 nd byte in page 2 in flash memory, which is the byte to which data has been written, if it is determined in step S301 that the first 4 bits of the 8 bits in the 2 nd byte read for the first time are not re-writable with values before erasure (e.g. the first 4 bits are written with 1), the last 4 bits are re-writable with values before erasure (e.g. the last 4 bits are written with 0), the test object may become the last 4 bits in the 2 nd byte and the test vector may correspond to the last 4 bits of the 2 nd byte, written in the data, the bits outside the test vector may coincide with the bits read in step S301, for example, the value of the first 4 bits of the 2 nd byte in the write data may be identical to the value of the first 4 bits of the 2 nd byte read in step S301 (e.g., 1111 also). If the read value of the last 4 bits of the 2 nd byte is consistent with the data value of the test vector written in step S303, it may be described that the functions of the last 4 bits of the 2 nd page and the 2 nd byte are normal, otherwise, if the read value of the last 4 bits of the 2 nd byte is inconsistent with the data value of the test vector written in step S303, it may be described that the functions of the last 4 bits of the 2 nd page and the 2 nd byte are not normal.

As an example, in the above test process, after the test vector corresponding to the test position is determined in S302, if the test vector is a full 0 vector, a full 1 vector, or a checkerboard vector, in S303, after the page containing the test vector is written into the test position in the flash memory, it may be determined whether the function of the test position is normal according to whether the data in the page corresponding to the read test position is consistent with the value of the written test vector in S304. Where the all 0 vector may be, for example, [0,0,0 … … 0,0], i.e., each element in the vector has a value of 0; a full 1 vector may be, for example, [1,1,1.. 1,1], i.e., each element in the vector has a value of 1; the checkerboard vector may be, for example, [0,1,0 … … 1,0] or [1,0,1 … … 0,1], i.e., the values of adjacent elements in the vector are opposite.

In the case where the vector type of the test vector is march pattern vector, all 0 vectors may be written to the test locations first, for example in S303, in S304, the value of the test position corresponding to the first element in the vector is read, and in the case where the read value is 0, it may be determined that the test site corresponding to the first element functions normally, and then, it may return to S303, in S303, writing 1 to the test position corresponding to the first element, in S304, reading the value of the test position corresponding to the second element in the vector, in the case of a read value of 1, it can be determined that the test site corresponding to the second element functions normally, and repeating the processes of testing the functions of the test positions corresponding to the elements in the vector in S303 and S304 by analogy with the test positions corresponding to the third element to the last element in the vector.

Optionally, after the test is performed, the original data at the test position may be recovered according to the value read in step S301 as needed. For example, the value read in step S301 may be rewritten after erasing the data modified at the time of the test.

FIG. 4 shows a flow chart of a flash memory testing method according to an embodiment of the present application. The method may be used in a terminal device, for example, the microprocessor 100a described above in the terminal device, as shown in fig. 4, and includes:

step S401, reading first data from a to-be-tested area of a flash memory;

step S402, generating a test vector according to the first data;

step S403, performing data writing operation on the flash memory according to the test vector, so that second data are stored in the area to be tested;

step S404, reading the second data from the area to be tested, and determining a test result aiming at the area to be tested according to whether the second data is consistent with the test vector.

Wherein the area to be tested may be the test position above. For example, each region to be tested may be one byte, wherein a plurality of bytes corresponding to a plurality of regions to be tested may be distributed in one page, or a plurality of pages. The area to be tested can be preset according to the test requirement, and the area to be tested can be continuous or discontinuous, which is not limited in the application. The first data may be data corresponding to the test location in the data read in step S301 in fig. 3, and the second data may be data corresponding to the test vector in the test location in the data written in the flash memory in step S303 in fig. 3.

And determining that the function of the area to be tested is normal under the condition that the second data is consistent with the test vector, and determining that the function of the area to be tested is abnormal under the condition that the second data is inconsistent with the test vector.

Examples of steps S401-S404 may refer to steps S301-S304 in FIG. 3.

Wherein, the generated test vector aiming at all or part of the bits can be determined according to the test requirement.

For example, the area to be tested may be the 2 nd byte in the 2 nd page in the flash memory, the 2 nd byte may be determined to be the byte in which data is written according to the first data, and the first 4 bits in the byte may not be rewritten with a value (for example, both are 1) before erasing, and the last 4 bits may be rewritten with a value (for example, both are 0) before erasing, and in one possible implementation, the vector type of the test vector formed by the last 4 bits corresponding to the 2 nd byte may be determined according to the function of the test, for example, an all-0 vector, an all-1 vector, and so on.

Examples of the way in which the vector types correspond to the functions tested can be found above.

Fig. 5 is a block diagram illustrating a flash memory test apparatus according to an embodiment of the present application. The apparatus may be used in a terminal device, such as the microprocessor 100a described above in the terminal device, and as shown in fig. 5, the apparatus includes:

afirst module 501, configured to read first data from a region to be tested in a flash memory;

asecond module 502, configured to generate a test vector according to the first data;

athird module 503, configured to perform data writing operation on the flash memory according to the test vector, so that second data is stored in the to-be-tested area;

afourth module 504, configured to read the second data from the region to be tested, and determine a test result for the region to be tested according to whether the second data is consistent with the test vector.

Therefore, the types of the test vectors can be flexibly selected according to the test requirements so as to test whether the corresponding functions are normal or not.

In one possible implementation, the testing includes one or more of a short circuit test, an open circuit test, a disturb test, an address error test for the area to be tested.

In one possible implementation, each of the regions to be tested is one byte.

The embodiment of the present application further provides a terminal device, which is characterized in that the terminal device includes a flash memory controller, and the flash memory controller is configured to execute the above method.

An embodiment of the present application further provides a flash memory testing apparatus, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the above method.

Embodiments of the present application also provide a non-transitory computer-readable storage medium having computer program instructions stored thereon, where the computer program instructions, when executed by a processor, implement the above-mentioned method.

The present disclosure may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for testing a flash memory, the method comprising:

reading first data from a region to be tested of a flash memory;

generating a test vector according to the first data;

performing data writing operation on the flash memory according to the test vector to enable second data to be stored in the area to be tested;

and reading the second data from the area to be tested, and determining a test result aiming at the area to be tested according to whether the second data is consistent with the test vector.

2. The method of claim 1, wherein performing a data write operation on the flash memory according to the test vector comprises:

and under the condition of not carrying out erasing operation, carrying out data writing operation on the flash memory according to the test vector.

3. The method of claim 1, wherein generating a test vector from the first data comprises:

and under the condition that all or part of bits in the area to be tested can be rewritten with data before erasing according to the first data, generating a test vector aiming at all or part of bits.

4. The method of any of claims 1-3, wherein the test vector has a vector type corresponding to a function of the test.

5. The method of claim 4, wherein the vector types comprise one or more of all 0 vectors, all 1 vectors, checkerboard vectors, march pattern vectors, and gapping pattern vectors.

6. The method of any one of claims 1-5, wherein the testing comprises one or more of a short circuit test, an open circuit test, a disturb test, and an address error test for the area under test.

7. The method of any of claims 1-6, wherein each of said areas to be tested is one byte.

8. A flash memory test apparatus, the apparatus comprising:

the first module is used for reading first data from a to-be-tested area of the flash memory;

a second module for generating a test vector according to the first data;

the third module is used for carrying out data writing operation on the flash memory according to the test vector so that second data are stored in the area to be tested;

and the fourth module is used for reading the second data from the area to be tested and determining a test result aiming at the area to be tested according to whether the second data is consistent with the test vector.

9. A terminal device, characterized in that the terminal device comprises a flash memory controller for performing the method according to any of claims 1-7.

10. A flash memory test apparatus, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of claims 1-7.

11. A non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of any of claims 1-7.