CN113193047A - Negative capacitance field effect transistor with ferroelectric layers of different thicknesses and preparation method - Google Patents

Abstract

Translated fromChinese

本申请涉及一种不同厚度铁电层的负电容场效应晶体管及制备方法。该晶体管包括：衬底、埋氧化层、基于顶层形成的源区、基于顶层形成的漏区、基于顶层形成的全耗尽或部分耗尽的沟道、侧墙，以及源区漏区之间通过侧墙隔离的栅氧化层、负电容铁电层、金属层，其特征在于：所述负电容铁电层的厚度由源区至漏区方向不同，使得栅极不同厚度的负电容铁电层对栅极电压放大作用呈线性放大，对栅极电压放大作用具有更好的控制能力，同时不同厚度铁电层的负电容场效应晶体管在相同的栅压下具有更高的饱和区电流以及更低的亚阈值斜率，因此提升了晶体管的性能。

The present application relates to a negative capacitance field effect transistor with ferroelectric layers of different thicknesses and a preparation method thereof. The transistor includes: a substrate, a buried oxide layer, a source region formed based on the top layer, a drain region formed based on the top layer, a fully depleted or partially depleted channel formed based on the top layer, spacers, and between the source and drain regions The gate oxide layer, the negative-capacitance ferroelectric layer, and the metal layer isolated by the sidewalls are characterized in that the thickness of the negative-capacitance ferroelectric layer is different from the source region to the drain region, so that the negative-capacitance ferroelectric layers with different thicknesses of the gate are The amplification effect of the ferroelectric layer on the gate voltage is linearly amplified, and the gate voltage amplification effect is better controlled. At the same time, the negative capacitance field effect transistors of different thickness ferroelectric layers have higher saturation current and Lower subthreshold slope, thus improving transistor performance.

Description

Negative capacitance field effect transistor with ferroelectric layers of different thicknesses and preparation method

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a negative capacitance field effect transistor with ferroelectric layers of different thicknesses and a preparation method thereof.

Background

The continuous development of moore's law has led to the continuous reduction of the feature size of semiconductor devices, the continuous increase of the power density of integrated circuits, the higher and higher working temperature of chips, and the great reduction of reliability and performance. Reducing the transistor sub-threshold swing is an effective way to reduce the power supply voltage and power consumption of integrated circuits. Negative Capacitance Field Effect Transistors (NCFETs) have great potential as the latest type of low power transistors in recent years. Compared with an MOSFET, the NCFET only superposes a ferroelectric thin film material with negative capacitance effect on the traditional gate oxide, realizes the amplification of gate voltage on the premise of not changing the channel transport mechanism of the traditional field effect transistor, can reduce Sub-threshold slope (SS) to be below 60mV/dec, and does not change the driving current of the NCFET under the condition that the power supply voltage VDD is greatly reduced, thereby obviously reducing the power consumption of an integrated circuit, further reducing the size of a device and further developing the Moore's law.

In order to improve the subthreshold characteristics of transistors and to reduce static power consumption, researchers have proposed various measures. For example, the document Salahuddin S, and Datta S. use of Negative Capacitance to Provide Voltage Amplification for Low Power nanoscopic Devices [ J ]. Nano Lett.,2008,8(2): 405-. The structure is shown in fig. 1, where 1 is a source region, 2 is a channel, 3 is a drain region, 4 is a ferroelectric layer, and 5 is a gate metal layer. The structure only superposes the ferroelectric film material with negative capacitance effect on the traditional gate oxide, and can realize the subthreshold swing less than the theoretical limit value of 60mV/decade on the premise of not changing the channel transport mechanism of the traditional field effect transistor. However, compared with the conventional MOSFET, the structure has the advantages of reduced sub-threshold swing and limited static power consumption, and the improvement performance is not obvious. The document A.Sharma and K.Roy. Design Space amplification of hystersis-Free HfZrOx-Based Negative Capacitance FETs [ J ]. IEEE Electron Device Letters,2017, 38(8):1165-1167 propose a Negative Capacitance transistor structure that fully depletes silicon on insulator as shown in FIG. 2. 1 is a substrate, 2 is a buried oxide layer, 3 is a source region, 4 is a fully depleted channel, 5 is a drain region, 6 is a gate oxide layer, 7 is a ferroelectric layer, 8 is a gate metal layer, and 9 is a side wall. The FDSOI structure improves the performance of a negative capacitor transistor through an undoped fully depleted channel and improved gate control, and enables the matching result of a capacitor and a ferroelectric layer to be better. But this structure does not allow the subthreshold swing to be below the limit value of 60mV/decade, and the amplification of the gate voltage is not controllable.

Therefore, the current negative capacitance transistor structure has a limitation in improving the sub-threshold characteristics of the transistor or reducing the static power consumption, and cannot linearly control the amplification of the gate voltage, and its performance is low.

Disclosure of Invention

In view of the above, it is desirable to provide a negative capacitance field effect transistor with ferroelectric layers of different thicknesses and a method for fabricating the same, which can improve the performance of the transistor.

The transistor comprises a substrate, a buried oxide layer, a source region formed on the basis of a top layer, a drain region formed on the basis of the top layer, a fully depleted or partially depleted channel formed on the basis of the top layer, a side wall, a gate oxide layer, a negative capacitor ferroelectric layer and a metal layer, wherein the gate oxide layer, the negative capacitor ferroelectric layer and the metal layer are isolated by the side wall between the source region and the drain region, and the directions of the negative capacitor ferroelectric layer from the source region to the drain region are different.

In one embodiment, the ferroelectric material of the negative capacitance ferroelectric layer is any one of a hafnium oxide-based ferroelectric, an organic ferroelectric, a layered bismuth-based ferroelectric, a lead zirconate titanate ferroelectric, a goethite-type ferroelectric, a lithium niobate-type ferroelectric, a tungsten bronze-type ferroelectric, and a bismuth layer-structured goethite-structured ferroelectric.

In one embodiment, the thickness of the negative capacitance ferroelectric layer is gradually decreased or increased in a direction from a source region to a drain region, the number of steps is n, wherein n is more than or equal to 2.

In one embodiment, the thickness of the negative capacitance ferroelectric layer is linearly decreased or increased from the source region to the drain region.

In one embodiment, the substrate and the top layer are made of any one of silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, silicon carbide and indium phosphide.

In one embodiment, the metal layer is made of any one of aluminum, copper, silver, gold, polysilicon, titanium nitride, or tantalum nitride.

In one embodiment, the sidewall spacer is made of any one of silicon nitride, silicon oxynitride and silicon oxycarbide.

A method for preparing a negative capacitance field effect transistor with ferroelectric layers of different thicknesses comprises the following steps:

forming a three-layer structure with a substrate, a buried oxide layer and a top layer by using an intelligent stripping technology;

depositing a gate oxide layer on the top layer, and depositing polycrystalline silicon on the gate oxide layer to serve as a virtual gate;

forming a side wall through deposition and etching processes, forming a lifting region on the top layer through a selective epitaxial process, forming a source region and a drain region on the lifting region on two sides through an ion implantation process, and forming a channel in a region below the gate oxide layer on the top layer;

removing the dummy gate by wet etching;

forming a ferroelectric layer on the gate oxide layer by a deposition process;

protecting the deposited ferroelectric material in the highest step area of the ferroelectric layer by using a mask plate, and removing the ferroelectric material which does not belong to the highest step area in the ferroelectric layer by an etching process to form a negative capacitance ferroelectric layer with the thickness in step change;

removing the mask plate through an etching process;

and preparing the metal layer by utilizing a physical vapor deposition process.

The negative capacitance field effect transistor with the ferroelectric layers of different thicknesses comprises a substrate, a buried oxide layer, a source region formed on the basis of a top layer, a drain region formed on the basis of the top layer, a fully depleted or partially depleted channel formed on the basis of the top layer, a side wall, a gate oxide layer, a negative capacitance ferroelectric layer and a metal layer, wherein the gate oxide layer, the negative capacitance ferroelectric layer and the metal layer are isolated by the side wall between the source region and the drain region, the direction from the source region to the drain region is different through the thickness of the negative capacitance ferroelectric layer, so that the negative capacitance ferroelectric layers with different thicknesses of a grid electrode are linearly amplified to the grid electrode voltage amplification effect, the control capability on the grid electrode voltage amplification effect is better, meanwhile, the negative capacitance field effect transistors with the ferroelectric layers of different thicknesses have higher saturation region current and lower subthreshold slope under the same grid voltage, and the performance of the transistor is improved.

Drawings

Fig. 1 is a schematic cross-sectional structure of a negative-capacitance transistor used indocument 1 in the related art;

fig. 2 is a schematic cross-sectional structure diagram of a double-gate negative-capacitance transistor adopted indocument 2 in the background art;

FIG. 3 is a schematic cross-sectional view of an embodiment of a negative-capacitance field-effect transistor with ferroelectric layers of different thicknesses;

FIG. 4 is a schematic cross-sectional view of another embodiment of a negative-capacitance FET with ferroelectric layers of different thicknesses;

FIG. 5 is a schematic diagram illustrating the voltage amplification effect of the negative capacitor ferroelectric layer of the negative capacitor field effect transistor with different ferroelectric layers of different thicknesses according to the present application compared with the voltage amplification effect of the ferroelectric layer of the conventional structure;

FIG. 6 is a schematic diagram of the transfer characteristics of the negative-capacitance field effect transistor of the present application with different thicknesses of the ferroelectric layer compared to a conventional structure;

FIG. 7 is a schematic cross-sectional view of the device instep 2 of the method for fabricating a negative-capacitance field-effect transistor with ferroelectric layers of different thicknesses according to an embodiment;

FIG. 8 is a schematic cross-sectional view of the device ofstep 3 in the method for fabricating a negative-capacitance field-effect transistor with ferroelectric layers of different thicknesses according to an embodiment;

FIG. 9 is a schematic cross-sectional view of the device ofstep 4 in the method for fabricating a negative-capacitance field-effect transistor with ferroelectric layers of different thicknesses according to an embodiment;

FIG. 10 is a schematic cross-sectional view of the device ofstep 5 in the method for fabricating a negative-capacitance field-effect transistor with ferroelectric layers of different thicknesses in one embodiment;

FIG. 11 is a schematic cross-sectional view of the device ofstep 6 in the method for fabricating a negative-capacitance field-effect transistor with ferroelectric layers of different thicknesses in one embodiment;

FIG. 12 is a schematic cross-sectional view of the device ofstep 7 in the method for fabricating a negative-capacitance field-effect transistor with ferroelectric layers of different thicknesses in one embodiment;

fig. 13 is a schematic cross-sectional structure diagram of the device instep 8 of the method for manufacturing a negative capacitance field effect transistor with ferroelectric layers of different thicknesses in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In one embodiment, as shown in fig. 3 and 4, a negative capacitance field effect transistor with ferroelectric layers of different thicknesses is provided, which includes asubstrate 1, a buriedoxide layer 2, asource region 4 formed based on a top layer, adrain region 5 formed based on a top layer, a fully depleted or partially depletedchannel 3 formed based on a top layer, asidewall 9, and agate oxide layer 6, a negative capacitanceferroelectric layer 7 and ametal layer 8 which are isolated between thesource region 4 and thedrain region 5 by thesidewall 9, wherein the thickness of the negative capacitanceferroelectric layer 7 is different from the source region to the drain region.

Thesubstrate 1, the buriedoxide layer 2, the top layer, thegate oxide layer 6, the negative capacitorferroelectric layer 7 and themetal layer 8 are sequentially overlapped from bottom to top, a fully depleted or partially depletedchannel 3 is formed on the top layer below thegate oxide layer 6, the top layers on two sides of thechannel 3 are subjected to a selective epitaxial process to form lifting areas, and asource area 4 and adrain area 5 are formed in the lifting areas on two sides by an ion implantation process.

In one embodiment, the thickness of the negative capacitance ferroelectric layer is gradually decreased or increased in a direction from the source region to the drain region, the number of steps is n, wherein n is more than or equal to 2.

As shown in fig. 3, the thickness of the negative capacitor ferroelectric layer increases stepwise from the source region to the drain region, and the number of steps is 2.

In one embodiment, the thickness of the negative capacitance ferroelectric layer is linearly decreased or increased from the source region to the drain region.

As shown in fig. 4, the thickness of the negative capacitor ferroelectric layer increases linearly from the source region to the drain region.

Theside walls 9 are used for controlling the grid electrode of the negative capacitance field effect transistor with the ferroelectric layers with different thicknesses to be electrically isolated from the source electrode and the drain electrode. Thegate oxide layer 6 is provided with ferroelectric layers with different thicknesses and negative capacitance properties, an external electric field enables the ferroelectric layers with different thicknesses to generate polarization, the negative capacitanceferroelectric layer 7 with the thickness in a step change or linear change is used for adjusting the voltage amplification effect, and the gate voltage can be linearly amplified, so that the control capability of the gate on a channel is improved.

In one embodiment, the ferroelectric material of the negative capacitanceferroelectric layer 7 is any one of a hafnium oxide-based ferroelectric, an organic ferroelectric, a layered bismuth-based ferroelectric, a lead zirconate titanate ferroelectric, a goethite-type ferroelectric, a lithium niobate-type ferroelectric, a tungsten bronze-type ferroelectric, and a bismuth layer-like goethite-structure ferroelectric.

In one embodiment, thesubstrate 1 and the top layer are made of any one of silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, silicon carbide, and indium phosphide.

In one embodiment, themetal layer 8 is made of any one of aluminum, copper, silver, gold, polysilicon, titanium nitride, or tantalum nitride.

In one embodiment, the material used for thesidewall spacers 9 is any one of silicon nitride, silicon oxynitride and silicon oxycarbide.

Comparing the voltage amplification effect of the ferroelectric layer of the conventional structure shown in (a) of fig. 5 with the voltage amplification effect of the negative capacitor ferroelectric layer 7 of the negative capacitor field effect transistor of the present application with different thicknesses of the ferroelectric layer shown in (b) of fig. 5, it can be seen from the N-type electrical characteristics exhibited by the negative capacitor field effect transistor of the present application based on the negative capacitor characteristics of different ferroelectric materials that the voltage amplification effect is improved to amplify the gate voltage linearly, the negative capacitor field effect transistor of the present application with different thicknesses of the ferroelectric layer shown in fig. 6 is a schematic diagram of the transfer characteristic improvement of the negative capacitor transistor of the conventional structure as compared with the negative capacitor transistor of the conventional structure, the curve of the conventional structure shown in fig. 5 is a transfer characteristic improvement curve of the negative capacitor transistor of the conventional structure, the curve of the thickness-variable ferroelectric layer structure shown in fig. 5 is a transfer characteristic improvement curve of the negative capacitor field effect transistor of the different thicknesses of the present application, the negative capacitance field effect transistor with the ferroelectric layers of different thicknesses based on the negative capacitance characteristics of different ferroelectric materials improves the transfer characteristics and reduces the subthreshold swing to be below a theoretical limit value of 60 mV/dec.

The negative capacitance field effect transistor with the ferroelectric layers with different thicknesses comprises a substrate, a buried oxide layer, a source region formed on the basis of a top layer, a drain region formed on the basis of the top layer, a channel formed on the basis of the top layer, a side wall, a gate oxide layer, a negative capacitanceferroelectric layer 7 and a metal layer, wherein the gate oxide layer, the negative capacitanceferroelectric layer 7 and the metal layer are isolated by the side wall between the source region and the drain region, the directions of the source region and the drain region are different through the thickness of the negative capacitanceferroelectric layer 7, so that the negative capacitanceferroelectric layers 7 with different thicknesses of a grid electrode are linearly amplified to the grid electrode voltage amplification effect, the grid electrode voltage amplification effect is better controlled, meanwhile, the negative capacitance field effect transistors with the ferroelectric layers with different thicknesses have higher saturation region current and lower subthreshold slope under the same grid voltage, and the subthreshold slope can be lower than a theoretical limit value of 60mV/dec, and therefore the performance of the transistor is improved.

A method for preparing a negative capacitance field effect transistor with ferroelectric layers of different thicknesses comprises the following steps:

step 1: a three-layer structure having asubstrate 1, a buriedoxide layer 2 and atop layer 10 is formed using smart-cut techniques.

Step 2: agate oxide layer 6 is deposited on thetop layer 10 and polysilicon is deposited on thegate oxide layer 6 as adummy gate 11, as shown in the schematic cross-sectional structure of the step-2 device shown in fig. 7.

And step 3: forming aside wall 9 through deposition and etching processes, performing a selective epitaxial process on thetop layer 10 to form a raised region, forming asource region 4 and adrain region 5 in the raised region on two sides by using an ion implantation process, and forming achannel 3 in a region below thegate oxide layer 6 of thetop layer 10, as shown in a schematic cross-sectional structure diagram of the device instep 3 shown in fig. 8.

And 4, step 4: thedummy gate 11 is removed by wet etching, as shown in fig. 9, which is a schematic cross-sectional structure diagram of the step-4 device.

And 5: aferroelectric layer 12 is formed on thegate oxide layer 6 by a deposition process, as shown in fig. 10, which is a schematic cross-sectional structure of the device ofstep 5.

Step 6: the deposited ferroelectric material in the highest step region of theferroelectric layer 12 is protected by using amask 13, and the ferroelectric material in theferroelectric layer 12, which does not belong to the highest step region, is removed by an etching process to form a negative capacitanceferroelectric layer 7 with a step-change thickness, as shown in the schematic cross-sectional structure diagram of the device instep 6 shown in fig. 11.

And 7: and removing themask plate 13 through an etching process, as shown in a schematic cross-sectional structure diagram of the device in thestep 7 shown in fig. 12.

And 8: themetal layer 8 is prepared by physical vapor deposition, as shown in fig. 13, which is a schematic cross-sectional structure diagram of the step-8 device.

In this case, an SOI substrate having a three-layer structure of thesubstrate 1, the buriedoxide layer 2, and thetop layer 10 may be directly used, and the preparation may be performed on thetop layer 10 of the SOI substrate. After the negative capacitance field effect transistors with the ferroelectric layers with different thicknesses are prepared, the grid electrodes, the drain electrodes and the source electrodes of the negative capacitance field effect transistors with the ferroelectric layers with different thicknesses are led out through the tungsten plugs; and then using chemical mechanical planarization to planarize the deposition plane.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (8)

Translated fromChinese

1.一种不同厚度铁电层的负电容场效应晶体管，所述晶体管包括衬底、埋氧化层、基于顶层形成的源区、基于顶层形成的漏区、基于顶层形成的全耗尽或部分耗尽的沟道、侧墙，以及源区漏区之间通过侧墙隔离的栅氧化层、负电容铁电层、金属层，其特征在于：1. A negative capacitance field effect transistor with ferroelectric layers of different thicknesses, the transistor comprising a substrate, a buried oxide layer, a source region formed based on a top layer, a drain region formed based on the top layer, a fully depleted or partially depleted region formed based on the top layer The depleted channel, the spacer, and the gate oxide layer, the negative capacitance ferroelectric layer, and the metal layer isolated by the spacer between the source and drain regions are characterized by:所述负电容铁电层的厚度由所述源区至所述漏区方向不同。The thickness of the negative capacitance ferroelectric layer is different from the source region to the drain region.2.根据权利要求1所述的晶体管，其特征在于，所述负电容铁电层的铁电材料为氧化铪基铁电体、有机铁电材料、层状铋系铁电材料、锆钛酸铅铁电材料、钙铁矿型铁电体、铌酸锂型铁电体、钨青铜型铁电体和铋层状钙铁矿结构铁电体材料中的任意一种。2 . The transistor according to claim 1 , wherein the ferroelectric material of the negative capacitance ferroelectric layer is a hafnium oxide-based ferroelectric material, an organic ferroelectric material, a layered bismuth-based ferroelectric material, and zirconate titanate. 3 . Any one of lead ferroelectric materials, perovskite-type ferroelectric materials, lithium niobate-type ferroelectric materials, tungsten bronze-type ferroelectric materials and bismuth layered perovskite-structured ferroelectric materials.3.根据权利要求1所述的晶体管，其特征在于，所述负电容铁电层的厚度由源区至漏区方向阶梯递减或递增，阶梯的数量为n，其中n≥2。3 . The transistor according to claim 1 , wherein the thickness of the negative capacitance ferroelectric layer decreases or increases stepwise from the source region to the drain region, and the number of steps is n, wherein n≧2. 4 .4.根据权利要求1所述的晶体管，其特征在于，所述负电容铁电层的厚度由源区至漏区方向线性递减或递增。4 . The transistor according to claim 1 , wherein the thickness of the negative capacitance ferroelectric layer linearly decreases or increases from the source region to the drain region. 5 .5.根据权利要求1所述的晶体管，其特征在于，所述衬底和顶层采用的材料为硅、锗、锗硅、砷化镓、氮化镓、碳化硅和磷化铟中的任意一种。5 . The transistor according to claim 1 , wherein the material used for the substrate and the top layer is any one of silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, silicon carbide and indium phosphide. 6 . kind.6.根据权利要求1所述的晶体管，其特征在于，所述金属层采用的材料为铝、铜、银、金、多晶硅、氮化钛或氮化钽中的任意一种。6 . The transistor according to claim 1 , wherein the material used for the metal layer is any one of aluminum, copper, silver, gold, polysilicon, titanium nitride or tantalum nitride. 7 .7.根据权利要求1所述的晶体管，其特征在于，所述侧墙采用的材料为氮化硅、氮氧化硅和碳氧化硅中的任意一种。7 . The transistor according to claim 1 , wherein the material used for the sidewall is any one of silicon nitride, silicon oxynitride and silicon oxycarbide. 8 .8.一种不同厚度铁电层的负电容场效应晶体管的制备方法，其特征在于，包括以下步骤：8. a preparation method of the negative capacitance field effect transistor of a ferroelectric layer of different thickness, is characterized in that, comprises the following steps:利用智能剥离技术形成具有衬底、埋氧化层和顶层的三层结构；Using intelligent lift-off technology to form a three-layer structure with a substrate, a buried oxide layer and a top layer;在所述顶层上沉积栅氧化层，并在所述栅氧化层上沉积多晶硅作为虚拟栅；depositing a gate oxide layer on the top layer, and depositing polysilicon as a dummy gate on the gate oxide layer;通过淀积和刻蚀工艺形成侧墙，并在所述顶层上进行选择性外延工艺形成抬升区域，并利用离子注入工艺在两侧抬升区域形成源区和漏区，所述顶层的所述栅氧化层下方区域形成沟道；Sidewall spacers are formed through deposition and etching processes, and a selective epitaxy process is performed on the top layer to form a raised region, and an ion implantation process is used to form source and drain regions on the raised regions on both sides. The area under the oxide layer forms a channel;通过湿法刻蚀去除虚拟栅；Remove the dummy gate by wet etching;通过沉积工艺在所述栅氧化层上形成铁电层；forming a ferroelectric layer on the gate oxide layer by a deposition process;利用掩膜板保护所述铁电层的最高级阶梯区域的沉积的铁电材料，通过刻蚀工艺将所述铁电层中不属于所述最高级阶梯区域的铁电材料去除，形成厚度呈阶梯变化的负电容铁电层；A mask is used to protect the deposited ferroelectric material in the uppermost step region of the ferroelectric layer, and the ferroelectric material in the ferroelectric layer that does not belong to the uppermost step region is removed by an etching process to form a thickness of Step-change negative capacitance ferroelectric layer;通过刻蚀工艺去除所述掩膜板；removing the mask by an etching process;利用物理气相淀积工艺制备金属层。The metal layer is prepared by a physical vapor deposition process.

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