技术领域Technical field
本发明涉及显示技术领域，更具体地，涉及一种阵列基板、显示面板和显示装置。The present invention relates to the field of display technology, and more specifically, to an array substrate, a display panel and a display device.
背景技术Background technique
现有技术中，显示面板的制程复杂，在制程中容易受到静电的影响，而大量的静电电荷聚集容易导致面板中扫描线末端击伤、边缘像素单元炸伤等问题，导致显示面板显示区内的边缘区域发生短路、点类不良等缺陷，影响显示面板的显示效果和使用寿命。因此，如何提高显示面板边缘区域抗静电能力这一问题亟待解决。In the existing technology, the manufacturing process of display panels is complex and is easily affected by static electricity during the manufacturing process. The accumulation of a large amount of electrostatic charges can easily lead to problems such as damage to the ends of scan lines in the panel, damage to edge pixel units, etc., causing damage to the display area of the display panel. Defects such as short circuits and defective dots occur in the edge area, affecting the display effect and service life of the display panel. Therefore, the problem of how to improve the antistatic ability of the edge area of the display panel needs to be solved urgently.
发明内容Contents of the invention
有鉴于此，本发明提供了一种阵列基板、显示面板和显示装置，用以改善显示面板边缘区域抗静电能力如何提高的问题。In view of this, the present invention provides an array substrate, a display panel and a display device to improve the problem of how to improve the antistatic capability of the edge area of the display panel.
第一方面，本申请提供一种阵列基板，包括显示区和至少部分围绕所述显示区的非显示区；所述阵列基板包括衬底；In a first aspect, the present application provides an array substrate, including a display area and a non-display area at least partially surrounding the display area; the array substrate includes a substrate;
还包括多条沿第一方向延伸、且沿第二方向排布的扫描线，所述第一方向和所述第二方向相交；It also includes a plurality of scan lines extending along a first direction and arranged along a second direction, where the first direction and the second direction intersect;
所述非显示区包括多个导电部，所述导电部用于释放与其具有交叠面积的所述扫描线上的静电荷；The non-display area includes a plurality of conductive parts, the conductive parts are used to release static charges on the scan lines having an overlapping area therewith;
沿垂直于所述衬底所在平面的方向，任一所述导电部在所述衬底的正投影和与其对应设置的所述扫描线在所述衬底的正投影之间的交叠面积为S1；Along the direction perpendicular to the plane of the substrate, the overlapping area between the orthographic projection of any conductive part on the substrate and the orthographic projection of the corresponding scan line on the substrate is S1;
所述阵列基板还包括多个在所述显示区内阵列排布的有源层单元，沿垂直于所述衬底所在平面的方向，任一所述有源层单元在所述衬底的正投影和与其对应设置的所述扫描线在所述衬底的正投影之间的交叠面积为S2；The array substrate also includes a plurality of active layer units arranged in an array in the display area. In a direction perpendicular to the plane of the substrate, any of the active layer units is located directly in front of the substrate. The overlapping area between the orthographic projection of the substrate and the corresponding scan line is S2;
其中，至少一个S1＞S2。Among them, at least one S1>S2.
第二方面，本申请提供了一种显示面板，所述显示面板包括所述阵列基板。In a second aspect, the present application provides a display panel, which includes the array substrate.
第三方面，本申请提供了一种显示装置，所述显示装置包括所述显示面板。In a third aspect, the present application provides a display device, which includes the display panel.
与现有技术相比，本发明提供的一种阵列基板、显示面板和显示装置，至少实现了如下的有益效果：Compared with the existing technology, the array substrate, display panel and display device provided by the present invention at least achieve the following beneficial effects:
本申请提供了一种阵列基板、显示面板和显示装置，通过在阵列基板的非显示区增设多个导电部，且设置导电部在衬底的正投影和与其对应设置的扫描线在衬底的正投影具有交叠面积，通过导电部释放与其具有交叠面积的扫描线上的静电荷，避免静电荷在扫描线末端的累积，从而避免扫描线末端被静电击伤、边缘像素单元炸伤的问题，大幅度提高显示面板的抗静电能力，提高了相应显示装置的良品率。The present application provides an array substrate, a display panel and a display device, by adding a plurality of conductive parts in the non-display area of the array substrate, and arranging the orthographic projection of the conductive parts on the substrate and the corresponding scan lines on the substrate. The orthographic projection has an overlapping area, and the conductive part releases the electrostatic charge on the scanning line with the overlapping area to avoid the accumulation of electrostatic charge at the end of the scanning line, thereby avoiding the end of the scanning line being injured by static electricity and the edge pixel unit being damaged. It greatly improves the anti-static ability of the display panel and improves the yield rate of the corresponding display device.
当然，实施本发明的任一产品必不特定需要同时达到以上所述的所有技术效果。Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned technical effects at the same time.
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。Other features of the invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings.
附图说明Description of drawings
被结合在说明书中并构成说明书的一部分的附图示出了本发明的实施例，并且连同其说明一起用于解释本发明的原理。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
图1所示为本申请实施例所提供的阵列基板的一种膜层结构示意图；Figure 1 shows a schematic diagram of a film structure of an array substrate provided by an embodiment of the present application;
图2所示为本申请实施例所提供的图1中A区域的一种俯视图；Figure 2 shows a top view of area A in Figure 1 provided by an embodiment of the present application;
图3所示为本申请实施例所提供的图1的一种俯视图；Figure 3 shows a top view of Figure 1 provided by the embodiment of the present application;
图4所示为本申请实施例所提供的图1中A区域的另一种俯视图；Figure 4 shows another top view of area A in Figure 1 provided by an embodiment of the present application;
图5所示为本申请实施例所提供的图1中A区域的另一种俯视图；Figure 5 shows another top view of area A in Figure 1 provided by an embodiment of the present application;
图6所示为本申请实施例所提供的图1中A区域的另一种俯视图；Figure 6 shows another top view of area A in Figure 1 provided by an embodiment of the present application;
图7所示为本申请实施例所提供的图1中A区域的另一种俯视图；Figure 7 shows another top view of area A in Figure 1 provided by the embodiment of the present application;
图8所示为本申请实施例所提供的图7中扫描线的一种BB’截面图；Figure 8 shows a BB’ cross-sectional view of the scanning line in Figure 7 provided by the embodiment of the present application;
图9所示为本申请实施例所提供的图7中金属线的一种CC’截面图；Figure 9 shows a CC' cross-sectional view of the metal wire in Figure 7 provided by the embodiment of the present application;
图10所示为本申请实施例所提供的图1中A区域的另一种俯视图；Figure 10 shows another top view of area A in Figure 1 provided by an embodiment of the present application;
图11所示为本申请实施例所提供的图1中A区域的另一种俯视图；Figure 11 shows another top view of area A in Figure 1 provided by an embodiment of the present application;
图12所示为本申请实施例所提供的阵列基板的另一种膜层结构示意图；Figure 12 shows a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application;
图13所示为本申请实施例所提供的阵列基板的再一种膜层结构示意图；Figure 13 shows a schematic diagram of another film structure of the array substrate provided by the embodiment of the present application;
图14所示为本申请实施例所提供的阵列基板中导电部复用有源层单元形成时的一种截面示意图；Figure 14 shows a schematic cross-sectional view of the conductive portion in the array substrate provided by the embodiment of the present application when multiple active layer units are formed;
图15所示为本申请实施例所提供的阵列基板中导电部复用有源层单元形成时的另一种截面示意图；Figure 15 shows another cross-sectional schematic diagram when the conductive portion in the array substrate is formed by multiplexing active layer units according to the embodiment of the present application;
图16所示为本申请实施例所提供的显示面板的一种示意图；Figure 16 shows a schematic diagram of a display panel provided by an embodiment of the present application;
图17所示为本申请实施例提供的显示装置的一种示意图。Figure 17 shows a schematic diagram of a display device provided by an embodiment of the present application.
具体实施方式Detailed ways
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values set forth in these examples do not limit the scope of the invention unless otherwise specifically stated.
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application or uses.
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered a part of the specification.
在这里示出和讨论的所有例子中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它例子可以具有不同的值。In all examples shown and discussed herein, any specific values are to be construed as illustrative only and not as limiting. Accordingly, other examples of the exemplary embodiments may have different values.
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。It should be noted that similar reference numerals and letters refer to similar items in the following figures, so that once an item is defined in one figure, it does not need further discussion in subsequent figures.
现有技术中，显示面板的制程复杂，在制程中容易受到静电的影响，而大量的静电电荷聚集容易导致面板中扫描线末端击伤、边缘像素单元炸伤等问题，导致显示面板显示区内的边缘区域发生短路、点类不良等缺陷，影响显示面板的显示效果和使用寿命。因此，如何提高显示面板边缘区域抗静电能力这一问题亟待解决。In the existing technology, the manufacturing process of display panels is complex and is easily affected by static electricity during the manufacturing process. The accumulation of a large amount of electrostatic charges can easily lead to problems such as damage to the ends of scan lines in the panel, damage to edge pixel units, etc., causing damage to the display area of the display panel. Defects such as short circuits and defective dots occur in the edge area, affecting the display effect and service life of the display panel. Therefore, the problem of how to improve the antistatic ability of the edge area of the display panel needs to be solved urgently.
有鉴于此，本发明提供了一种阵列基板、显示面板和显示装置，用以改善显示面板边缘区域抗静电能力如何提高的问题。In view of this, the present invention provides an array substrate, a display panel and a display device to improve the problem of how to improve the antistatic capability of the edge area of the display panel.
图1所示为本申请实施例所提供的阵列基板的一种膜层结构示意图，图2所示为本申请实施例所提供的图1中A区域的一种俯视图，请参照图1和图2，本申请提供了一种阵列基板100，包括显示区10和至少部分围绕显示区10的非显示区20；阵列基板100包括衬底01；Figure 1 shows a schematic diagram of a film structure of an array substrate provided by an embodiment of the present application. Figure 2 shows a top view of area A in Figure 1 provided by an embodiment of the present application. Please refer to Figure 1 and Figure 2. The present application provides an array substrate 100, including a display area 10 and a non-display area 20 at least partially surrounding the display area 10; the array substrate 100 includes a substrate 01;
还包括多条沿第一方向延伸、且沿第二方向排布的扫描线11，第一方向和第二方向相交；It also includes a plurality of scan lines 11 extending along the first direction and arranged along the second direction, where the first direction and the second direction intersect;
非显示区20包括多个导电部12，导电部12用于释放与其具有交叠面积的扫描线11上的静电荷；The non-display area 20 includes a plurality of conductive parts 12, and the conductive parts 12 are used to release static charges on the scan lines 11 with overlapping areas;
沿垂直于衬底01所在平面的方向，任一导电部12在衬底01的正投影和与其对应设置的扫描线11在衬底01的正投影之间的交叠面积为S1；Along the direction perpendicular to the plane of the substrate 01, the overlapping area between the orthographic projection of any conductive part 12 on the substrate 01 and the orthographic projection of the corresponding scan line 11 on the substrate 01 is S1;
阵列基板100还包括多个在显示区10内阵列排布的有源层单元13，沿垂直于衬底01所在平面的方向，任一有源层单元13在衬底01的正投影和与其对应设置的扫描线11在衬底01的正投影之间的交叠面积为S2；The array substrate 100 also includes a plurality of active layer units 13 arranged in an array in the display area 10. Along the direction perpendicular to the plane where the substrate 01 is located, the orthographic projection of any active layer unit 13 on the substrate 01 and its corresponding The overlapping area between the set scan line 11 and the orthographic projection of the substrate 01 is S2;
其中，至少一个S1＞S2。Among them, at least one S1>S2.
具体地，请继续参照图1和图2，本申请提供了一种阵列基板100，该阵列基板100包括显示区10和非显示区20，本申请提供的一种实施例为，非显示区20围绕显示区10设置；但本申请并不以此为限，也可为非显示区20至少部分围绕显示区10设置等。本申请所提供的阵列基板100中包括多条扫描线11，任一条扫描线11均沿第一方向延伸、且沿第二方向排布，其中第一方向和第二方向相交，具体可为第一方向和第二方向垂直。Specifically, please continue to refer to Figures 1 and 2. This application provides an array substrate 100. The array substrate 100 includes a display area 10 and a non-display area 20. An embodiment provided by this application is that the non-display area 20 The non-display area 20 can also be arranged around the display area 10 at least partially. However, the application is not limited to this. The non-display area 20 can also be arranged around the display area 10 at least partially. The array substrate 100 provided by the present application includes a plurality of scan lines 11. Each scan line 11 extends along the first direction and is arranged along the second direction, where the first direction and the second direction intersect. Specifically, the first direction and the second direction intersect. One direction is perpendicular to the second direction.
本申请所提供的阵列基板100中还包括多个导电部12，该导电部12位于非显示区20设置；阵列基板100包括衬底01，沿垂直于衬底01所在平面的方向，阵列基板100中所设置的任一导电部12在衬底01的正投影和与其对应设置的扫描线11在衬底01的正投影具有交叠面积，以使得导电部12和与其对应的扫描线11之间可进行静电荷的传输，即非显示区20中增设的导电部12用于释放与其具有交叠面积的扫描线11上的静电荷。The array substrate 100 provided in this application also includes a plurality of conductive parts 12, which are located in the non-display area 20; the array substrate 100 includes a substrate 01, and in a direction perpendicular to the plane of the substrate 01, the array substrate 100 The orthographic projection of any conductive part 12 provided in the substrate 01 and the orthographic projection of the corresponding scan line 11 on the substrate 01 have an overlapping area, so that there is an overlapping area between the conductive part 12 and the corresponding scan line 11 The electrostatic charge can be transferred, that is, the conductive portion 12 added in the non-display area 20 is used to release the electrostatic charge on the scan line 11 with an overlapping area.
需要说明的是，本申请并不限定导电部12和与其对应设置的扫描线11之间是否具有电连接关系。本申请通过导电部12消除扫描线11上静电的原理是基于正负电荷在电场中产生定向运动，即正电荷在电场中将从电势高处向电势低处移动，而负电荷在电场中将从低电势向高电势移动的原理设计实现的。It should be noted that this application does not limit whether there is an electrical connection relationship between the conductive portion 12 and the scanning line 11 provided corresponding thereto. The principle of this application to eliminate static electricity on the scan line 11 through the conductive part 12 is based on the directional movement of positive and negative charges in the electric field, that is, the positive charges will move from a high potential to a low potential in the electric field, while the negative charges will move in the electric field. It is designed based on the principle of moving from low potential to high potential.
本申请提供一种可选择的实施例为，导电部12和与其对应设置的扫描线11之间具有绝缘层，使得导电部12和扫描线11不具有电连接关系时，可通过导电部12、扫描线11之间存在的电势差驱使扫描线11上所存在的静电荷向导电部12移动，也即扫描线11上的静电荷在该电势差的驱使下，击穿绝缘层后到达相对应的导电部12，从而通过导电部12收集扫描线11上的多余的静电荷，实现扫描线11上残余静电荷的释放，避免静电荷在扫描线11末端的累积，来达到避免扫描线11末端被静电击伤、边缘像素单元炸伤的问题；有利于提高阵列基板100的抗静电能力，提高了阵列基板100的良品率。This application provides an optional embodiment that there is an insulating layer between the conductive part 12 and the corresponding scan line 11, so that when the conductive part 12 and the scan line 11 do not have an electrical connection relationship, they can be connected through the conductive part 12, The potential difference between the scan lines 11 drives the electrostatic charges existing on the scan lines 11 to move toward the conductive portion 12 . That is, the electrostatic charges on the scan lines 11 are driven by the potential difference to break down the insulating layer and reach the corresponding conductive portion. part 12, thereby collecting the excess static charge on the scan line 11 through the conductive part 12, realizing the release of the residual electrostatic charge on the scan line 11, and avoiding the accumulation of electrostatic charge at the end of the scan line 11, so as to avoid the end of the scan line 11 being electrostatically charged The problem of damage to the edge pixel units due to impact damage; it is beneficial to improve the anti-static ability of the array substrate 100 and improve the yield rate of the array substrate 100.
需要说明的是，当导电部12和扫描线11之间如果存在绝缘层时，绝缘层内部本身存在有电荷，但是由于正、负电荷的电量平衡，使得物体本身并不对外放电。但是，当绝缘层的两端(具体为扫描线11和导电部12)存在电势差时，即是形成电场时，施加给绝缘层对应区域一个电场力，电场力驱使绝缘层中的正、负电荷可以在电势差两端(具体为扫描线11和导电部12)形成通路，从而形成电荷的定向移动。也即，通过绝缘层中形成的通路实现扫描线11上静电荷向导电部12的移动。It should be noted that when there is an insulating layer between the conductive part 12 and the scanning line 11, there is charge inside the insulating layer itself, but due to the balance of positive and negative charges, the object itself does not discharge to the outside. However, when there is a potential difference between the two ends of the insulating layer (specifically, the scanning line 11 and the conductive portion 12), that is, when an electric field is formed, an electric field force is applied to the corresponding area of the insulating layer, and the electric field force drives the positive and negative charges in the insulating layer. A path can be formed at both ends of the potential difference (specifically, the scanning line 11 and the conductive portion 12), thereby forming a directional movement of charges. That is, the movement of static charges on the scanning line 11 to the conductive portion 12 is achieved through the path formed in the insulating layer.
此外，本申请提供的阵列基板100的显示区10内，还包括多个阵列排布的有源层单元13，沿垂直于衬底01所在平面的方向，本申请设置非显示区20中任一导电部12在衬底01的正投影和与其对应设置的扫描线11在衬底01的正投影之间的交叠面积为S1，显示区10内任一有源层单元13在衬底01的正投影和与其对应设置的扫描线11在衬底01的正投影之间的交叠面积为S2，本申请提供一种可选的方式为，阵列基板100中至少存在一个S1＞S2；即，沿垂直于衬底01所在平面的方向，设置非显示区20中导电部12与扫描线11的交叠面积S1大于显示区10中有源层单元13与扫描线11的交叠面积S2；设置与扫描线11交叠面积较大的导电部12，以使得导电部12对于扫描线11上所存在静电荷的收集能力更强，且在每条扫描线11的末端均设置对应的导电部12，可使得每条扫描线11均受到保护，提高导电部12对每条扫描线11上残余静电荷的释放效果，从而有利于提高该阵列基板100的良品率。In addition, the display area 10 of the array substrate 100 provided by this application also includes a plurality of active layer units 13 arranged in an array. Along the direction perpendicular to the plane where the substrate 01 is located, this application sets any one of the non-display areas 20 The overlapping area between the orthographic projection of the conductive portion 12 on the substrate 01 and the orthographic projection of the corresponding scan line 11 on the substrate 01 is S1. Any active layer unit 13 in the display area 10 is on the substrate 01 The overlapping area between the orthographic projection and the corresponding scan line 11 on the orthographic projection of the substrate 01 is S2. This application provides an optional method that there is at least one S1>S2 in the array substrate 100; that is, Along the direction perpendicular to the plane of the substrate 01, it is set that the overlapping area S1 of the conductive part 12 and the scanning line 11 in the non-display area 20 is larger than the overlapping area S2 of the active layer unit 13 and the scanning line 11 in the display area 10; it is set The conductive portion 12 has a larger overlapping area with the scan line 11 so that the conductive portion 12 has a stronger ability to collect electrostatic charges existing on the scan line 11 , and a corresponding conductive portion 12 is provided at the end of each scan line 11 , each scan line 11 can be protected, and the release effect of the conductive portion 12 on the residual electrostatic charge on each scan line 11 can be improved, thereby helping to improve the yield rate of the array substrate 100 .
图3所示为本申请实施例所提供的图1的一种俯视图，请参照图1和图3，可选地，任一条扫描线11包括沿第一方向相对的第一端111和第二端112；Figure 3 shows a top view of Figure 1 provided by an embodiment of the present application. Please refer to Figures 1 and 3. Optionally, any scan line 11 includes a first end 111 and a second end 111 opposite in the first direction. end112;
沿垂直于衬底01所在平面的方向，至少1个导电部12在衬底01的正投影与第一端111在衬底01的正投影至少部分交叠，且至少1个导电部12在衬底01的正投影与第二端112在衬底01的正投影至少部分交叠。Along the direction perpendicular to the plane of the substrate 01 , the orthographic projection of the at least one conductive part 12 on the substrate 01 at least partially overlaps with the orthographic projection of the first end 111 on the substrate 01 , and at least one conductive part 12 is on the substrate 01 . The orthographic projection of the base 01 and the orthographic projection of the second end 112 on the substrate 01 at least partially overlap.
具体地，阵列基板100中设置的扫描线11均沿第一方向延伸、且沿第二方向排布，任一条扫描线11均包括沿第一方向相对的第一端111和第二端112，换句话说，任一条扫描线11均可延伸至显示区10在第一方向上两侧的非显示区20中。Specifically, the scan lines 11 provided in the array substrate 100 all extend along the first direction and are arranged along the second direction. Each scan line 11 includes a first end 111 and a second end 112 opposite along the first direction. In other words, any scan line 11 can extend into the non-display areas 20 on both sides of the display area 10 in the first direction.
设置于非显示区20中的多个导电部12和扫描线11之间存在的一种位置关系为，沿垂直于衬底01所在平面的方向，同一条扫描线11的第一端111在衬底01的正投影和导电部12在衬底01的正投影至少部分交叠，同一条扫描线11的第二端112在衬底01的正投影和导电部12在衬底01的正投影至少部分交叠。如此设置，使得同一条扫描线11延伸至非显示区20的两个端部均可通过相对应设置的导电部12进行静电荷的释放，通过两个端部同时对一条扫描线11上的静电荷进行释放，有利于提高扫描线11上静电荷的释放效果，从而有利于提升相应显示面板的显示效果和使用寿命。There is a positional relationship between the plurality of conductive portions 12 and the scan lines 11 disposed in the non-display area 20. In the direction perpendicular to the plane of the substrate 01, the first end 111 of the same scan line 11 is on the substrate 01. The orthographic projection of the bottom 01 and the orthographic projection of the conductive part 12 on the substrate 01 at least partially overlap, and the orthographic projection of the second end 112 of the same scan line 11 on the substrate 01 and the orthographic projection of the conductive part 12 on the substrate 01 at least partially overlap. Partially overlapped. With this arrangement, both ends of the same scan line 11 extending to the non-display area 20 can release static charges through the corresponding conductive parts 12 , and the static charges on one scan line 11 can be simultaneously discharged through the two ends. The discharge of electrostatic charges on the scan lines 11 is beneficial to improving the release effect of electrostatic charges on the scan lines 11, thereby improving the display effect and service life of the corresponding display panel.
需要说明的是，本申请并不限定阵列基板100中的每一条扫描线11均可通过第一端111和第二端112进行静电荷的释放，阵列基板100中可存在部分扫描线11仅通过第一端111进行静电荷的释放，也可存在部分扫描线11仅通过第二端112进行静电荷的释放；用户可根据实际需求进行相应的设置和调整。It should be noted that this application does not limit that each scan line 11 in the array substrate 100 can release static charges through the first end 111 and the second end 112. There may be some scan lines 11 in the array substrate 100 that only pass through the first end 111 and the second end 112. The first end 111 releases electrostatic charges, and there may also be some scan lines 11 that only release electrostatic charges through the second end 112; the user can make corresponding settings and adjustments according to actual needs.
本申请提供一种可选择的实施例为，对于一个阵列基板100中的所有扫描线11，每一条扫描线11的第一端111和第二端112均设置有相对应的导电部12，实现每一条扫描线11的第一端111、第二端112均可用于释放静电荷至其对应的导电部12中，从而增加扫描线11上静电荷的释放路径，提升扫描线11上静电荷的释放效率。This application provides an optional embodiment that for all the scan lines 11 in an array substrate 100, the first end 111 and the second end 112 of each scan line 11 are provided with corresponding conductive parts 12 to achieve The first end 111 and the second end 112 of each scan line 11 can be used to release electrostatic charges into its corresponding conductive portion 12 , thereby increasing the release path of electrostatic charges on the scan lines 11 and improving the electrostatic charge on the scan lines 11 . Unleash efficiency.
需要说明的是，图2、图3以及后续的附图中，均以透视图的方式将衬底01进行体现，以清晰说明例如扫描线11、导电部12等沿垂直于衬底01所在平面的方向的正投影是位于衬底01内的。It should be noted that in Figures 2, 3 and subsequent drawings, the substrate 01 is shown in a perspective view to clearly illustrate that, for example, the scanning lines 11, the conductive portions 12, etc. are arranged along a plane perpendicular to the plane where the substrate 01 is located. The orthographic projection of the direction is located within substrate 01.
请参照图2和图3，可选地，沿垂直于衬底01所在平面的方向，每一导电部12在衬底01的正投影面积为W1，每一有源层单元13在衬底01的正投影面积为W2；Please refer to FIGS. 2 and 3 , optionally, along the direction perpendicular to the plane of the substrate 01 , the orthogonal projected area of each conductive part 12 on the substrate 01 is W1, and each active layer unit 13 is on the substrate 01 The orthographic projection area is W2;
其中，至少一个W1＞W2。Among them, at least one W1>W2.
具体地，本申请阵列基板100的非显示区20包括多个导电部12，显示区10包括多个有源层单元13，如图2和图3所示出的，导电部12的面积大于有源层单元13的面积。具体地，沿垂直于衬底01所在平面的方向，本申请设置每一导电部12在衬底01的正投影面积为W1，每一有源层单元13在衬底01的正投影面积为W2，设置至少包括一个W1＞W2。需要说明的是，本申请提供一种可选择的设置方式为，将非显示区20中导电部12的面积设置为大于显示区10中有源层单元13的面积，从而有利于实现一个导电部12和扫描线11的端部在衬底01的正投影的交叠面积，大于一个有源层单元13和扫描线11在衬底01的正投影的交叠面积，有利于提高导电部12和扫描线11端部的交叠面积。设置W1＞W2时，可以增大导电部12与扫描线11的交叠面积，提高导电部12用于收集并释放静电荷的能力；具体地，导电部12在衬底01的正投影和扫描线11在衬底01的正投影之间的交叠面积越大，扫描线11上静电荷向导电部12转移的路径越宽广，从而有利于提升扫描线11上静电荷的释放效率，避免阵列基板100的边缘部分被静电荷击伤的现象发生。Specifically, the non-display area 20 of the array substrate 100 of the present application includes a plurality of conductive parts 12, and the display area 10 includes a plurality of active layer units 13. As shown in FIGS. 2 and 3, the area of the conductive parts 12 is larger than that of the active layer units 13. The area of the source layer unit 13. Specifically, along the direction perpendicular to the plane of the substrate 01 , this application sets the orthogonal projected area of each conductive part 12 on the substrate 01 to be W1, and the orthogonal projected area of each active layer unit 13 on the substrate 01 is W2. , the setting includes at least one W1>W2. It should be noted that this application provides an optional setting method, which is to set the area of the conductive part 12 in the non-display area 20 to be larger than the area of the active layer unit 13 in the display area 10, thereby facilitating the realization of a conductive part. The overlapping area of the orthographic projection of the end of the scanning line 12 and the substrate 01 on the substrate 01 is larger than the overlapping area of the orthographic projection of the active layer unit 13 and the scanning line 11 on the substrate 01, which is beneficial to improving the conductive portion 12 and The overlapping area of the ends of scan line 11. When W1>W2 is set, the overlapping area of the conductive part 12 and the scan line 11 can be increased, and the ability of the conductive part 12 to collect and release electrostatic charges is improved; specifically, the orthographic projection and scanning of the conductive part 12 on the substrate 01 The larger the overlapping area of the line 11 between the orthographic projections of the substrate 01, the wider the path for the electrostatic charge on the scan line 11 to transfer to the conductive portion 12, which is conducive to improving the release efficiency of the electrostatic charge on the scan line 11 and avoiding the array. The edge portion of the substrate 100 is damaged by electrostatic charges.
本申请并不限定阵列基板100上所有导电部12在衬底01的正投影面积均大于每一有源层单元13在衬底01的正投影面积，用户可根据实际需求对其进行相应调整。This application does not limit the orthographic projection area of all conductive portions 12 on the array substrate 100 to the substrate 01 to be larger than the orthographic projection area of each active layer unit 13 on the substrate 01. Users can adjust it accordingly according to actual needs.
请继续参照图2和图3，可选地，沿垂直于衬底01所在平面的方向，至少部分导电部12在衬底01的正投影面积相同、且形状相同。Please continue to refer to FIGS. 2 and 3 , optionally, along the direction perpendicular to the plane where the substrate 01 is located, at least part of the conductive portion 12 has the same orthographic projection area on the substrate 01 and the same shape.
具体地，本申请提供一种可选择的实施例为，各个导电部12在衬底01的正投影具有相同的面积和相同的形状，也即阵列基板100中的各个导电部12可选择均通过同一种制程和工艺进行制作，有利于简化阵列基板100的制作工艺，提高阵列基板100的制作效率。Specifically, this application provides an alternative embodiment in which the orthographic projection of each conductive portion 12 on the substrate 01 has the same area and the same shape, that is, each conductive portion 12 in the array substrate 100 can choose to pass through Manufacturing using the same process and technology is beneficial to simplifying the manufacturing process of the array substrate 100 and improving the manufacturing efficiency of the array substrate 100 .
需要说明的是，本申请并不以各个导电部12在衬底01的正投影具有相同的面积和相同的形状作为阵列基板100的限定条件，也可仅设置阵列基板100中的部分导电部12在衬底01的正投影具有相同的面积和相同的形状，在此基础上还包括多个导电部12在衬底01的正投影具有不同的面积、不同的形状；用户可根据实际需求对其进行相应调整。It should be noted that this application does not require that each conductive part 12 has the same area and the same shape in the orthographic projection of the substrate 01 as the limiting condition of the array substrate 100 , and only part of the conductive parts 12 in the array substrate 100 may be provided. The orthographic projection of the substrate 01 has the same area and the same shape. On this basis, it also includes a plurality of conductive parts 12 with different areas and different shapes in the orthographic projection of the substrate 01; the user can adjust them according to actual needs. Make adjustments accordingly.
请继续参照图2和图3，可选地，至少部分导电部12包括至少一个尖端。Continuing to refer to FIGS. 2 and 3 , optionally, at least part of the conductive portion 12 includes at least one tip.
具体地，本申请所提供的用于释放扫描线11上静电荷的导电部12，可设置至少部分导电部12包括尖端，例如导电部12在衬底01的正投影为矩形、菱形、三角形、带有尖端的水滴形等，只要是具有至少一个尖端的形状均可；例如图2和图3中所示出的菱形导电部12。设置有尖端的导电部12可通过尖端放电的方式将扫描线11上传输至导电部12的静电荷向外部进行释放，即导电部12上的尖端起到了有效吸引和定点释放静电荷的效果，有利于提升导电部12对于其所对应的扫描线11中静电荷的收集释放能力，避免阵列基板100显示区10内的边缘区域因静电击伤所导致的短路、点类不良等缺陷。Specifically, the conductive part 12 provided in this application for releasing static charges on the scan line 11 can be provided with at least part of the conductive part 12 including a tip. For example, the orthographic projection of the conductive part 12 on the substrate 01 is a rectangle, a rhombus, a triangle, It can be a teardrop shape with a tip, etc., as long as it has at least one tip; for example, the rhombus-shaped conductive portion 12 shown in FIGS. 2 and 3 . The conductive part 12 provided with a tip can release the electrostatic charge transmitted from the scan line 11 to the conductive part 12 to the outside through tip discharge. That is, the tip on the conductive part 12 has the effect of effectively attracting and releasing electrostatic charges at a fixed point. It is beneficial to improve the ability of the conductive part 12 to collect and release static charges in its corresponding scan line 11 and avoid short circuits, dot defects and other defects caused by electrostatic damage in the edge area of the display area 10 of the array substrate 100 .
需要说明的是，本申请并不限定阵列基板100中的每一个导电部12均包括至少一个尖端，可仅选择设置部分导电部12具有尖端结构；用户可根据实际需求，例如导电部12所对应位置对阵列基板100良率的影响程度，对其进行相应调整。It should be noted that this application does not limit each conductive part 12 in the array substrate 100 to include at least one tip. Only part of the conductive parts 12 can be selected to have a tip structure; the user can, according to actual needs, for example, the corresponding conductive part 12 The degree of influence of the position on the yield of the array substrate 100 is adjusted accordingly.
图4所示为本申请实施例所提供的图1中A区域的另一种俯视图，请参照图1和图4，可选地，导电部12包括第一子导电部121和第二子导电部122；Figure 4 shows another top view of area A in Figure 1 provided by the embodiment of the present application. Please refer to Figures 1 and 4. Optionally, the conductive part 12 includes a first sub-conductive part 121 and a second sub-conductive part. Department 122;
沿垂直于衬底01所在平面的方向，至少包括一条扫描线11在衬底01的正投影与第一子导电部121、第二子导电部122在衬底01的正投影均交叠；Along the direction perpendicular to the plane of the substrate 01, the orthographic projection of at least one scan line 11 on the substrate 01 overlaps with the orthographic projections of the first sub-conductive part 121 and the second sub-conductive part 122 on the substrate 01;
沿第一方向上，第一子导电部121、第二子导电部122均位于扫描线11的同一端，第二子导电部122位于第一子导电部121远离显示区10的一侧；Along the first direction, the first sub-conductive part 121 and the second sub-conductive part 122 are located at the same end of the scanning line 11, and the second sub-conductive part 122 is located on the side of the first sub-conductive part 121 away from the display area 10;
沿垂直于衬底01所在平面的方向，第一子导电部121在衬底01的正投影面积为S11，第二子导电部122在衬底01的正投影面积为S12，其中，S12＞S11。Along the direction perpendicular to the plane of the substrate 01, the orthogonal projected area of the first sub-conductive part 121 on the substrate 01 is S11, and the orthogonal projected area of the second sub-conductive part 122 on the substrate 01 is S12, where S12>S11 .
具体地，一个导电部12可由多个子类导电部(例如第一子导电部121和第二子导电部122)组成，此时，沿垂直于衬底01所在平面的方向，该导电部12对应设置的扫描线11在衬底01的正投影与第一子导电部121、第二子导电部122在衬底01的正投影均具有交叠面积，以使得第一子导电部121和第二子导电部122可均用于该扫描线11上的静电荷的释放。Specifically, one conductive part 12 may be composed of multiple sub-type conductive parts (such as the first sub-conductive part 121 and the second sub-conductive part 122). At this time, along the direction perpendicular to the plane where the substrate 01 is located, the conductive part 12 corresponds to The orthographic projection of the scan line 11 on the substrate 01 and the orthographic projection of the first sub-conductive part 121 and the second sub-conductive part 122 on the substrate 01 have an overlapping area, so that the first sub-conductive part 121 and the second sub-conductive part 122 have an overlapping area. The sub-conductive parts 122 can all be used to release electrostatic charges on the scan line 11 .
需要说明的是，该第一子导电部121和第二子导电部122均位于扫描线11的同一侧，即沿第一方向上，第一子导电部121、第二子导电部122均与扫描线11的同一端部的正投影相交叠；其中，可将第二子导电部122位于第一子导电部121远离显示区10的一侧设置。It should be noted that the first sub-conductive part 121 and the second sub-conductive part 122 are located on the same side of the scan line 11 , that is, along the first direction, the first sub-conductive part 121 and the second sub-conductive part 122 are both on the same side of the scan line 11 . The orthographic projections of the same end of the scan line 11 overlap; wherein, the second sub-conductive part 122 can be disposed on a side of the first sub-conductive part 121 away from the display area 10 .
本申请提供一种可选择的实施例为，沿垂直于衬底01所在平面的方向，同一导电部12中的第一子导电部121在衬底01的正投影面积为S11，第二子导电部122在衬底01的正投影面积为S12，设置S12＞S11；也即同一导电部12中的第一子导电部121在衬底01的正投影面积S11小于第二子导电部122在衬底01的正投影面积S12，且第二子导电部122位于第一子导电部121远离显示区10一侧。换句话说，设置于扫描线11一端用于释放该扫描线11上静电荷的导电部12，设置为沿显示区10指向非显示区20一侧，该导电部12中的子类导电部(例如第一子导电部121、第二子导电部122)的正投影面积越来越大。面积越大的子类导电部(例如第二子导电部122)吸引静电荷聚集的能力越大，则用于释放扫描线11中静电荷的效果越好，将正投影面积较大的第二子导电部122设置于正投影面积较小的第一子导电部121远离显示区10的一侧，可以实现远离显示区10一侧的第二子导电部122收集扫描线11上静电荷的能力更强，则越靠近显示区10位置的子类导电部(例如第一子导电部121)上的残余静电荷的数量越小。An optional embodiment provided by this application is that along the direction perpendicular to the plane where the substrate 01 is located, the front projection area of the first sub-conductive part 121 in the same conductive part 12 on the substrate 01 is S11, and the second sub-conductive part 121 The orthogonal projected area of the portion 122 on the substrate 01 is S12, and S12>S11 is set; that is, the orthogonal projected area S11 of the first sub-conductive portion 121 in the same conductive portion 12 on the substrate 01 is smaller than the orthogonal projected area S11 of the second sub-conductive portion 122 on the substrate. The orthographic projection area S12 of the bottom 01 is 12, and the second sub-conductive part 122 is located on the side of the first sub-conductive part 121 away from the display area 10. In other words, the conductive portion 12 disposed at one end of the scan line 11 for releasing static charges on the scan line 11 is disposed along the display area 10 toward the non-display area 20 side, and the sub-type conductive portions in the conductive portion 12 ( For example, the front projection area of the first sub-conductive part 121 and the second sub-conductive part 122) is getting larger and larger. The larger the area of the sub-type conductive part (such as the second sub-conductive part 122), the greater the ability to attract electrostatic charge accumulation, and the better the effect of releasing the electrostatic charge in the scan line 11. The second sub-type conductive part with a larger front projection area is The sub-conductive part 122 is disposed on the side of the first sub-conductive part 121 with a smaller front projection area away from the display area 10 , which can realize the ability of the second sub-conductive part 122 on the side away from the display area 10 to collect static charges on the scan line 11 If the electrostatic charge is stronger, the amount of residual electrostatic charge on the sub-type conductive part (for example, the first sub-conductive part 121 ) closer to the display area 10 is smaller.
再者，导电部12中所收集到的扫描线11上的静电荷，会从导电部12向其周边的闲置空间进行释放，通过远离显示区10一侧的第二子导电部122来收集更多数量的静电荷，能够降低导电部12收集到的静电荷进而向显示区10内部游走的风险，降低显示区10内边缘器件被静电荷击伤的风险，有利于进一步提升阵列基板100的良产率。Furthermore, the electrostatic charge on the scan line 11 collected in the conductive part 12 will be released from the conductive part 12 to the idle space around it, and more electrostatic charges will be collected through the second sub-conductive part 122 on the side away from the display area 10 A large amount of electrostatic charges can reduce the risk of electrostatic charges collected by the conductive part 12 and then migrate into the display area 10 , reduce the risk of edge devices in the display area 10 being damaged by electrostatic charges, and help further improve the performance of the array substrate 100 Good yield.
还需要说明的是，本申请对于第一子导电部121和第二子导电部122的形状并不做具体限定，例如可设置第一子导电部121和第二子导电部122为相似图形，也可设置第一子导电部121和第二子导电部122为完全不同的图形；例如设置第二子导电部122具有比第一子导电部121更多的尖端结构等。本申请对此并不做具体限定，用户可根据需求进行相应的调整。It should also be noted that this application does not specifically limit the shapes of the first sub-conductive part 121 and the second sub-conductive part 122. For example, the first sub-conductive part 121 and the second sub-conductive part 122 can be set to have similar shapes. The first sub-conductive part 121 and the second sub-conductive part 122 may also be provided with completely different patterns; for example, the second sub-conductive part 122 may be provided with more tip structures than the first sub-conductive part 121 . This application does not specifically limit this, and users can make corresponding adjustments according to needs.
图5所示为本申请实施例所提供的图1中A区域的另一种俯视图，请参照图1、图3和图5，可选地，沿垂直于衬底01所在平面的方向，至少包括一条扫描线11在衬底01的正投影与多个导电部12在衬底01的正投影交叠；Figure 5 shows another top view of the area A in Figure 1 provided by the embodiment of the present application. Please refer to Figures 1, 3 and 5. Alternatively, along the direction perpendicular to the plane where the substrate 01 is located, at least It includes that the orthographic projection of one scan line 11 on the substrate 01 overlaps with the orthographic projection of the plurality of conductive portions 12 on the substrate 01;
沿扫描线11向其两端分别延伸的方向，导电部12的面积逐渐增大。Along the direction in which the scanning line 11 extends toward its two ends, the area of the conductive portion 12 gradually increases.
具体地，本申请提供了一种可选择的实施例为，沿垂直于衬底01所在平面的方向，存在至少一条扫描线11在衬底01的正投影与多个导电部12在衬底01的正投影交叠，具体为一条扫描线11的至少一个端部在衬底01的正投影与多个导电部12在衬底01的正投影交叠，也可为一条扫描线11的第一端111、第二端112在衬底01的正投影均与多个导电部12在衬底01的正投影交叠。Specifically, this application provides an alternative embodiment in which, along the direction perpendicular to the plane of the substrate 01 , there is at least one orthographic projection of the scan line 11 on the substrate 01 and a plurality of conductive portions 12 on the substrate 01 The orthographic projection overlaps, specifically the orthographic projection of at least one end of one scan line 11 on the substrate 01 overlaps with the orthographic projection of the plurality of conductive portions 12 on the substrate 01 , or it can also be the first intersection of one scan line 11 The orthographic projections of the end 111 and the second end 112 on the substrate 01 both overlap with the orthographic projections of the plurality of conductive parts 12 on the substrate 01 .
需要说明的是，图5中仅示出了扫描线11右侧非显示区20中导电部12的一种设置方式，对于扫描线11左侧非显示区20中导电部12的设置方式可以右侧作为参照。再者，图5中示出的同一条扫描线11对应设置的多个导电部12具有不同的形状，仅是本申请提供的一种可行的实施例，本申请并不以此为限，导电部12的形状可根据实际需求进行相应的改变。图5中靠近显示区10一侧的两个导电部12的尖端均朝向远离显示区10的一侧，使得导电部12通过尖端释放收集到的静电荷时，静电荷均朝向非显示区20释放，有利于避免静电荷被释放到显示区10中对显示区10边缘的器件造成损伤。It should be noted that FIG. 5 only shows one arrangement mode of the conductive portion 12 in the non-display area 20 on the right side of the scanning line 11. The arrangement mode of the conductive portion 12 in the non-display area 20 on the left side of the scanning line 11 can be as follows: side as a reference. Furthermore, the plurality of conductive portions 12 corresponding to the same scan line 11 shown in FIG. 5 have different shapes, which is only a feasible embodiment provided by the present application, and the present application is not limited thereto. The shape of the portion 12 can be changed accordingly according to actual needs. In FIG. 5 , the tips of the two conductive parts 12 on the side close to the display area 10 are all facing the side away from the display area 10 , so that when the conductive parts 12 release the collected electrostatic charges through the tips, the electrostatic charges are all released towards the non-display area 20 , which is beneficial to avoid electrostatic charges being released into the display area 10 and causing damage to devices at the edge of the display area 10 .
当沿垂直于衬底01所在平面的方向，扫描线11的第一端111在衬底01的正投影与多个导电部12在衬底01的正投影交叠时，可设置沿扫描线11向第一端111的延伸方向上，导电部12在衬底01正投影的面积逐渐增大；当扫描线11的第二端112在衬底01的正投影与多个导电部12在衬底01的正投影交叠时，可设置沿扫描线11向第二端112的延伸方向上，导电部12在衬底01正投影的面积逐渐增大；当扫描线11的第一端111、第二端112在衬底01的正投影均与多个导电部12在衬底01的正投影交叠时，沿扫描线11向其两端分别延伸的方向，导电部12的面积均是呈逐渐增大的状态设置。When the orthographic projection of the first end 111 of the scanning line 11 on the substrate 01 overlaps with the orthographic projection of the plurality of conductive portions 12 on the substrate 01 along the direction perpendicular to the plane of the substrate 01 , the configuration along the scanning line 11 can be In the extending direction toward the first end 111 , the area of the conductive portion 12 in the orthographic projection of the substrate 01 gradually increases; when the second end 112 of the scan line 11 is in the orthographic projection of the substrate 01 and the multiple conductive portions 12 are in the substrate 01 When the orthographic projections of 01 overlap, it can be arranged that along the extending direction of the scan line 11 to the second end 112, the area of the conductive portion 12 on the orthographic projection of the substrate 01 gradually increases; when the first end 111 and the second end 111 of the scan line 11 When the orthographic projections of the two ends 112 on the substrate 01 overlap with the orthographic projections of the plurality of conductive portions 12 on the substrate 01 , along the direction in which the scan line 11 extends to its two ends respectively, the areas of the conductive portions 12 are gradually Increased status settings.
通过将扫描线11末端对应的多个导电部12，以在衬底01正投影的面积为由小到大的方式，沿远离显示区10的一侧方向进行设置，以使得最靠近阵列基板100边缘的导电部12的面积最大，最靠近显示区10的导电部12的面积最小。由于大面积的导电部12具有更强的吸引静电荷聚集的能力，如此设置，可实现扫描线11中的静电荷被尽可能的吸引并聚集到面积最大的导电部12处进行释放，使得越靠近显示区10的方向残余静电荷的数量越少，从而可以降低从导电部12进一步转移到显示区10内的静电荷数量，有利于保护显示区10边缘的像素单元不被静电荷击伤，避免显示区10内的边缘区域发生短路、点类不良等缺陷。By arranging the plurality of conductive portions 12 corresponding to the ends of the scan lines 11 along the direction away from the display area 10 in order from small to large in the orthographic projection area of the substrate 01 , so as to be closest to the array substrate 100 The conductive portion 12 at the edge has the largest area, and the conductive portion 12 closest to the display area 10 has the smallest area. Since the large-area conductive part 12 has a stronger ability to attract the accumulation of electrostatic charges, such an arrangement can realize that the electrostatic charges in the scan line 11 are attracted as much as possible and gathered to the conductive part 12 with the largest area for release, so that the electrostatic charges can be released more easily. The smaller the amount of residual static charges in the direction closer to the display area 10 , which can reduce the amount of static charges further transferred from the conductive part 12 into the display area 10 , which is beneficial to protecting the pixel units at the edge of the display area 10 from being damaged by electrostatic charges. This avoids defects such as short circuits and defective dots in the edge areas of the display area 10 .
图6所示为本申请实施例所提供的图1中A区域的另一种俯视图，请参照图1和图6，可选地，非显示区20还包括至少一条金属线113，每条金属线113与一条扫描线11电连接；Figure 6 shows another top view of area A in Figure 1 provided by an embodiment of the present application. Please refer to Figures 1 and 6. Optionally, the non-display area 20 also includes at least one metal line 113, each metal line 113. Line 113 is electrically connected to a scan line 11;
沿垂直于衬底01所在平面的方向，至少包括一个导电部12在衬底01的正投影与金属线113在衬底01的正投影交叠。Along the direction perpendicular to the plane of the substrate 01 , the orthographic projection of at least one conductive portion 12 on the substrate 01 overlaps with the orthographic projection of the metal line 113 on the substrate 01 .
具体地，本申请还提供了一种可选择的实施例为，在阵列基板100的非显示区20增设多条金属线113，至少一条金属线113与一条扫描线11电连接，具体可为，扫描线11的末端进一步电连接一条或多条金属线113。同时，沿垂直于衬底01所在平面的方向，设置导电部12在衬底01的正投影与金属线113在衬底01的正投影具有交叠面积，从而可实现通过金属线113将扫描线11上的静电荷向导电部12进行释放，增加了扫描线11上静电荷的释放路径，有利于提升扫描线11上静电荷的释放效率。Specifically, this application also provides an optional embodiment of adding a plurality of metal lines 113 to the non-display area 20 of the array substrate 100, and at least one metal line 113 is electrically connected to one scanning line 11. Specifically, it can be: The ends of the scan lines 11 are further electrically connected to one or more metal lines 113 . At the same time, along the direction perpendicular to the plane of the substrate 01 , the orthographic projection of the conductive part 12 on the substrate 01 and the orthographic projection of the metal line 113 on the substrate 01 have an overlapping area, so that the scanning line can be realized through the metal line 113 The electrostatic charge on the scan line 11 is released to the conductive portion 12 , which increases the release path of the electrostatic charge on the scan line 11 , which is beneficial to improving the electrostatic charge release efficiency on the scan line 11 .
需要说明的是，用于释放金属线113上静电荷的导电部12可为同时用于释放扫描线11上静电荷的导电部12，如图6中右上Q1和右下Q2两个区域示出的导电部12；也可为每一条金属线113所对应设置的导电部12可仅用于对该条金属线113上的静电荷进行释放，而不用于与其余金属线113/扫描线11上静电荷的释放，如图6中Q3区域对应设置的金属线113和导电部12。本申请对于金属线113和导电部12之间的设置关系并不做具体限定，例如一个导电部12可对应于多条金属线113和/或扫描线11上静电荷的释放；也可设置金属线113和导电部12为一一对应的关系，与扫描线11直接对应的导电部12也不与金属线113具有对应的交叠面积。It should be noted that the conductive part 12 used to release the static charge on the metal line 113 may be the conductive part 12 used to release the static charge on the scan line 11 at the same time, as shown in the upper right Q1 and lower right Q2 areas in FIG. 6 The conductive part 12; the conductive part 12 provided corresponding to each metal line 113 can only be used to release the electrostatic charge on this metal line 113, and is not used to communicate with other metal lines 113/scan lines 11. The release of electrostatic charge refers to the metal line 113 and the conductive part 12 corresponding to the Q3 area in Figure 6 . This application does not specifically limit the arrangement relationship between the metal lines 113 and the conductive portion 12. For example, one conductive portion 12 can correspond to the release of electrostatic charges on multiple metal lines 113 and/or the scanning lines 11; metal can also be provided. The lines 113 and the conductive portions 12 have a one-to-one correspondence, and the conductive portions 12 directly corresponding to the scan lines 11 do not have a corresponding overlapping area with the metal lines 113 .
通过设置金属线113，可将扫描线11第一端111和/或第二端112所存在的静电荷向金属线113上进行分散，有利于避免扫描线11端部静电荷数量积累过大，通过金属线113、扫描线11端部同时将静电荷向导电部12进行释放，有利于提高扫描线11上静电荷的释放效率，避免扫描线11末端被静电击伤、边缘像素单元炸伤的问题，大幅度提高阵列基板100的抗静电能力，提高了阵列基板100的良品率。By arranging the metal line 113, the electrostatic charge existing at the first end 111 and/or the second end 112 of the scan line 11 can be dispersed to the metal line 113, which is beneficial to avoid excessive accumulation of electrostatic charge at the end of the scan line 11. The electrostatic charges are simultaneously released to the conductive part 12 through the ends of the metal lines 113 and the scan lines 11, which is beneficial to improving the release efficiency of the electrostatic charges on the scan lines 11 and preventing the ends of the scan lines 11 from being damaged by static electricity and the edge pixel units being damaged. problem, the anti-static ability of the array substrate 100 is greatly improved, and the yield rate of the array substrate 100 is improved.
图7所示为本申请实施例所提供的图1中A区域的另一种俯视图，请参照图1和图7，可选地，沿垂直于衬底01所在平面的方向，每条金属线113在衬底01的正投影分别与至少一个导电部12在衬底01的正投影交叠。Figure 7 shows another top view of the area A in Figure 1 provided by the embodiment of the present application. Please refer to Figures 1 and 7. Optionally, along the direction perpendicular to the plane where the substrate 01 is located, each metal line The orthographic projections of 113 on the substrate 01 respectively overlap with the orthographic projections of the at least one conductive portion 12 on the substrate 01 .
具体地，本申请在扫描线11的末端增设金属线113后，每一条金属线113可至少对应设置有一个用于释放其上静电荷的导电部12，即可设置多个导电部12同时用于释放同一条金属线113上的静电荷，此时，沿垂直于衬底01所在平面的方向，每条金属线113在衬底01的正投影分别与至少一个导电部12在衬底01的正投影交叠。通过多个导电部12同时释放一条金属线113上的静电荷，有利于提高对应扫描线11上静电荷的释放效率，避免扫描线11末端被静电击伤、边缘像素单元炸伤的问题，大幅度提高阵列基板100的抗静电能力，提高了阵列基板100的良品率。Specifically, after the present application adds metal lines 113 at the ends of the scan lines 11, each metal line 113 can be provided with at least one conductive part 12 for releasing electrostatic charges thereon, that is, multiple conductive parts 12 can be provided simultaneously. When releasing the static charge on the same metal line 113, at this time, along the direction perpendicular to the plane of the substrate 01, the orthographic projection of each metal line 113 on the substrate 01 is respectively connected with the at least one conductive portion 12 on the substrate 01. Orthographic projection overlap. The simultaneous release of electrostatic charges on a metal line 113 through multiple conductive parts 12 is beneficial to improving the release efficiency of electrostatic charges on the corresponding scan line 11 and avoiding the problems of electrostatic damage to the end of the scan line 11 and damage to the edge pixel units, which greatly The anti-static ability of the array substrate 100 is greatly improved, and the yield rate of the array substrate 100 is improved.
具体地，请参照图7所示，例如一条金属线113可对应设置3个导电部12，多个导电部12的设置可用于分别对扫描线11中的残余静电荷进行收集并进行单独的释放；且一条扫描线11的一个端部可电连接多个金属线113，提高静电荷的分流效果；且一个导电部12也可用于对多条扫描线11上的静电荷进行收集释放，大面积设置的导电部12具有更高的收集静电荷的能力，以使得扫描线11上静电荷的释放效果更佳。Specifically, please refer to FIG. 7 . For example, one metal line 113 can be provided with three conductive portions 12 . The arrangement of multiple conductive portions 12 can be used to collect and release the residual electrostatic charges in the scan line 11 separately. ; And one end of one scan line 11 can be electrically connected to multiple metal lines 113 to improve the shunting effect of electrostatic charges; and a conductive part 12 can also be used to collect and release electrostatic charges on multiple scan lines 11, covering a large area. The conductive part 12 provided has a higher ability to collect electrostatic charges, so that the electrostatic charge release effect on the scan line 11 is better.
请参照图6、图7，可选地，金属线113和与其电连接的扫描线11采用同种材质、并在同一工艺中制成。Referring to FIGS. 6 and 7 , optionally, the metal line 113 and the scanning line 11 electrically connected thereto are made of the same material and made in the same process.
具体地，在制程中，增设于扫描线11一端的金属线113可选择与扫描线11采用同种材质、并在同一工艺中制成，如此设置可以简化阵列基板100的制作工序，提高阵列基板100的制作效率。需要说明的是，这只是本申请提供的一种实施例，并不用于限定本申请中金属线113和扫描线11的制作方式，扫描线11和金属线113也可选用不同的材质，在不同的制程中进行制作，只要金属线113能够用于分流扫描线11上的静电荷即可。用户可根据实际需求对金属线113和扫描线11的制程进行调整。Specifically, during the manufacturing process, the metal line 113 added to one end of the scan line 11 can be made of the same material as the scan line 11 and made in the same process. Such an arrangement can simplify the manufacturing process of the array substrate 100 and improve the efficiency of the array substrate. 100 production efficiency. It should be noted that this is only an embodiment provided by the present application and is not used to limit the manufacturing method of the metal line 113 and the scanning line 11 in the application. The scanning line 11 and the metal line 113 can also be made of different materials. It is produced in a manufacturing process, as long as the metal line 113 can be used to shunt the electrostatic charge on the scan line 11. The user can adjust the manufacturing process of the metal line 113 and the scanning line 11 according to actual needs.
图8所示为本申请实施例所提供的图7中扫描线的一种BB’截面图，图9所示为本申请实施例所提供的图7中金属线的一种CC’截面图，请参照图7和图8、图9，可选地，沿垂直于衬底01的方向、且沿垂直于金属线113的延伸方向，金属线113的截面面积为D1；沿垂直于衬底01的方向、且沿垂直于扫描线11的延伸方向，扫描线11的截面面积为D2；D1＝D2。Figure 8 shows a BB' cross-sectional view of the scanning line in Figure 7 provided by an embodiment of the present application, and Figure 9 shows a CC' cross-sectional view of the metal line in Figure 7 provided by an embodiment of the present application. Please refer to Figures 7, 8, and 9. Alternatively, along the direction perpendicular to the substrate 01 and along the extension direction perpendicular to the metal line 113, the cross-sectional area of the metal line 113 is D1; along the direction perpendicular to the substrate 01 direction and along the extension direction perpendicular to the scanning line 11, the cross-sectional area of the scanning line 11 is D2; D1=D2.
具体地，当在扫描线11的一端增设金属线113时，沿垂直于衬底01的方向、且沿垂直于金属线113的延伸方向，本申请设置金属线113的截面面积为D1；沿垂直于衬底01的方向、且沿垂直于扫描线11的延伸方向，本申请设置扫描线11的截面面积为D2，并提供一种可选择的设置方式为D1＝D2。换句话说，本申请设置扫描线11和与其电连接的各条金属线113具有相同的线宽，如此设置可以使得扫描线11中的静电荷在多条金属线113上的静电荷分流效果更加均衡，从而有利于静电荷均匀地向导电部12进行释放，提升扫描线11上静电荷的释放效果。Specifically, when a metal line 113 is added to one end of the scan line 11, along the direction perpendicular to the substrate 01 and along the extension direction perpendicular to the metal line 113, this application sets the cross-sectional area of the metal line 113 to D1; In the direction of the substrate 01 and along the extension direction perpendicular to the scan line 11, this application sets the cross-sectional area of the scan line 11 to D2, and provides an optional setting method of D1=D2. In other words, the present application sets the scan line 11 and each metal line 113 electrically connected to it to have the same line width. Such an arrangement can make the electrostatic charge shunting effect of the electrostatic charge in the scan line 11 on the multiple metal lines 113 more effective. Balance, thereby facilitating the uniform release of electrostatic charges to the conductive portion 12 and improving the electrostatic charge release effect on the scan line 11 .
同时，本申请还提供了一种可选择的实施例为，金属线113与扫描线11电连接，且其延伸方向朝向非显示区20远离显示区10的一侧，从而控制金属线113上静电荷在远离显示区10的一侧向导电部12进行释放，避免静电荷释放位置距离显示区10过近，进一步进入到显示区10中的情况；如此设置，使得扫描线11中静电荷的释放路径更优。At the same time, this application also provides an optional embodiment in which the metal line 113 is electrically connected to the scanning line 11, and its extension direction is toward the side of the non-display area 20 away from the display area 10, thereby controlling the static electricity on the metal line 113. The charges are released to the conductive portion 12 on the side away from the display area 10 to avoid the situation where the electrostatic charge release position is too close to the display area 10 and further enters the display area 10; this arrangement enables the release of electrostatic charges in the scan line 11 The path is better.
需要说明的是，本申请并不以此为限，也可选择设置金属线113与扫描线11的线宽不同。It should be noted that the present application is not limited to this, and the metal lines 113 and the scan lines 11 may also be configured to have different line widths.
图10所示为本申请实施例所提供的图1中A区域的另一种俯视图，请参照图1和图10，可选地，任一个导电部12包括多个形状相同的子导电部123，子导电部123之间电连接。FIG. 10 shows another top view of area A in FIG. 1 provided by the embodiment of the present application. Please refer to FIG. 1 and FIG. 10 . Optionally, any conductive part 12 includes a plurality of sub-conductive parts 123 with the same shape. , the sub-conductive parts 123 are electrically connected.
具体地，任一个导电部12可包括多个形状相同的子导电部123，且可同时设置多个子导电部123的面积均相同，且各个子导电部123之间电连接，形成一个整体的导电部12。面积和形状均相同的子导电部123制作工艺更为简单，有利于提高阵列基板100的制作效率。Specifically, any conductive part 12 may include a plurality of sub-conductive parts 123 with the same shape, and multiple sub-conductive parts 123 may be provided at the same time with the same area, and each sub-conductive part 123 is electrically connected to form an integral conductive part. Department 12. The manufacturing process of the sub-conductive parts 123 with the same area and shape is simpler, which is beneficial to improving the manufacturing efficiency of the array substrate 100 .
通过设置导电部12包括多个电连接子导电部123，有利于增加扫描线11端部在衬底01的正投影和导电部12在衬底01的正投影之间的交叠面积，从而提升扫描线11中静电荷的传输效率，提高阵列基板100的抗静电能力，提高阵列基板100的良品率。By arranging the conductive part 12 to include a plurality of electrical connectors and the conductive part 123, it is beneficial to increase the overlapping area between the orthographic projection of the end of the scan line 11 on the substrate 01 and the orthographic projection of the conductive part 12 on the substrate 01, thereby improving the The transmission efficiency of electrostatic charges in the scan lines 11 improves the antistatic ability of the array substrate 100 and improves the yield rate of the array substrate 100 .
图11所示为本申请实施例所提供的图1中A区域的另一种俯视图，请参照图1和图11，可选地，沿扫描线11向其两端分别延伸的方向，子导电部123的面积逐渐增大。Figure 11 shows another top view of the area A in Figure 1 provided by the embodiment of the present application. Please refer to Figure 1 and Figure 11. Optionally, along the direction in which the scan line 11 extends to its two ends, the sub-conducting The area of the portion 123 gradually increases.
具体地，任一个导电部12可包括多个形状相同的子导电部123，但并不限定多个子导电部123的面积大小均相同，此时例如可设置多个子导电部123的面积沿显示区10指向非显示区20的方向上(沿扫描线11向其两端分别延伸的方向)依次递增，且各个子导电部123之间电连接，形成一个整体的导电部12。Specifically, any conductive part 12 may include multiple sub-conductive parts 123 with the same shape, but the area size of the multiple sub-conductive parts 123 is not limited to be the same. In this case, for example, the areas of the multiple sub-conductive parts 123 may be arranged along the display area. 10 points increase in sequence in the direction of the non-display area 20 (along the direction in which the scanning line 11 extends to its two ends), and each sub-conductive part 123 is electrically connected to form an integral conductive part 12 .
通过设置导电部12包括面积依次增大的多个子导电部123，既能够增加扫描线11端部在衬底01的正投影和导电部12在衬底01的正投影之间的交叠面积，提升扫描线11中静电荷的传输效率；且还能够控制扫描线11中的静电荷尽可能多地向面积更大的子导电部123的位置进行释放，避免静电荷释放位置距离显示区10过近，进一步进入到显示区10中的情况；如此设置，使得扫描线11中静电荷的释放路径更优。By arranging the conductive part 12 to include a plurality of sub-conductive parts 123 with sequentially increasing areas, it is possible to increase the overlapping area between the orthographic projection of the end of the scan line 11 on the substrate 01 and the orthographic projection of the conductive part 12 on the substrate 01. The electrostatic charge transmission efficiency in the scan line 11 is improved; and the electrostatic charge in the scan line 11 can also be controlled to be released to the position of the larger sub-conductive portion 123 as much as possible, so as to avoid the electrostatic charge release position being too far away from the display area 10 Recently, it further enters the display area 10; this arrangement makes the release path of the electrostatic charge in the scan line 11 more optimal.
图12所示为本申请实施例所提供的阵列基板的另一种膜层结构示意图，请参照图12，可选地，阵列基板100还包括第一绝缘层14；导电部12和与其对应设置的扫描线11之间包括第一绝缘层14；Figure 12 shows a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application. Please refer to Figure 12. Optionally, the array substrate 100 also includes a first insulating layer 14; a conductive portion 12 and corresponding arrangements The first insulating layer 14 is included between the scan lines 11;
第一绝缘层14的介电常数为K，5.8≤K≤6.7。The dielectric constant of the first insulating layer 14 is K, 5.8≤K≤6.7.
具体地，阵列基板100还包括第一绝缘层14，导电部12和扫描线11之间包括绝缘层，此时导电部12和与其对应设置的扫描线11之间具体为第一绝缘层14。本申请此处提供第一绝缘层14的介电常数为5.8-6.7，在此介电常数范围内的第一绝缘层14具有更加良好的绝缘效果。Specifically, the array substrate 100 further includes a first insulating layer 14 , and an insulating layer is included between the conductive portion 12 and the scanning line 11 . In this case, the first insulating layer 14 is specifically between the conductive portion 12 and the corresponding scanning line 11 . This application provides that the dielectric constant of the first insulating layer 14 is 5.8-6.7. The first insulating layer 14 within this dielectric constant range has a better insulation effect.
且需要补充的是，该第一绝缘层14可由SiO和SiNx两层组成，其中，SiO与Poly-Si应力匹配效果好，有利于减少Poly-Si晶格缺陷与界面陷阱；SiNx具有极好的绝缘性；由SiO和SiNx两层组成的第一绝缘层14更能够满足阵列基板100所需的电学性能。What needs to be added is that the first insulating layer 14 can be composed of two layers of SiO andSiNx . Among them, SiO and Poly-Si have good stress matching effect, which is beneficial to reducing Poly-Si lattice defects and interface traps;SiN Good insulation; the first insulating layer 14 composed of two layers of SiO and SiNx can better meet the electrical performance required by the array substrate 100 .
具体地，通过扫描线11和导电部12之间存在的电势差，扫描线11上的静电荷穿过第一绝缘层14后被释放到相应的导电部12上，以此种非接触式的电荷传导方式对扫描线11上的静电荷进行释放，避免静电荷在扫描线11末端的累积，从而避免扫描线11末端被静电击伤、边缘像素单元炸伤的问题。Specifically, through the potential difference existing between the scan line 11 and the conductive part 12, the electrostatic charge on the scan line 11 passes through the first insulating layer 14 and is released to the corresponding conductive part 12. In this way, the non-contact charge The conduction method releases the electrostatic charge on the scan line 11 to avoid the accumulation of electrostatic charge at the end of the scan line 11, thereby avoiding the problem of the end of the scan line 11 being damaged by static electricity and the edge pixel units being damaged.
再者，导电部12和扫描线11之间设置第一绝缘层14，还有利于避免在去除静电荷的过程中，对阵列基板100中的其他器件造成破坏，提高阵列基板100的良产率。Furthermore, disposing the first insulating layer 14 between the conductive part 12 and the scan line 11 is also helpful to avoid damage to other devices in the array substrate 100 during the process of removing static charges, and improve the yield of the array substrate 100 .
图13所示为本申请实施例所提供的阵列基板的再一种膜层结构示意图，请参照图13，可选地，阵列基板100还包括第一绝缘层14；导电部12和与其对应设置的扫描线11之间包括第一绝缘层14；Figure 13 shows a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application. Please refer to Figure 13. Optionally, the array substrate 100 also includes a first insulating layer 14; a conductive portion 12 and corresponding arrangements The first insulating layer 14 is included between the scan lines 11;
导电部12和与其对应设置的扫描线11之间电连接。The conductive portion 12 is electrically connected to the corresponding scanning line 11 .
具体地，阵列基板100还包括第一绝缘层14，导电部12和扫描线11之间包括绝缘层，此时导电部12和与其对应设置的扫描线11之间具体为第一绝缘层14。除了上述通过非接触式对扫描线11上的静电荷进行释放的方式外，也可设置导电部12和与其对应设置的扫描线11之间电连接，具体例如可通过在第一绝缘层14开孔，通过在开孔中增设连接线141实现，扫描线11上的静电荷通过电连接的方式传导至导电部12进行释放。Specifically, the array substrate 100 further includes a first insulating layer 14 , and an insulating layer is included between the conductive portion 12 and the scanning line 11 . In this case, the first insulating layer 14 is specifically between the conductive portion 12 and the corresponding scanning line 11 . In addition to the above-mentioned non-contact way of releasing the electrostatic charge on the scan line 11 , an electrical connection between the conductive part 12 and the corresponding scan line 11 may also be provided. For example, the conductive part 12 may be electrically connected by opening an opening on the first insulating layer 14 . The hole is realized by adding a connecting line 141 in the opening, and the electrostatic charge on the scanning line 11 is conducted to the conductive part 12 through electrical connection for release.
除了图13所示出的，通过在第一绝缘层14开孔来实现扫描线11和导电部12的电连接外，也可直接去除部分第一绝缘层14，使得扫描线11和导电部12的之间没有绝缘层的设置，直接通过搭接实现扫描线11和导电部12的电连接。In addition to realizing the electrical connection between the scan line 11 and the conductive part 12 by opening holes in the first insulating layer 14 as shown in FIG. 13 , part of the first insulating layer 14 can also be directly removed, so that the scan line 11 and the conductive part 12 There is no insulating layer between them, and the electrical connection between the scan line 11 and the conductive part 12 is directly realized through overlapping.
请参照图12和图13，可选地，导电部12和有源层单元13采用同种材质、并在同一工艺中制成。Referring to FIGS. 12 and 13 , optionally, the conductive part 12 and the active layer unit 13 are made of the same material and made in the same process.
具体地，导电部12和有源层单元13可位于阵列基板100的同一膜层结构中进行设置，也即至少部分导电部12和有源层单元13可采用同种材质，并在同一工艺中制成，如此设置有利于简化阵列基板100的制作工艺，提高阵列基板100的制作效率。Specifically, the conductive portion 12 and the active layer unit 13 can be disposed in the same film structure of the array substrate 100 , that is, at least part of the conductive portion 12 and the active layer unit 13 can be made of the same material and processed in the same process. This arrangement is beneficial to simplifying the manufacturing process of the array substrate 100 and improving the manufacturing efficiency of the array substrate 100 .
此处提供一种可选择的实施例为，在制作显示区10有源层单元13的同时，扩大该有源层单元13的制作范围至非显示区20，位于非显示区20中的有源层单元13复用为导电部12，用于对延伸至非显示区20中的扫描线11端部的静电荷进行释放，避免扫描线11末端被静电击伤、边缘像素单元炸伤的问题。An optional embodiment provided here is to expand the manufacturing range of the active layer unit 13 to the non-display area 20 while manufacturing the active layer unit 13 in the display area 10. The layer unit 13 is reused as a conductive part 12 to release the electrostatic charge extending to the end of the scanning line 11 in the non-display area 20 to avoid the problem of the end of the scanning line 11 being damaged by static electricity and the edge pixel unit being damaged.
当导电部12和有源层单元13采用同种材质、并在同一工艺中制成时，则每一个有源层单元13的电阻率ρ1和每一个导电部12的电阻率ρ2是相等的；且每一个有源层单元13和每一个导电部12的制作厚度L也是相同的；在此条件下，沿垂直于衬底01所在平面的方向，当本申请设置每一导电部12在衬底01的正投影面积W1大于每一有源层单元13在衬底01的正投影面积W2时，根据本领域技术中的ρ＝RS/L，可知面积越大的导电部02其电阻越小，也即，如此设置有利于导电部02电阻的减小。其中，ρ为电阻率，R为电阻值，L为电阻长度，S为电阻面积。When the conductive part 12 and the active layer unit 13 are made of the same material and made in the same process, the resistivity ρ1 of each active layer unit 13 and the resistivity ρ2 of each conductive part 12 are equal. ; and the thickness L of each active layer unit 13 and each conductive part 12 is also the same; under this condition, along the direction perpendicular to the plane of the substrate 01, when the application sets each conductive part 12 in When the orthographic projection area W1 of the substrate 01 is larger than the orthographic projection area W2 of each active layer unit 13 on the substrate 01, according to ρ=RS/L in the art, it can be seen that the conductive portion 02 with a larger area has a higher resistance. Small, that is, such an arrangement is beneficial to reducing the resistance of the conductive part 02. Among them, ρ is the resistivity, R is the resistance value, L is the resistance length, and S is the resistance area.
图14所示为本申请实施例所提供的阵列基板中导电部复用有源层单元形成时的一种截面示意图，图15所示为本申请实施例所提供的阵列基板中导电部复用有源层单元形成时的另一种截面示意图；请参照图14、图15，除上述内容外，也可将现有技术中阵列基板在显示区的制程延伸至非显示区，在非显示区中，控制ILD(层间间隔层)源极(source)上开孔，漏极(Drain)ILD(层间间隔层)、PLN(平坦化层)、ITO1(第一电极层)未开孔、PV(钝化层)开小孔；或是源/漏极ILD(层间间隔层)、PLN(平坦化层)、ITO1(第一电极层)、PV(钝化层)均不开孔；以此实现非显示区中的子像素单元不用于显示，仅用于作为导电部对扫描线11上存在的残余静电荷进行释放，其中作为导电部12功能的膜层为有源层poly。FIG. 14 is a schematic cross-sectional view of the multiplexing of conductive portions in the array substrate provided by the embodiment of the present application when the active layer unit is formed. FIG. 15 shows the multiplexing of conductive portions in the array substrate provided by the embodiment of the present application. Another schematic cross-sectional view of the formation of the active layer unit; please refer to Figure 14 and Figure 15. In addition to the above, the process of the array substrate in the display area in the prior art can also be extended to the non-display area. In the control, holes are opened on the source electrode (source) of the ILD (interlayer spacer layer), and no holes are opened on the drain (Drain) ILD (interlayer spacer layer), PLN (planarization layer), and ITO1 (first electrode layer). The PV (passivation layer) has small holes; or the source/drain ILD (interlayer spacer), PLN (planarization layer), ITO1 (first electrode layer), and PV (passivation layer) do not have holes; In this way, the sub-pixel unit in the non-display area is not used for display, but is only used as a conductive part to release the residual electrostatic charge existing on the scan line 11, where the film layer that functions as the conductive part 12 is the active layer poly.
需要说明的是，上述通过对膜层结构中细节化的调整，以实现位于非显示区中的子像素单元不用于显示的内容，仅为本申请提供的几种可选择的实施例，但本申请并不以此为限。只要控制位于非显示区中的子像素单元为闲置状态，能够利用其中的有源层poly作为导电部12使用，实现对于扫描线11上静电荷的释放即可。It should be noted that the above-mentioned detailed adjustments to the film structure to realize that the sub-pixel units located in the non-display area are not used for display are only several optional embodiments provided by this application, but this application Applications are not limited to this. As long as the sub-pixel units located in the non-display area are controlled to be in an idle state, the active layer poly therein can be used as the conductive portion 12 to achieve the release of electrostatic charges on the scan lines 11 .
图16所示为本申请实施例所提供的显示面板的一种示意图，请在图1-图13的基础上参照图16，基于同一发明构思，本申请还提供了一种显示面板200，该显示面板200包括的阵列基板100。阵列基板100为本申请提供的任一种阵列基板100。Figure 16 shows a schematic diagram of a display panel provided by an embodiment of the present application. Please refer to Figure 16 on the basis of Figures 1-13. Based on the same inventive concept, this application also provides a display panel 200. The display panel 200 includes an array substrate 100 . The array substrate 100 is any array substrate 100 provided in this application.
图17所示为本申请实施例提供的显示装置的一种示意图，请参照图17，基于同一发明构思，本申请还提供了一种显示装置300，该显示装置300包括显示面板200。显示面板200为本申请提供的任一种显示面板200。FIG. 17 is a schematic diagram of a display device provided by an embodiment of the present application. Please refer to FIG. 17 . Based on the same inventive concept, the present application also provides a display device 300 . The display device 300 includes a display panel 200 . The display panel 200 is any display panel 200 provided by this application.
需要说明的是，本申请实施例所提供的显示装置的实施例可参见上述显示面板的实施例，重复指出不再赘述。本申请所提供的显示装置可以为：手机、平板电脑、电视机、台阶走线区、笔记本电脑、车载显示屏、导航仪等任何具有显示功能的产品和部件。It should be noted that, for the embodiments of the display device provided in the embodiments of the present application, reference may be made to the above embodiments of the display panel, which will not be described again. The display device provided by this application can be any product and component with a display function such as a mobile phone, a tablet computer, a television, a step wiring area, a notebook computer, a vehicle display screen, a navigator, etc.
通过上述实施例可知，本发明提供的阵列基板、显示面板和显示装置，至少实现了如下的有益效果：It can be seen from the above embodiments that the array substrate, display panel and display device provided by the present invention at least achieve the following beneficial effects:
本申请提供了一种阵列基板、显示面板和显示装置，通过在阵列基板的非显示区增设多个导电部，且设置导电部在衬底的正投影和与其对应设置的扫描线在衬底的正投影具有交叠面积，通过导电部释放与其具有交叠面积的扫描线上的静电荷，避免静电荷在扫描线末端的累积，从而避免扫描线末端被静电击伤、边缘像素单元炸伤的问题，大幅度提高显示面板的抗静电能力，提高了相应显示装置的良品率。The present application provides an array substrate, a display panel and a display device, by adding a plurality of conductive parts in the non-display area of the array substrate, and arranging the orthographic projection of the conductive parts on the substrate and the corresponding scan lines on the substrate. The orthographic projection has an overlapping area, and the conductive part releases the electrostatic charge on the scanning line with the overlapping area to avoid the accumulation of electrostatic charge at the end of the scanning line, thereby avoiding the end of the scanning line being injured by static electricity and the edge pixel unit being damaged. It greatly improves the anti-static ability of the display panel and improves the yield rate of the corresponding display device.
虽然已经通过例子对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上例子仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。Although some specific embodiments of the invention have been described in detail by way of examples, those skilled in the art will understand that the above examples are for illustration only and are not intended to limit the scope of the invention. Those skilled in the art will understand that the above embodiments can be modified without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110219806.XACN113161370B (en) | 2021-02-26 | 2021-02-26 | Array substrate, display panel and display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110219806.XACN113161370B (en) | 2021-02-26 | 2021-02-26 | Array substrate, display panel and display device |
| Publication Number | Publication Date |
|---|---|
| CN113161370A CN113161370A (en) | 2021-07-23 |
| CN113161370Btrue CN113161370B (en) | 2024-02-09 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110219806.XAActiveCN113161370B (en) | 2021-02-26 | 2021-02-26 | Array substrate, display panel and display device |
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| CN116490034A (en)* | 2023-05-25 | 2023-07-25 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN117525078A (en)* | 2023-06-27 | 2024-02-06 | 苏州华星光电技术有限公司 | Driving substrate and display panel |
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