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CN113115132B - Method and device for recombining frames in OLT (optical line terminal) - Google Patents

Method and device for recombining frames in OLT (optical line terminal)
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CN113115132B
CN113115132BCN202110226319.6ACN202110226319ACN113115132BCN 113115132 BCN113115132 BCN 113115132BCN 202110226319 ACN202110226319 ACN 202110226319ACN 113115132 BCN113115132 BCN 113115132B
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pon
multiplexing
bit width
mode
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娄非志
黄元波
李祥辉
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Fiberhome Telecommunication Technologies Co Ltd
Wuhan Fisilink Microelectronics Technology Co Ltd
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Fiberhome Telecommunication Technologies Co Ltd
Wuhan Fisilink Microelectronics Technology Co Ltd
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Abstract

The invention discloses a method and a device for frame recombination in an OLT (optical line terminal), and relates to the technical field of data storage and forwarding. The method comprises the following steps: each PON port carries out normalized adaptation on the data frames output by the uplink PON MAC, so that each data frame in all EPON series modes is aligned with a GPON series mode in the attribute description of the fragments; according to the requirements of the current application scene, each PON port gates a PON mode; transmitting the data to a corresponding recombination cache in a multi-channel multiplexing mode; and the recombination cache performs data recombination on the data multiplexed and output by the channels and outputs the data to a service scheduling plane for service scheduling. The invention can decouple the strong association between the protocol plane and the recombination plane, thereby improving the designability and maintainability; in addition, by using the design scheme of shared cache, the method not only can adapt to all PON modes, but also can effectively reduce the total cache usage and simplify the complexity of service scheduling.

Description

Method and device for recombining frames in OLT (optical line terminal)
Technical Field
The present invention relates to the technical field of data storage and forwarding, and in particular, to a method and an apparatus for frame reassembly in an OLT (Optical Line Terminal).
Background
The PON (Passive Optical Network) technology widely used in The existing Network includes two mainstream technologies of EPON (Ethernet Passive Optical Network) and GPON (Gigabit-Capable Passive Optical Network), which are widely used in The field of FTTX (Fiber To The X). The EPON technology has experienced 1G EPON, asymmetric 10G EPON and symmetric 10G EPON, and is developed towards higher bandwidth of 25G/50G; GPON technology goes through 1G GPON, XGPON1, XGSPON starts to be deployed on a large scale, and a new 25G/50G GPON scheme is released.
With the advancement of materials, processes and other technologies, in order to meet the demand of high-capacity central office equipment, the OLT equipment in the PON network is gradually upgraded with the technology, and the number of ports supported by a single chip is also multiplied, and the number of PON ports supported by a single chip is from 1 port, 2 ports, 4 ports to 16 or 32 ports at present. Meanwhile, in order to increase the usage amount of the same chip, the PON mode supported by a single chip is more and more abundant, and from an initial mode of the single chip to a mode of the single chip which simultaneously supports multiple modes such as EPON, symmetric 10G EPON, asymmetric 10G EPON, GPON, XGPON1, XGSPON, and the like, each port can support any mode through configuration. Therefore, the development of the OLT device for the multimode multi-PON port is a real requirement at present.
A conventional multi-mode multi-PON-port OLT upstream design is shown in fig. 1, where the OLT upstream may be roughly divided into a protocol plane (PON MAC), a reassembly plane (a data frame is reassembled from data fragments in the GPON technology into a complete data frame, or a data frame in the EPON technology is stored and then forwarded), and a service scheduling plane (a service processing plane schedules services of multiple data recombiners to a subsequent service processing plane) according to a data flow direction. The protocol plane and the recombination plane of each PON mode are in one-to-one correspondence and tightly coupled.
Taking the uplink of the 4-mode OLT supporting N PON ports in fig. 1 as an example, each PON mode simply copies the PON MAC of a single PON port and the corresponding reassembly buffer to meet the requirement of the N PON ports, and each PON port may be configured as any mode. In the scheme, 4 × N reassembly buffers are actually designed, only N reassembly buffers are working at the same time, and the rest 3 × N reassembly buffers are all in an idle state. Moreover, the reassembly buffers of the GPON technique need to support data interleaving reception, so that the buffer capacity is large, the occupied area is also large, and when the reassembly buffer of 3/4 is in an idle state, the waste is large. The service scheduling plane needs to schedule data for 4 × N reassembly buffers, and although scheduling needs to be performed only from N reassembly buffers at the same time, design waste is caused and design complexity is increased.
In summary, the uplink design scheme of the conventional multi-mode multi-PON port OLT has the following disadvantages:
1. the protocol planes (PON MAC) and the recombination planes of all PON modes are in one-to-one correspondence and tightly coupled, which is not beneficial to normalization and modular design and can cause a large amount of idle recombination caches, thereby not only wasting resources but also occupying a larger area and expanding the chip cost;
2. the number of recombination caches far exceeding the actual demand increases the difficulty of service scheduling;
3. the recombination cache units between the PON ports are completely isolated and cannot be shared with each other, which is not beneficial to improving the cache utilization rate.
Disclosure of Invention
The present invention aims to overcome the above-mentioned drawbacks of the background art, and provides a method and an apparatus for frame reassembly in an OLT, which can decouple the strong association between a protocol plane (PON MAC) and a reassembly plane, and use a design scheme of a shared buffer, so that the method and the apparatus can adapt to all PON modes, and simultaneously share the buffer, effectively reduce the total buffer usage, and simplify the complexity of service scheduling.
In order to achieve the above object, the present invention provides a method for frame reassembly in an OLT, which is applied to an OLT with multiple PON ports, where the OLT with multiple PON ports includes N PON ports, and each PON port supports M different PON modes; the method for recombining the frames in the OLT comprises the following steps:
step A, each PON port carries out normalized adaptation on a data frame output by an uplink PON MAC, so that each data frame in all EPON series modes is aligned with a GPON series mode in the attribute description of the fragments;
b, according to the requirements of the current application scene, each PON port gates a PON mode; transmitting the data to a corresponding recombination cache in a multi-channel multiplexing mode;
and step C, the recombination cache performs data recombination on the data multiplexed and output by the channels and outputs the data to a service scheduling plane for service scheduling.
On the basis of the technical scheme, the step A specifically comprises the following steps:
if the data frame output by the uplink PON MAC is a data frame in a GPON series mode, adapting the data frame which is cut into a plurality of fragments into a first GPON packaging format, and adapting the data frame of one fragment into a second GPON packaging format;
and if the data frame output by the uplink PON MAC is the data frame in the EPON series mode, the data frame is adapted to a second GPON packaging format after the last fragment lf information is added.
On the basis of the technical scheme, in the step B, multiplexing of multiple channels is realized by adopting a mode of increasing the clock frequency or widening the data bit width or combining the clock frequency and the data bit width.
On the basis of the technical scheme, the method for realizing multiplexing of multiple channels by adopting a mode of improving clock frequency specifically comprises the following steps: under the condition of keeping the data bit width unchanged, the clock frequency input by the multiple PON ports is increased, the source data of the multiple PON ports are combined into one PON data path in an interleaving mode, the clock frequency after the combination of the multiple PON ports into one PON data path is greater than or equal to X Y HZ, X is the multiplexing path number of the multiplexing of the multiple channels, and Y is the clock frequency of each PON port.
On the basis of the technical scheme, the method for realizing multiplexing of multiple channels by adopting a mode of widening data bit width specifically comprises the following steps: under the condition of keeping the clock frequency unchanged, source data of multiple PON ports are combined into one PON data path by widening the data bit width, the data bit width after the data bit width is combined into one path is X X L bit, X is the multiplexing path number of the multiplexing of multiple channels, and L is the data bit width of each PON port.
On the basis of the technical scheme, the method for realizing multiplexing of multiple channels by adopting a mode of combining clock frequency improvement and data bit width widening specifically comprises the following steps: the clock frequency and the data bit width are simultaneously increased, source data of multiple PON ports are combined into one PON data path, the clock frequency after the PON data path is combined into one PON data path is greater than or equal to (X/Z) Y HZ, the data bit width is Z X L bit, X is the multiplexing path number of multiplexing of multiple paths, Z is the data bit width broadening coefficient, Y is the clock frequency of each PON port, and L is the data bit width of each PON port.
On the basis of the technical scheme, when the multiplexing path number X of the multiplexing of the multi-path is selected in the multiplexing process of the multi-path, comprehensive evaluation is carried out according to the limitation of the maximum clock frequency P supported by the system, the maximum input data bandwidth M supported by the reorganization cache and the maximum input data bit width Q supported by the reorganization cache.
On the basis of the technical scheme, when the multiplexing number X of the multiplexing of the multi-channel is selected in the process of realizing the multiplexing of the multi-channel by adopting a mode of improving the clock frequency, comprehensive evaluation is carried out according to the limitation of the maximum clock frequency P supported by a system and the maximum input data bandwidth M supported by a recombination cache, and the specific limiting conditions are as follows: x is Y < P, and Y is the clock frequency of each PON port; and X Y L < M, L is the data bit width of each PON port.
On the basis of the technical scheme, in the process of multiplexing the multiple channels by adopting a mode of widening the data bit width, when the multiplexing path number X of the multiple channel multiplexing is selected, comprehensive evaluation is carried out according to the limitation of the maximum input data bit width Q supported by the reassembly cache and the maximum input data bandwidth M supported by the reassembly cache, and the specific limitation conditions are as follows: x is L < Q, L is the data bit width of each PON port; and X Y L M, Y is the clock frequency of each PON port.
On the basis of the technical scheme, when the multiplexing number X of the multiplexing of the multi-channel is selected in the multiplexing process of the multi-channel by adopting a mode of combining the improvement of the clock frequency and the widening of the data bit width, comprehensive evaluation is carried out according to the limitation of the maximum clock frequency P supported by the system, the maximum input data bandwidth M supported by the reassembly cache and the maximum input data bit width Q supported by the reassembly cache, and the specific limiting conditions are as follows: (X/Z) Y < P, wherein Z is a data bit width broadening coefficient, and Y is the clock frequency of each PON port; z is L < Q, L is the data bit width of each PON port; and X Y L < M.
The invention also provides a device for recombining frames in the OLT, which is applied to the OLT with multiple PON ports, wherein the OLT with multiple PON ports comprises N PON ports, and each PON port supports M different PON modes; the device for recombining the frames in the OLT comprises: the device comprises N normalized adaptation units and N mode selection units, wherein each normalized adaptation unit and each mode selection unit correspond to a PON port; the system also comprises N/X channel multiplexing units and N/X recombination cache units, wherein X is the multiplexing path number of channel multiplexing, X PON ports correspond to one channel multiplexing unit, and one channel multiplexing unit corresponds to one recombination cache unit;
the normalized adaptation unit is configured to: carrying out normalized adaptation on data frames output by the MAC of the uplink PON, so that each data frame in all EPON series modes is aligned with a GPON series mode in the attribute description of the fragments;
the mode selection unit is configured to: according to the requirements of the current application scene, gating a PON mode;
the channel multiplexing unit is configured to: transmitting the gated PON mode data to a corresponding recombination cache unit in a multi-channel multiplexing mode;
the reassembly cache unit is configured to: and performing data recombination on the data output by the channel multiplexing unit, and outputting the data to a service scheduling plane for service scheduling.
On the basis of the above technical solution, the normalization adaptation unit performs normalization adaptation on the data frame output by the uplink PON MAC, specifically including the following operations:
if the data frame output by the uplink PON MAC is a data frame in a GPON series mode, adapting the data frame which is cut into a plurality of fragments into a first GPON packaging format, and adapting the data frame of one fragment into a second GPON packaging format;
and if the data frame output by the uplink PON MAC is the data frame in the EPON series mode, the data frame is adapted to a second GPON packaging format after the last fragment lf information is added.
On the basis of the technical scheme, the channel multiplexing unit realizes multiplexing of multiple channels by adopting a mode of increasing clock frequency or widening data bit width or combining the clock frequency with the data bit width.
On the basis of the technical scheme, when the multiplexing path number X of the channel multiplexing is selected, comprehensive evaluation is carried out according to the limitation of the maximum clock frequency P supported by the system, the maximum input data bandwidth M supported by the reassembly cache and the maximum input data bit width Q supported by the reassembly cache.
The invention has the beneficial effects that:
in the invention, each PON port carries out normalized adaptation on the data frame output by the uplink PON MAC, so that the same processing technology can be used for the data output by all the PON MACs in the subsequent data processing, the strong association between the protocol plane (PON MAC) and the recombination plane is decoupled, the flexibility and the usability are improved, and the designability and the maintainability are higher. Meanwhile, the number of recombination caches finally used can be greatly reduced by selecting a PON mode and a data transmission mode of multiplexing multiple channels, so that the idle of the recombination caches is effectively avoided, and the chip area is reduced; and the design scheme of sharing the recombination cache by using a plurality of PON ports is beneficial to the balanced load of occupied cache resources among different PON ports, greatly reduces the quantity of scheduling source ports of a service scheduling plane, simplifies the complexity of service scheduling and meets the actual use requirement.
Drawings
Fig. 1 is a schematic diagram of a conventional multi-mode multi-PON port OLT upstream design;
fig. 2 is a schematic diagram of an uplink design of a multi-mode multi-PON port OLT according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for frame reassembly in an OLT in accordance with an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating adaptation of the encapsulation format of an EPON data frame and a GPON data frame according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an example implementation of 4-way channel multiplexing with increased clock frequency;
FIG. 6 is a diagram illustrating an example of implementing 4-way channel multiplexing using a broadened data bit width;
fig. 7 is a schematic diagram of an example of implementing 4-way channel multiplexing by using a combination of increasing a clock frequency and widening a data bit width.
Detailed Description
It can be understood that, in the existing OLT GPON technology, after an upstream data frame is decapsulated by (X) GEM, a data frame may be divided into multiple segments (i.e. fragments), and fragments between data frames of different T-CONT (Transmission containers) are also sent in an interleaved manner, the number of T-CONT supported by a single PON port can reach up to GPON 4K or XGPON/XGSPON 16K, and data must be a complete continuous data frame before entering a data service plane from PON MAC of OLT, which requires a large amount of buffer to reassemble fragmented data of multiple T-CONT into a complete data frame, and when the number of PON ports is increased to 16 or more, and simultaneously supported GPON technical modes include 1G GPON, XGPON1, XGSPON, and so on, a large amount of buffer is required. In the existing OLT EPON technology, each data frame of PON MAC uplink of the OLT is continuous and complete, the requirement of interpolation between the data frames does not need to be considered, and the required buffer between the PON MAC and a service plane is relatively small.
In the prior art, when the number of PON ports and PON modes supported by an OLT chip is small, the total capacity requirement for data buffering is relatively small, and the challenges caused by the increase of chip area and design complexity due to frame reassembly are also small, but when the number of PON ports supported by a chip reaches 8 or 16 or more and supported PON modes include all EPON and GPON technology series, the huge buffering requirement for frame reassembly and the complexity of a service scheduling plane will have a large influence on the chip cost, and a new design method must be introduced to optimize buffering and scheduling so as to achieve better balance between performance and cost.
Therefore, aiming at the requirements of uplink recombination and service scheduling of the multi-mode multi-PON port OLT, the invention aims to provide a method and a device for frame recombination in the OLT, which can decouple the strong correlation between a protocol plane (PON MAC) and a recombination plane, use a design scheme of shared cache, can adapt to all PON modes, simultaneously share the cache, effectively reduce the total cache usage amount, and simplify the complexity of service scheduling, thereby achieving better balance of performance and cost.
The main design concept is as follows: each PON port carries out normalized adaptation on the data frames output by the uplink PON MAC, so that each data frame in all EPON series modes is aligned with a GPON series mode in the attribute description of the fragments; according to the requirements of the current application scene, each PON port gates a PON mode; transmitting the data to a corresponding recombination cache in a multi-channel multiplexing mode; and the recombination cache performs data recombination on the data multiplexed and output by the channels and outputs the data to a service scheduling plane for service scheduling.
In the scheme, each PON port performs normalized adaptation on the data frame output by the uplink PON MAC, so that the uplink data can be structurally adapted to the same format in any PON mode, the same processing technology can be used for the data output by all PON MACs in subsequent data processing, the strong association between a protocol plane (PON MAC) and a recombination plane is decoupled, and the flexibility and the usability are improved. Meanwhile, through the selection of the PON mode and the data transmission mode of multiplexing of the multipath channel, the number of the recombination caches which are finally used can be greatly reduced, so that the idle of the recombination caches is effectively avoided, and the area of a chip is reduced; and the design scheme of sharing the recombined cache by a plurality of PON ports is favorable for balancing load of occupied cache resources among different PON ports, greatly reduces the quantity of scheduling source ports of a service scheduling plane, simplifies the complexity of service scheduling and meets the actual use requirement.
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
However, it should be noted that: the examples to be described next are only some specific examples, and are not intended to limit the embodiments of the present invention necessarily to the following specific steps, values, conditions, data, orders, and the like. Those skilled in the art can, upon reading this specification, utilize the concepts of the present invention to construct more embodiments than those specifically described herein.
Example one
The embodiment provides a method for frame recombination in an OLT, which is applied to the OLT with multiple PON ports. Referring to fig. 2, the OLT of the multi-mode multi-PON port includes N PON ports (N is a natural number greater than or equal to 2), and each PON port supports M different PON modes (M is a natural number greater than or equal to 2), where the different PON modes include, but are not limited to: EPON, 10G EPON, GPON, XGPON1, XGSON, etc. Referring to fig. 3, the method for frame reassembly in the OLT specifically includes the following steps:
step A, each PON port performs normalized adaptation on data frames output by the MAC of the uplink PON, so that each data frame under all EPON series modes (such as 1G EPON, 10G EPON and the like) is aligned with a GPON series mode (such as 1G GPON, XGSON and the like) on the attribute description of the fragments.
It can be understood that in order to use the same processing technology for the data output by all PON MACs in the subsequent data processing, a normalized adaptation operation needs to be performed on the data frames output by different PON MACs. In this embodiment, a fragmentation concept similar to the GPON series mode is designed to be established for ethernet frames output by PON MACs (e.g., EPON MAC, 10G EPON MAC) in the EPON series mode: the data frame in the GPON series mode may be cut into a plurality of fragments or a fragment (a complete data frame), while each data frame output in the EPON series mode is a complete data frame, which may be processed as a special case that the data frame in the GPON series mode is only cut into a fragment, and all the EPON series modes are aligned with the GPON series mode in the attribute description of the fragment.
Further, as an optional implementation manner, step a in this embodiment specifically includes the following operations:
(1) as shown in fig. 4, if the data frame output by the uplink PON MAC is a data frame in a GPON series mode, the data frame that is cut into multiple fragments is adapted to a first GPON encapsulation format, that is, theGPON encapsulation 1 in fig. 4; as shown in fig. 4, in the case of the GPON package 1: for data of a plurality of sequential gem _ start (gem frame data start indication) to gem _ end (gem frame data end indication) as non-last slices, data of a plurality of sequential fragment _ start (slice start indication) to fragment _ end (slice end indication) sequentially correspond, and at the same time, fragment _ valid (slice valid indication) corresponds to gem _ valid (gem frame data valid indication), and fragment _ lf (last slice indication) is invalid/low; for data from gem _ start to gem _ end as the last fragment, data from fragment _ start to fragment _ end corresponding to fragment _ lf being valid/high;
adapting a fragmented data frame (a complete data frame) to a second GPON encapsulation format, i.e.GPON encapsulation 2 in fig. 4; as shown in fig. 4, in the case of GPON package 2: and directly processing the fragment as the last fragment, wherein the data from the gem _ start to the gem _ end directly correspond to the data from the fragment _ start to the fragment _ end with fragment _ lf being effective/high, and fragment _ valid corresponds to the gem _ valid.
(2) As shown in fig. 4, if the data frame output by the uplink PON MAC is a data frame in an EPON series mode, the data frame is directly adapted to the second GPON encapsulation format, that is, theGPON encapsulation 2 in fig. 4, after lf (last fragment) information is added to the data frame. As shown in fig. 4, when the EPON is adapted to theGPON encapsulation 2, the fragment is treated as the last fragment, and the data from EPON _ frame _ start (EPON frame start indication) to EPON _ frame _ end (EPON frame end indication) directly corresponds to the data from fragment _ start to fragment _ end; meanwhile, fragment _ valid corresponds to epon _ frame _ valid (epon frame valid indication), and adds last fragment lf information that fragment _ lf (last fragment indication) is valid/high.
As can be seen from step a, since each PON port performs normalized adaptation on the data frames output by the uplink PON MAC, so that each data frame in all EPON series modes is aligned with a GPON series mode in the attribute description of the fragment, the data output by the uplink PON MAC in any PON mode can be structurally adapted to the same format (the first GPON encapsulation format or the second GPON encapsulation format), so that the same processing technique can be used for the data output by all PON MACs in subsequent data processing. In addition, the strong association between the protocol plane (PON MAC) and the recombination plane can be decoupled through the steps, so that the flexibility and the usability are improved.
B, according to the requirements of the current application scene, each PON port gates a PON mode; and the data is transmitted to the corresponding recombination cache in a multipath channel multiplexing mode.
It can be understood that each OLT PON port only works in one PON mode, and therefore, in actual application, the CPU can be operated to output configuration to gate a group of adapted PON data to be transmitted to a subsequent stage, that is, to gate one PON mode for data transmission, according to the requirements of an application scenario. Through mode selection, the data of M × N PON ports can be effectively reduced to the data of N PON ports, and the reduction of the subsequent recombination cache number is facilitated. On this basis, in order to further reduce the number of subsequent reassembly buffers, in this embodiment, a multi-channel multiplexing mode is further designed to transmit data to corresponding reassembly buffers, so that N PON port data can be further reduced to N/X, where X is the multiplexing number of the multi-channel multiplexing (that is, the X-channel PON port data is multiplexed to one-channel PON port data, and the contraction ratio of the corresponding channel multiplexing is X:1), and further, the number of reassembly buffers can be correspondingly reduced to N/X, thereby implementing a design of shared reassembly buffers, and facilitating balanced load of occupied buffer resources among different PON ports.
Further, as a preferred implementation manner, in step B of this embodiment, multiplexing of multiple channels may be implemented by increasing a clock frequency, widening a data bit width, or increasing a combination of the clock frequency and widening the data bit width.
Specifically, as an optional implementation manner, multiplexing of multiple channels is implemented by increasing a clock frequency, and a specific flow includes: under the condition of keeping the data bit width unchanged, the clock frequency input by the multiple PON ports is increased, and the source data of the multiple PON ports are combined into one PON data in an interleaving mode. It can be understood that, in actual operation, if it is desired to implement the X-path channel multiplexing and the clock frequency of each path in the X-path PON port is Y HZ, when the X-path channel multiplexing is implemented by increasing the clock frequency, the clock frequency after synthesizing one path should be greater than or equal to X × Y HZ. For example, taking the implementation of 4-way channel multiplexing by increasing the clock frequency as an example: as shown in fig. 5, under the condition of keeping the data bit width unchanged, the current 4 PON ports (PON0, PON1, PON2, PON3) are input by increasing the clock frequency to 4 × Y HZ or more, and source data (PON 0: P01, P00; PON 1: P11, P10; PON 2: P21, P20; PON 3: P31, P30) of the 4 PON ports are combined into one PON data (P31, P21, P11, P01, P30, P20, P10, P00) in an interleaving manner, so that the purpose of multiplexing the 4 channels into one channel is achieved.
As an optional implementation manner, the multiplexing of multiple channels is implemented by widening the data bit width, and the specific process includes: under the condition of keeping the clock frequency unchanged, source data of multiple PON ports are combined into one PON data path by widening the data bit width. It can be understood that, in actual operation, if it is desired to implement the X-path channel multiplexing, and each data bit width in the X-path PON port is L bit, when the X-path channel multiplexing is implemented by widening the data bit width, the data bit width after synthesizing one path is X × L bit. For example, the implementation of 4-way channel multiplexing by widening data bit width is taken as an example: as shown in fig. 6, under the condition of keeping the clock frequency unchanged, source data of the current 4 PON ports (PON 0: P01, P00; PON 1: P11, P10; PON 2: P21, P20; PON 3: P31, P30) are combined into one PON data path ({ P01, P11, P21, P31}, { P00, P10, P20, P30}) by expanding the data bit width to 4 × L bit, so that the purpose of multiplexing the 4 channels into one path is achieved.
As an optional implementation manner, multiplexing of multiple channels is implemented by a combination of increasing a clock frequency and widening a data bit width, and a specific flow includes: the clock frequency and the data bit width are simultaneously increased, source data of multiple PON ports are combined into one PON data path, the clock frequency after the PON data path is combined into one PON data path is greater than or equal to (X/Z) Y HZ, the data bit width is Z X L bit, wherein X is the multiplexing number of multiplexing of multiple channels, Z is the data bit width broadening coefficient, Y is the clock frequency of each PON port, and L is the data bit width of each PON port. For example, a mode of combining increasing the clock frequency and widening the data bit width to realize 4-way channel multiplexing is taken as an example: as shown in fig. 7, by increasing the clock frequency to (4/2) × yhz and widening the data bit width to 2 × L bit (where the number of multiplexed channels X is 4 and the data bit width widening coefficient Z is 2), the source data of the current 4 PON ports (PON 0: P01, P00; PON 1: P11, P10; PON 2: P21, P20; PON 3: P31, P30) are combined into one PON data ({ P21, P31}, { P01, P11}, { P20, P30}, { P00, P10}), thereby achieving the purpose of multiplexing the 4 channels into one channel.
Further, as a preferred embodiment, when the multiplexing number X of the multiplexing of the multiple channels is selected (that is, how many channels of PON port data are multiplexed into one channel of PON port data) in the multiplexing process of the multiple channels, comprehensive evaluation may be performed according to the limitations of the maximum clock frequency P supported by the system, the maximum input data bandwidth M supported by the reassembly buffer, and the maximum input data bit width Q supported by the reassembly buffer. Specifically, assuming that the maximum clock frequency limit supported by the system is pthz, the maximum input data bit width supported by the reassembly buffers is Q bit, and the maximum input data bandwidth supported by the reassembly buffers is M bit/s, the comprehensive evaluation is performed according to the following limiting conditions when the multiplexing path number X of the multipath channel multiplexing is selected:
1) when the multiplexing of multiple channels is realized by adopting a mode of increasing the clock frequency, the multiplexing is limited by the maximum clock frequency P supported by a system, namely X X Y < P, and Y is the clock frequency of each PON port; and the limitation of the maximum input data bandwidth M supported by the reassembly cache is limited, namely X Y L < M, wherein L is the data bit width of each PON port;
2) when the multiplexing of multiple channels is realized by adopting a mode of widening the data bit width, the multiplexing is limited by the limitation of the maximum input data bit width Q supported by the reorganization cache, namely X < L < Q; and a limit limited by the maximum input data bandwidth M supported by the reassembly cache, i.e., X Y L < M;
3) when the multiplexing of multiple channels is realized by combining the improvement of the clock frequency and the widening of the data bit width, the multiplexing is limited by the limitation of the maximum clock frequency P supported by a system, namely (X/Z) × Y < P, and Z is a data bit width widening coefficient; and limited by the limit of the maximum input data bit width Q supported by the reassembly cache, i.e., Z x L < Q; it is also limited by the limit of the maximum input data bandwidth M supported by the reassembly buffers, i.e., X Y L < M.
And step C, the recombination cache performs data recombination on the data multiplexed and output by the channels and outputs the data to a service scheduling plane for service scheduling.
It can be understood that, by selecting the mode in step B, the data of M × N PON ports can be effectively reduced to N PON port data, and by the data transmission manner of multiplexing the multiple channels in step B, the data of N PON ports can be further reduced to N/X, and further, the number of reassembly buffers can be correspondingly reduced to N/X. For example, if a scheme of multiplexing 2 channels into one channel is adopted, the number of the corresponding required reassembly buffers is N/2, as shown in fig. 2; if the scheme that 4 paths of channels are multiplexed into one path is adopted, the number of the corresponding needed recombination caches is N/4, and the number of the recombination caches corresponding to other multiplexing schemes can be calculated similarly.
Compared with the traditional scheme, the number of the recombination caches in the embodiment is greatly reduced, so that the idle of the recombination caches can be effectively avoided, and the chip area is reduced; moreover, the design of sharing and recombining the cache by a plurality of PON ports is beneficial to the balanced load of occupied cache resources among different PON ports; and the quantity of scheduling source ports of the service scheduling plane is greatly reduced, the complexity of service scheduling is simplified, and the actual use requirement is met.
Example two
Based on the same inventive concept, an embodiment of the present invention further provides a device for frame reassembly in an OLT, which is applied to an OLT in a multi-mode and multi-PON port, where the OLT in the multi-mode and multi-PON port includes N PON ports, and each PON port supports M different PON modes. Specifically, the apparatus for frame reassembly in the OLT includes: the device comprises N normalized adaptation units and N mode selection units, wherein each normalized adaptation unit and each mode selection unit correspond to a PON port; the system also comprises N/X channel multiplexing units and N/X recombination cache units, wherein X is the multiplexing path number of channel multiplexing, X PON ports correspond to one channel multiplexing unit, and one channel multiplexing unit corresponds to one recombination cache unit.
Wherein the normalized adaptation unit is configured to: and carrying out normalized adaptation on the data frames output by the MAC of the uplink PON, so that each data frame in all EPON series modes is aligned with the GPON series mode on the attribute description of the fragments. A mode selection unit to: and according to the requirements of the current application scene, gating a PON mode. A channel multiplexing unit to: and transmitting the gated PON mode data to the corresponding recombination buffer unit by adopting a multiplex channel multiplexing mode. A reassembly cache unit to: and carrying out data recombination on the data output by the channel multiplexing unit, and outputting the data to a service scheduling plane for service scheduling.
It can be seen from the above that, by using the apparatus of the embodiment, not only can the strong association between the protocol plane (PON MAC) and the reassembly plane be decoupled, thereby improving flexibility and usability, and making the designability stronger and the maintainability higher; moreover, the quantity of the recombination caches can be greatly reduced from the traditional M × N caches to N/X caches, so that the idle of the recombination caches is effectively avoided, and the chip area is reduced; in addition, the design scheme of sharing the recombination cache by using the multiple PON ports is beneficial to the balanced load of occupied cache resources among different PON ports, greatly reduces the quantity of scheduling source ports of a service scheduling plane, simplifies the complexity of service scheduling and meets the actual use requirement.
It should be noted that various changes and specific examples in the foregoing method embodiments are also applicable to the apparatus of the present embodiment, and the detailed description of the foregoing method is clear to those skilled in the art, so that the detailed description is omitted here for the sake of brevity.
Note that: the above-described embodiments are merely examples and are not intended to be limiting, and those skilled in the art can combine and combine some steps and devices from the above-described separately embodiments to achieve the effects of the present invention according to the concept of the present invention, and such combined and combined embodiments are also included in the present invention, and such combined and combined embodiments are not described herein separately.
Advantages, effects, and the like, which are mentioned in the embodiments of the present invention, are only examples and are not limiting, and they cannot be considered as necessarily possessed by the various embodiments of the present invention. Furthermore, the foregoing specific details disclosed herein are merely for purposes of example and for purposes of clarity of understanding, and are not intended to limit the embodiments of the invention to the particular details which may be employed to practice the embodiments of the invention.
The block diagrams of devices, apparatuses, systems involved in the embodiments of the present invention are only given as illustrative examples, and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by one skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably herein. As used in connection with embodiments of the present invention, the terms "or" and "refer to the term" and/or "and are used interchangeably herein unless the context clearly dictates otherwise. The word "such as" is used with respect to embodiments of the present invention is intended to mean, and is used interchangeably with, the word "such as but not limited to".
The flow charts of steps in the embodiments of the present invention and the above description of the methods are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As will be appreciated by those of skill in the art, the order of the steps in the above embodiments may be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. Furthermore, any reference to an element in the singular, for example, using the articles "a," "an," or "the" is not to be construed as limiting the element to the singular.
In addition, the steps and devices in the embodiments of the present invention are not limited to be implemented in a certain embodiment, and in fact, some steps and devices in the embodiments of the present invention may be combined according to the concept of the present invention to conceive new embodiments, and these new embodiments are also included in the scope of the present invention.
The respective operations in the embodiments of the present invention may be performed by any appropriate means capable of performing the corresponding functions. The means may include various hardware and/or software components and/or modules, including, but not limited to, hardware circuitry or a processor.
The method of an embodiment of the invention includes one or more acts for implementing the method described above. The methods and/or acts may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and/or use of specific actions may be modified without departing from the scope of the claims.
The functions in the embodiments of the present invention may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions on a tangible computer-readable medium. A storage media may be any available tangible media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other tangible medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk (disk) and Disc (Disc) include Compact Disc (CD), laser Disc, optical Disc, DVD (Digital Versatile Disc), floppy disk and blu-ray Disc where disks reproduce data magnetically, while discs reproduce data optically with lasers.
Accordingly, a computer program product may perform the operations presented herein. For example, such a computer program product may be a computer-readable tangible medium having instructions stored (and/or encoded) thereon that are executable by one or more processors to perform the operations described herein. The computer program product may include packaged material.
Other examples and implementations are within the scope and spirit of the embodiments of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard-wired, or any combination of these. Features implementing functions may also be physically located at various locations, including being distributed such that portions of functions are implemented at different physical locations.
Various changes, substitutions and alterations to the techniques described herein may be made by those skilled in the art without departing from the techniques of the teachings as defined by the appended claims. Moreover, the scope of the claims of the present disclosure is not limited to the particular aspects of the process, machine, manufacture, composition of matter, means, methods and acts described above. Processes, machines, manufacture, compositions of matter, means, methods, or acts, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or acts.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the invention to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof. And those not described in detail in this specification are within the skill of the art.

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