CN113097289A - Thin film transistor, preparation method thereof and array substrate - Google Patents

Abstract

The embodiment of the invention discloses a thin film transistor, a preparation method thereof and an array substrate, wherein the thin film transistor comprises the following components: a substrate; a semiconductor layer on one side of the substrate; a hydrogen element supply layer on a side of the semiconductor layer close to or remote from the substrate; the hydrogen element supply layer contains hydrogen; a barrier layer between the hydrogen element supply layer and the semiconductor layer; the barrier layer comprises a barrier region and at least two non-barrier regions, and the hydrogen element transmittance of the barrier region is lower than that of the non-barrier regions; wherein the hydrogen element supplying layer is for supplying a hydrogen element to the semiconductor layer through the non-barrier region to make the semiconductor layer conductive at a position corresponding to the non-barrier region. According to the technical scheme provided by the embodiment of the invention, the conductor of the channel region is reduced when the semiconductor source region and the semiconductor drain region are made into conductors, so that the effective channel length is not influenced, the requirement of a TFT (thin film transistor) device is further met, and the distribution uniformity of the TFT channel length on the array substrate is improved.

Description

Thin film transistor, preparation method thereof and array substrate

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a thin film transistor, a preparation method thereof and an array substrate.

Background

The array substrate comprises a plurality of Thin Film Transistors (TFT), and when the TFT is prepared, in order to ensure that a source electrode and a drain electrode in the TFT are in good contact with a semiconductor layer, reduce the lap-jointed impedance of the source electrode and the drain electrode and improve the performance of the TFT, the edge of the semiconductor layer is required to be subjected to conductor treatment on the contact position of the source electrode and the drain electrode.

In the prior art, the method of destroying chemical bonds in a semiconductor layer by using etching gas during etching a gate insulating layer or the method of ion implantation is used for realizing the conductor formation of a source region and a drain region of a semiconductor. However, in the prior art, after the edge conductor treatment of the semiconductor layer, etching gas diffuses to the channel region of the transistor, so that the effective channel length is narrowed, the requirement of a TFT device cannot be met, and the uniformity of the distribution of the TFT channel length on the array substrate is reduced.

Disclosure of Invention

The embodiment of the invention provides a thin film transistor, a preparation method thereof and an array substrate, which are used for reducing the conductor of a channel region when a source region and a drain region of a semiconductor are made into conductors, ensuring that the effective channel length is not influenced, further meeting the requirements of a TFT (thin film transistor) device and improving the distribution uniformity of the TFT channel length on the array substrate.

In a first aspect, an embodiment of the present invention provides a thin film transistor, including:

a substrate;

a semiconductor layer on one side of the substrate;

a hydrogen element supply layer on a side of the semiconductor layer close to or remote from the substrate; the hydrogen element supply layer contains hydrogen;

a barrier layer between the hydrogen element supply layer and the semiconductor layer; wherein the barrier layer comprises a barrier region and at least two non-barrier regions, the barrier region having a hydrogen element permeability that is lower than the hydrogen element permeability of the non-barrier regions; the vertical projection of the channel region of the semiconductor layer on the barrier layer is positioned in the barrier region;

wherein the hydrogen element supply layer is configured to supply a hydrogen element to the semiconductor layer through the non-barrier region to make a position of the semiconductor layer corresponding to the non-barrier region conductive.

Optionally, the barrier layer includes a first barrier sublayer, and a thickness of the first barrier sublayer of the non-barrier region is smaller than a thickness of the first barrier sublayer of the barrier region;

preferably, the material of the first barrier sublayer comprises aluminum oxide.

Optionally, the thickness of the first barrier sublayer of the non-barrier region is zero.

Optionally, the barrier layer further comprises a second barrier sublayer, the second barrier sublayer is located between the first barrier sublayer and the semiconductor layer, and the thickness of the second barrier sublayer is positively correlated with the hydrogen content in the hydrogen element supplying layer; the hydrogen element transmittance of the first barrier sublayer is lower than that of the second barrier sublayer;

preferably, the material of the second barrier sublayer comprises silicon oxide.

Optionally, the transistor further comprises a gate, a source and a drain; the hydrogen element supply layer is positioned on one side of the semiconductor layer close to the substrate;

the grid electrode is positioned on one side of the semiconductor layer far away from the substrate; a gate insulating layer is further arranged between the gate and the semiconductor layer; the side, far away from the substrate, of the grid further comprises an interlayer insulating layer, and the source electrode and the drain electrode are located on the side, far away from the substrate, of the interlayer insulating layer; the source electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a first via hole penetrating the interlayer insulating layer and the gate insulating layer, and the drain electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a second via hole penetrating the interlayer insulating layer and the gate insulating layer;

or the grid is positioned on one side of the hydrogen element supply layer close to the substrate; the gate insulating layer is further arranged between the gate and the hydrogen element supply layer, the interlayer insulating layer is further arranged on one side, away from the substrate, of the semiconductor layer, and the source electrode and the drain electrode are located on one side, away from the substrate, of the interlayer insulating layer; the source electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a first via hole penetrating the interlayer insulating layer, and the drain electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a second via hole penetrating the interlayer insulating layer.

Optionally, the transistor further comprises a gate, a source and a drain; the hydrogen element supply layer is positioned on one side of the semiconductor layer far away from the substrate;

the grid electrode is positioned on one side of the hydrogen element supply layer far away from the substrate; a gate insulating layer is further provided between the gate electrode and the hydrogen element supply layer; the side, far away from the substrate, of the grid further comprises an interlayer insulating layer, and the source electrode and the drain electrode are located on the side, far away from the substrate, of the interlayer insulating layer; the source electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a first via hole penetrating the interlayer insulating layer, the gate insulating layer, the hydrogen element supply layer, and the blocking layer, and the drain electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a second via hole penetrating the interlayer insulating layer, the gate insulating layer, the hydrogen element supply layer, and the blocking layer;

or the grid is positioned on one side of the semiconductor layer close to the substrate; the interlayer insulating layer is arranged between the grid electrode and the semiconductor layer; an interlayer insulating layer is further arranged between the semiconductor layer and the barrier layer, and the source electrode and the drain electrode are positioned on one side, away from the substrate, of the hydrogen element supply layer; the source electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a first via hole penetrating the hydrogen element supply layer, the barrier layer, and the interlayer insulating layer, and the drain electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a second via hole penetrating the hydrogen element supply layer, the barrier layer, and the interlayer insulating layer;

preferably, the vertical projection of the first via hole on the blocking layer is located in the non-blocking area, the edge distance between the vertical projection of the first via hole on the blocking layer and the edge distance between the vertical projection of the first via hole on the non-blocking area is greater than 0, the vertical projection of the second via hole on the blocking layer is located in the non-blocking area, and the edge distance between the vertical projection of the second via hole on the blocking layer and the edge distance between the vertical projection of the second via hole on the non-blocking area is greater than 0.

In a second aspect, an embodiment of the present invention provides a method for manufacturing a thin film transistor, including:

providing a substrate;

forming a semiconductor layer, wherein the semiconductor layer is positioned on one side of the substrate;

forming a hydrogen element supply layer on a side of the semiconductor layer close to or remote from the substrate; the hydrogen element supply layer contains hydrogen;

forming a barrier layer between the hydrogen element supplying layer and the semiconductor layer; wherein the barrier layer comprises a barrier region and at least two non-barrier regions, the barrier region having a hydrogen element permeability that is lower than the hydrogen element permeability of the non-barrier regions; the vertical projection of the channel region of the semiconductor layer on the barrier layer is positioned in the barrier region;

wherein the hydrogen element supply layer is configured to supply a hydrogen element to the semiconductor layer through the non-barrier region to make a position of the semiconductor layer corresponding to the non-barrier region conductive.

Optionally, the position of the semiconductor layer corresponding to the non-blocking region is made conductive, and the step of making the semiconductor layer corresponding to the non-blocking region includes:

the hydrogen element in the hydrogen element supplying layer is diffused from the non-barrier region of the barrier layer to the semiconductor layer by the thermal annealing process to make the position of the semiconductor layer corresponding to the non-barrier region conductive.

In a third aspect, an embodiment of the present invention provides an array substrate, including the thin film transistor in any one of the first aspect.

Optionally, the array substrate further includes a capacitor, a first electrode of the capacitor and the semiconductor layer in the thin film transistor are located in the same layer, and a second electrode of the capacitor and the gate electrode in the thin film transistor are located in the same layer;

at the capacitive location, the blocking layer includes a non-blocking region.

The embodiment of the invention provides a thin film transistor, a preparation method thereof and an array substrate, wherein hydrogen is provided for a semiconductor layer through a hydrogen supply layer so as to enable the semiconductor layer to be in a conductor state, a barrier layer is arranged between the hydrogen supply layer and the semiconductor layer, the barrier layer comprises a barrier region and at least two non-barrier regions, the hydrogen transmittance of the barrier region is lower than that of the non-barrier regions, and the hydrogen transmittance of the non-barrier regions is relatively high, so that when the semiconductor layer is in a conductor state, the position of the semiconductor layer corresponding to the non-barrier regions can receive more hydrogen and be in a conductor state; the barrier layer hydrogen permeability of the barrier region corresponding to the channel region of the semiconductor layer is low, so that when the semiconductor layer is subjected to semiconduction, hydrogen elements are not easy to enter the channel region of the semiconductor layer through the barrier layer, the channel region is not easy to be subjected to semiconduction, the semiconduction part of the semiconductor layer is limited through the barrier layer, the semiconduction of the channel region when the source region and the drain region of the semiconductor are subjected to semiconduction is reduced, the effective channel length is not influenced, the requirement of a TFT (thin film transistor) device is further met, and the distribution uniformity of the TFT channel length on the array substrate.

Drawings

Fig. 1 is a schematic structural diagram of a thin film transistor with a top gate structure provided in the prior art;

fig. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;

fig. 8 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;

fig. 9 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention;

fig. 10 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention;

fig. 11 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention;

fig. 12 is a schematic partial structure diagram of an array substrate according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

The thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode, a drain electrode, and the like. Thin film transistors can be classified into a top gate structure and a bottom gate structure. For example, fig. 1 is a schematic structural diagram of a thin film transistor having a top gate structure provided in the prior art, and referring to fig. 1, in the top gate structure, asemiconductor layer 40 is located on one side of asubstrate 10, agate insulating layer 50 is located on one side of thesemiconductor layer 40 away from thesubstrate 10, a gate G is located on one side of thegate insulating layer 50 away from thesubstrate 10, aninterlayer insulating layer 60 is located on one side of the gate G away from thesubstrate 10, and a source S and a drain D are located on one side of theinterlayer insulating layer 60 away from thesubstrate 10. The source electrode S and the drain electrode D are in contact with thesemiconductor layer 40 through the via hole. As described in the background art, during TFT manufacturing, in order to ensure that the source S and the drain D in the TFT are in good contact with thesemiconductor layer 40, reduce the resistance of the overlap joint of the source S and the drain D, and improve the performance of the TFT, a position (source region and drain region) where the edge of thesemiconductor layer 40 is in contact with the source and the drain needs to be subjected to a conductor processing.

In the prior art, for the top gate structure, the chemical bond inside the semiconductor layer can be destroyed by using the etching gas when thegate insulating layer 50 is etched, so that oxygen in the semiconductor layer is released, the content of oxygen vacancy is increased, and the semiconductor layer is made into a conductor. Or the material of the semiconductor layer can be hydrogenated or de-oxidized by means of ion implantation to achieve the electrical conductivity of the semiconductor. However, in the prior art, the semiconductor is made conductive by using a method of destroying chemical bonds in thesemiconductor layer 40 or an ion implantation method by using an etching gas when thegate oxide layer 50 is etched, and the etching gas diffuses into a channel region of a transistor during edge conduction processing of the semiconductor layer, so that the problem of conductive diffusion exists, the length B of the conductive region is increased, the effective channel length a is smaller than that of the gate G, the channel length a of each thin film transistor cannot be effectively controlled, and the uniformity of the distribution of the channel length of the TFT on the array substrate is reduced. The same problem exists with the bottom gate structure of the thin film transistor, and the description thereof is omitted.

In view of the above, an embodiment of the present invention provides a thin film transistor, and fig. 2 is a schematic structural diagram of the thin film transistor provided in the embodiment of the present invention, and referring to fig. 2, the thin film transistor includes:

asubstrate 10;

asemiconductor layer 40 on one side of thesubstrate 10;

a hydrogenelement supply layer 20, the hydrogenelement supply layer 20 being located on a side of thesemiconductor layer 40 close to or remote from thesubstrate 10; the hydrogenelement supply layer 20 contains hydrogen therein (the hydrogenelement supply layer 20 is exemplarily shown in fig. 2 to be located on the side of thesemiconductor layer 40 close to the substrate 10);

abarrier layer 30, thebarrier layer 30 being located between the hydrogenelement supplying layer 20 and thesemiconductor layer 40; wherein thebarrier layer 30 comprises a barrier region and at least two non-barrier regions, the hydrogen element permeability of the barrier region being lower than the hydrogen element permeability of the non-barrier regions; the channel region of thesemiconductor layer 40 is located within the barrier region at a vertical projection of thebarrier layer 30;

the hydrogenelement supply layer 20 is used to supply hydrogen element to thesemiconductor layer 40 through the non-barrier region to make thesemiconductor layer 40 conductive at a position corresponding to the non-barrier region.

Specifically, thesubstrate 10 of the thin film transistor may be made of a transparent material such as glass. Thesemiconductor layer 40 is located on one side of thesubstrate 10; thesemiconductor layer 40 is an active layer, and the material thereof may be an oxide semiconductor material, such as IGZO, ITZO, IZO. In order to ensure that the source S and the drain D in the thin film transistor are in good contact with thesemiconductor layer 40, reduce the impedance of the overlap joint of the source S and the drain D, and improve the performance of the thin film transistor, a position where the edge of thesemiconductor layer 40 is in contact with the source and the drain needs to be subjected to a conductor processing. The metal oxide in the thin film transistor needs to obtain at least two resistance regions, and the length of the large resistance region (corresponding to the non-blocking region) is used as the effective channel length a; the length of the small resistive region (corresponding to the blocking region) is the conductive region length B, which serves as a wire.

The thin film transistor is additionally provided with a hydrogenelement supplying layer 20 and abarrier layer 30. Wherein the hydrogenelement supplying layer 20 contains hydrogen, the hydrogenelement supplying layer 20 is located on the side of thesemiconductor layer 40 close to thesubstrate 10, or the hydrogenelement supplying layer 20 is located on the side of thesemiconductor layer 40 away from thesubstrate 10. That is, the hydrogenelement supply layer 20 may be positioned on the side of thesemiconductor layer 40 close to or far from thesubstrate 10, and it is sufficient that hydrogen contained in the hydrogenelement supply layer 20 diffuses into thesemiconductor layer 40 to convert thesemiconductor layer 40 into a conductor. Thesemiconductor layer 40 may be made conductive at a position in contact with the source S and the drain D of the thin film transistor. Therefore, abarrier layer 30 is provided between the hydrogenelement supplying layer 20 and thesemiconductor layer 40, and thebarrier layer 30 includes a barrier region and at least two non-barrier regions, and the hydrogen element permeability of the barrier region is lower than that of the non-barrier regions. The channel region of thesemiconductor layer 40 is located in the blocking region in the vertical projection of theblocking layer 30, which may be in the thickness direction of the thin film transistor, and the blocking region of theblocking layer 30 covers the channel region of thesemiconductor layer 40, wherein the area of the blocking region of theblocking layer 30 may be greater than or equal to the area of the channel region of the semiconductor layer. Thesemiconductor layer 40 is made conductive at a position corresponding to the non-barrier region, and thesemiconductor layer 40 is not made conductive at a position corresponding to the barrier region. In the thickness direction of the thin film transistor, the size of the blocking region of theblocking layer 30 may correspond to the size of the gate of the thin film transistor, so that the length of the effective channel region may be closer to the size of the gate after the step of semiconducting the semiconductor layer. Optionally, the material of thebarrier layer 30 may be alumina with good compactness, so as to ensure that the hydrogen permeability of the barrier region of thebarrier layer 30 is low. The material of the hydrogenelement supplying layer 20 may be silicon nitride. The raw material for forming silicon nitride includes hydrogen element, and thus hydrogen element remains in silicon nitride. The hydrogen in the hydrogenelement supply layer 20 may be diffused from the non-barrier region of the alumina to the oxide semiconductor based on the annealing process, thereby lowering the resistance of the oxide semiconductor at the non-barrier region of the alumina, and achieving the electrical conduction of the oxide semiconductor thereat.

It should be noted that the thin film transistor provided in the embodiment of the present invention may also be a top gate structure or a bottom gate structure. For a top gate structure, the hydrogenelement supply layer 20 may be located on a side of thesemiconductor layer 40 closer to or farther from thesubstrate 10; it is sufficient that thebarrier layer 30 is located between the hydrogenelement supply layer 20 and the semiconductor layer 40 (the specific structure is shown in fig. 2 and fig. 6 of the following embodiments, where the hydrogenelement supply layer 20 is exemplarily shown on the side of thesemiconductor layer 40 close to thesubstrate 10 in fig. 2, and the hydrogenelement supply layer 20 is exemplarily shown on the side of thesemiconductor layer 40 away from thesubstrate 10 in fig. 6). For a bottom gate structure, the hydrogenelement supply layer 20 may be located on a side of thesemiconductor layer 40 closer to or farther from the substrate 10 (the specific structure is referred to fig. 5 and 7 of the following embodiments; the hydrogenelement supply layer 20 is exemplarily shown on a side of thesemiconductor layer 40 closer to thesubstrate 10 in fig. 5, and the hydrogenelement supply layer 20 is exemplarily shown on a side of thesemiconductor layer 40 farther from thesubstrate 10 in fig. 7); thebarrier layer 30 may be located between the hydrogenelement supplying layer 20 and thesemiconductor layer 40. Thebarrier layer 30 includes a barrier region and at least two non-barrier regions, and the barrier region has a lower hydrogen element permeability than the non-barrier regions. Because the hydrogen element transmittance of the non-blocking area is relatively high, when the semiconductor layer is subjected to semiconduction, the position of the semiconductor layer corresponding to the non-blocking area can receive more hydrogen elements and be subjected to semiconduction; the barrier layer hydrogen permeability of the barrier region corresponding to the channel region of the semiconductor layer is low, so that when the semiconductor layer is subjected to semiconduction, hydrogen elements are not easy to enter the channel region of the semiconductor layer through the barrier layer, the channel region is not easy to be subjected to semiconduction, the semiconduction part of the semiconductor layer is limited through the barrier layer, the semiconduction of the channel region when the source region and the drain region of the semiconductor layer are subjected to semiconduction is reduced, the control of the effective channel length is realized, the effective channel length is not influenced by the semiconduction of the source region and the drain region of the semiconductor layer, the requirements of a TFT device are further met, and the uniformity of the distribution of.

With continued reference to fig. 2, optionally, thebarrier layer 30 includes a first barrier sublayer 31, the thickness h2 of the first barrier sublayer 31 of the non-barrier region being less than the thickness h1 of the first barrier sublayer 31 of the barrier region.

Specifically, thebarrier layer 30 located between the hydrogenelement supplying layer 20 and thesemiconductor layer 40 includes the first barrier sublayer 31, and in a direction perpendicular to thesubstrate 10, the thickness h2 of the first barrier sublayer 31 in the non-barrier region of the first barrier sublayer 31 is smaller than the thickness h1 of the first barrier sublayer 31 in the barrier region, and the thickness of the first barrier sublayer 31 has a negative correlation with the hydrogen element transmittance. The smaller the thickness of the first barrier sublayer 31, the greater the hydrogen element transmittance; the greater the thickness of the first barrier sublayer 31, the smaller the hydrogen element transmittance. The thickness h2 of the first barrier sublayer 31 of the non-barrier region of the first barrier sublayer 31 is smaller than the thickness h1 of the first barrier sublayer 31 of the barrier region, so that the hydrogen element transmittance of the barrier region is lower than that of the non-barrier region, the conductor part of thesemiconductor layer 40 is limited by thebarrier layer 30, the problem of conductor diffusion is solved, the effective channel length A can be controlled by setting the range of the barrier region and the non-barrier region, and the uniformity of the distribution of the TFT channel length on the array substrate can be improved.

Optionally, the material of the first barrier sublayer 31 comprises aluminum oxide. A layer of aluminum may be formed and patterned such that the thickness h2 of the first barrier sublayer 31 of the non-barrier region is less than the thickness h1 of the first barrier sublayer 31 of the barrier region to define the non-barrier and barrier regions of thebarrier layer 30. The aluminum layer is then oxidized to form dense aluminum oxide by natural oxidation or "oxygen" containing plasma treatment, or annealing in an "oxygen" containing atmosphere.

Fig. 3 is a schematic structural diagram of another tft according to an embodiment of the present invention, and referring to fig. 3, optionally, the thickness of the first barrier sublayer 31 in the non-barrier region is zero.

Specifically, the thickness of the first barrier sublayer 31 in the non-barrier region is zero, that is, the first barrier sublayer 31 forms an opening in the non-barrier region. By the annealing process, hydrogen in the hydrogenelement supply layer 20 is diffused from the opening of the first barrier sublayer 31 to thesemiconductor layer 40, so that the resistance of the oxide semiconductor at the opening of the alumina is lowered, and the conductivity of the oxide semiconductor is achieved there. The first barrier sublayer 31 forms an opening in the non-barrier region, maximizes the transmittance of hydrogen in the hydrogenelement supply layer 20 in the non-barrier region, accelerates the speed of conductor formation of thesemiconductor layer 40, and reduces the material and cost for manufacturing the thin film transistor.

Fig. 4 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention, and referring to fig. 4, optionally, thebarrier layer 30 further includes a second barrier sublayer 32, the second barrier sublayer 32 is located between the first barrier sublayer 31 and thesemiconductor layer 40, and the thickness of the second barrier sublayer 32 is positively correlated to the hydrogen content in the hydrogenelement supplying layer 20; the hydrogen element transmittance of the first barrier sublayer 31 is lower than that of the second barrier sublayer 32.

Specifically, thebarrier layer 30 includes a first barrier sublayer 31, and the thickness of the first barrier sublayer 31 of the non-barrier region is smaller than the thickness of the first barrier sublayer 31 of the barrier region. By providing different thicknesses of the first barrier sublayer 31 at different locations, non-barrier and barrier regions of thebarrier layer 30 are defined. Thebarrier layer 30 further comprises a second barrier sublayer 32, the second barrier sublayer 32 being located between the first barrier sublayer 31 and thesemiconductor layer 40. The hydrogen element transmittance of the first barrier sublayer 31 is lower than that of the second barrier sublayer 32, and the thickness of the second barrier sublayer 32 is positively correlated with the hydrogen content in the hydrogenelement supply layer 20. If the hydrogen content in the hydrogenelement supply layer 20 is large, the total amount of hydrogen diffused from the hydrogenelement supply layer 20 into thesemiconductor layer 40 is large, which may cause the amount of hydrogen supplied into the hydrogenelement supply layer 20 to be larger than the amount of hydrogen required for the portion of thesemiconductor layer 40 to be conducted, and hydrogen to be diffused from the position of thesemiconductor layer 40 corresponding to the non-barrier region to the position of thesemiconductor layer 40 corresponding to the barrier region. The amount of hydrogen diffused into thesemiconductor layer 40 can be limited by the second barrier sublayer 32, so that the condition of conductor diffusion is further improved, the effective channel length can be controlled, and the uniformity of the distribution of the TFT channel length a on the array substrate is further improved.

Optionally, the material of the second barrier sublayer 32 includes silicon oxide, and the material of the first barrier sublayer 31 includes aluminum oxide, which satisfies that the hydrogen element transmittance of the first barrier sublayer 31 is lower than the hydrogen element transmittance of the second barrier sublayer 32. The silicon oxide satisfies both the condition of not affecting the conductor formation at the position of thesemiconductor layer 40 corresponding to the non-barrier region and the condition of adjusting the hydrogen content at the position of thesemiconductor layer 40 corresponding to the non-barrier region.

Optionally, referring to fig. 2 to 4, the thin film transistor further includes a gate G, a source S, and a drain D; the hydrogenelement supply layer 20 is located on the side of thesemiconductor layer 40 close to thesubstrate 10; the grid is positioned on one side of thesemiconductor layer 40 far away from thesubstrate 10; agate insulating layer 50 is further included between the gate electrode and thesemiconductor layer 40; the side of the gate away from thesubstrate 10 further includes an interlayer insulatinglayer 60, and the source S and the drain D are located on the side of the interlayer insulatinglayer 60 away from thesubstrate 10; the source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a first via hole penetrating theinterlayer insulating layer 60 and thegate insulating layer 50, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a second via hole penetrating theinterlayer insulating layer 60 and thegate insulating layer 50.

Specifically, the thin film transistor further includes a gate electrode G, a source electrode S, and a drain electrode D, the thin film transistor is of a top gate structure, and the hydrogenelement supply layer 20 is located on the side of thesemiconductor layer 40 close to thesubstrate 10. At this time, the hydrogenelement supply layer 20 is located on one side of thesubstrate 10, and covers thesubstrate 10. Thebarrier layer 30 is located on the side of the hydrogenelement supplying layer 20 away from thesubstrate 10, and covers the hydrogenelement supplying layer 20. Thebarrier layer 30 is patterned to vary the thickness of thebarrier layer 30 at different locations to define a barrier region and at least two non-barrier regions of thebarrier layer 30. The blocking region is located between two non-blocking regions. By setting the thickness of thebarrier layer 30 in which the thickness of the non-barrier region is smaller than the thickness of the barrier region, the hydrogen element transmittance of the barrier region is lower than that of the non-barrier region, and the portion of thesemiconductor layer 40 to be conducted is defined by thebarrier layer 30. Thesemiconductor layer 40 is located on a side of thebarrier layer 30 remote from thesubstrate 10 and covers thebarrier layer 30.

Thegate insulating layer 50 is positioned between the gate electrode and thesemiconductor layer 40. Thegate insulating layer 50 is located on a side of thesemiconductor layer 40 away from thesubstrate 10 and covers thesemiconductor layer 40. The gate electrode is located on a side of thegate insulating layer 50 away from thesubstrate 10 and covers thegate insulating layer 50, and thegate insulating layer 50 is used for isolating the contact between the gate electrode and thesemiconductor layer 40. The gate metal layer is patterned so that a gate G can be formed at the gate location. The projection of the gate G on thebarrier layer 30 is located in the barrier region of thebarrier layer 30. The side of the gate G away from thesubstrate 10 is further covered with an interlayer insulatinglayer 60, the source S and the drain D are located on the side of the interlayer insulatinglayer 60 away from thesubstrate 10, and the interlayer insulatinglayer 60 is used for isolating the gate from the source S and the drain D. The thin film transistor further includes a first via hole penetrating theinterlayer insulating layer 60 and thegate insulating layer 50 and a second via hole penetrating theinterlayer insulating layer 60 and thegate insulating layer 50, the source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through the first via hole penetrating theinterlayer insulating layer 60 and thegate insulating layer 50, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through the second via hole penetrating theinterlayer insulating layer 60 and thegate insulating layer 50. Thereby connecting the source S and drain D to the conductive positions of thesemiconductor layer 40.

Referring to fig. 5, optionally, the thin film transistor further includes a gate electrode G, a source electrode S, and a drain electrode D; the hydrogenelement supply layer 20 is located on the side of thesemiconductor layer 40 close to thesubstrate 10; the gate G is located on the side of the hydrogenelement supplying layer 20 close to thesubstrate 10; agate insulating layer 50 is further provided between the gate G and the hydrogenelement supply layer 20, aninterlayer insulating layer 60 is further provided on the side of thesemiconductor layer 40 away from thesubstrate 10, and the source S and the drain D are provided on the side of the interlayer insulatinglayer 60 away from thesubstrate 10; the source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a first via hole penetrating theinterlayer insulating layer 60, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a second via hole penetrating theinterlayer insulating layer 60.

Specifically, the thin film transistor further includes a gate electrode G, a source electrode S, and a drain electrode D, the thin film transistor is of a bottom gate structure, and the hydrogenelement supply layer 20 is located on the side of thesemiconductor layer 40 close to thesubstrate 10. At this time, the gate G is positioned at one side of thesubstrate 10 and covers thesubstrate 10. A gate metal layer is formed on thesubstrate 10 and patterned so that a gate G may be formed at the gate position. The projection of the gate on the subsequently formedbarrier layer 30 is located in the barrier region of thebarrier layer 30. Agate insulating layer 50 is disposed on a side of the gate G away from thesubstrate 10 and covers the gate and thesubstrate 10 uncovered by the gate. The hydrogenelement supplying layer 20 is located on the side of thegate insulating layer 50 away from thesubstrate 10, and covers thegate insulating layer 50. Thebarrier layer 30 is located on the side of the hydrogenelement supplying layer 20 away from thesubstrate 10, and covers the hydrogenelement supplying layer 20. Thebarrier layer 30 is patterned to vary the thickness of thebarrier layer 30 at different locations to define a barrier region and at least two non-barrier regions of thebarrier layer 30. The blocking region is located between two non-blocking regions. By setting the thickness of thebarrier layer 30 in which the thickness of the non-barrier region is smaller than the thickness of the barrier region (the thickness of the barrier layer of the non-barrier region in fig. 5 is 0), the hydrogen element transmittance of the barrier region is lower than that of the non-barrier region, and the portion of thesemiconductor layer 40 to be a conductor is defined by thebarrier layer 30. Thesemiconductor layer 40 is located on a side of thebarrier layer 30 remote from thesubstrate 10 and covers thebarrier layer 30.

The side of thesemiconductor layer 40 away from thesubstrate 10 is further covered with an interlayer insulatinglayer 60, the source S and the drain D are located on the side of the interlayer insulatinglayer 60 away from thesubstrate 10, and the interlayer insulatinglayer 60 is used for isolating the gate from the source S and the drain D. And further includes a first via hole penetrating theinterlayer insulating layer 60 and a second via hole penetrating theinterlayer insulating layer 60, the source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through the first via hole penetrating theinterlayer insulating layer 60, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through the second via hole penetrating theinterlayer insulating layer 60. Thereby connecting the source S and drain D to the conductive positions of thesemiconductor layer 40.

Referring to fig. 6, optionally, the thin film transistor further includes a gate electrode G, a source electrode S, and a drain electrode D; the hydrogenelement supply layer 20 is located on the side of thesemiconductor layer 40 away from thesubstrate 10; the gate G is located on the side of the hydrogenelement supply layer 20 away from thesubstrate 10; agate insulating layer 50 is further provided between the gate electrode and the hydrogenelement supply layer 20; the side of the gate G away from thesubstrate 10 further includes an interlayer insulatinglayer 60, and the source S and the drain D are located on the side of the interlayer insulatinglayer 60 away from thesubstrate 10; the source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a first via hole penetrating theinterlayer insulating layer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a second via hole penetrating theinterlayer insulating layer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30.

Specifically, the thin film transistor further comprises a gate G, a source S and a drain D; the thin film transistor is of a top gate structure, and the hydrogenelement supply layer 20 is located on the side of thesemiconductor layer 40 remote from thesubstrate 10. At this time, thesemiconductor layer 40 is positioned at one side of thesubstrate 10 and covers thesubstrate 10. Thebarrier layer 30 is located on a side of thesemiconductor layer 40 remote from thesubstrate 10 and covers thesemiconductor layer 40. Thebarrier layer 30 is patterned to vary the thickness of thebarrier layer 30 at different locations to define a barrier region and at least two non-barrier regions of thebarrier layer 30. The blocking region is located between two non-blocking regions. Thehydrogen donor layer 20 is located on the side of thebarrier layer 30 remote from thesubstrate 10 and covers thebarrier layer 30. The hydrogenelement supply layer 20 serves to supply a hydrogen element to thesemiconductor layer 40 through the non-barrier region to make thesemiconductor layer 40 conductive at a position corresponding to the non-barrier region. By providing thebarrier layer 30 in which the thickness of the non-barrier region is smaller than the thickness of the barrier region (the thickness of the non-barrier region in fig. 6 is 0), the hydrogen element transmittance of the barrier region is lower than that of the non-barrier region, and the portion of thesemiconductor layer 40 to be a conductor is defined by thebarrier layer 30.

The side of the hydrogenelement supply layer 20 remote from thesubstrate 10 is also covered with agate insulating layer 50. The gate is located on a side of thegate insulating layer 50 away from thesubstrate 10 and covers thegate insulating layer 50. A gate metal layer may be formed on thegate insulating layer 50 and patterned so that a gate may be formed at the gate position. The projection of the gate on thebarrier layer 30 is located in the barrier region of thebarrier layer 30. The gate G further includes an interlayer insulatinglayer 60 on a side away from thesubstrate 10, and the interlayer insulatinglayer 60 covers the gate G and the hydrogenelement supply layer 20 not covered by the gate G. The source S and the drain D are located on a side of the interlayer insulatinglayer 60 away from thesubstrate 10. A first via hole penetrating theinterlayer insulating layer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30, and a second via hole penetrating theinterlayer insulating layer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30 are also included. The source S is electrically connected to thesemiconductor layer 40 corresponding to the non-barrier region through a first via hole penetrating theinterlayer insulating layer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30, and the drain D is electrically connected to thesemiconductor layer 40 corresponding to the non-barrier region through a second via hole penetrating theinterlayer insulating layer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30, whereby the source S and the drain D are connected to the portion of thesemiconductor layer 40 corresponding to the conductor. In the process of manufacturing the thin film transistor having such a structure, it is necessary to diffuse hydrogen in the hydrogenelement supply layer 20 to theconductive semiconductor layer 40 in thesemiconductor layer 40 based on an annealing process, and then to provide the first via hole and the second via hole to connect the source/drain D to thesemiconductor layer 40.

Referring to fig. 7, optionally, the thin film transistor further includes a gate electrode G, a source electrode S, and a drain electrode D; the hydrogenelement supply layer 20 is located on the side of thesemiconductor layer 40 away from thesubstrate 10; the grid is positioned on one side of thesemiconductor layer 40 close to thesubstrate 10; aninterlayer insulating layer 60 is further included between the gate electrode and thesemiconductor layer 40; aninterlayer insulating layer 60 is further included between thesemiconductor layer 40 and thebarrier layer 30, and the source electrode S and the drain electrode D are located on the side of the hydrogenelement supply layer 20 away from thesubstrate 10; the source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-barrier region through a first via hole penetrating the hydrogenelement supply layer 20, thebarrier layer 30, and the interlayer insulatinglayer 60, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-barrier region through a second via hole penetrating the hydrogenelement supply layer 20, thebarrier layer 30, and the interlayer insulatinglayer 60.

Specifically, the thin film transistor further comprises a gate G, a source S and a drain D; the thin film transistor is of a bottom gate structure, and the hydrogenelement supply layer 20 is located on the side of thesemiconductor layer 40 remote from thesubstrate 10. At this time, the gate G is positioned at one side of thesubstrate 10 and covers thesubstrate 10. A gate metal layer is formed on thesubstrate 10 and patterned so that a gate can be formed at the gate location. The projection of the gate G on the subsequently formedbarrier layer 30 is located in the barrier region of thebarrier layer 30. Agate insulating layer 50 is disposed on a side of the gate away from thesubstrate 10, and thegate insulating layer 50 covers the gate G and thesubstrate 10 not covered by the gate G. Thesemiconductor layer 40 is located on a side of thegate insulating layer 50 away from thesubstrate 10 and covers thesemiconductor layer 40. An interlayer insulatinglayer 60 is further provided on the side of thesemiconductor layer 40 remote from thesubstrate 10, and the interlayer insulatinglayer 60 covers thesemiconductor layer 40. Thebarrier layer 30 is located on a side of the interlayer insulatinglayer 60 away from thesubstrate 10, and covers theinterlayer insulating layer 60. Thebarrier layer 30 is patterned to vary the thickness of thebarrier layer 30 at different locations to define a barrier region and at least two non-barrier regions of thebarrier layer 30. The blocking region is located between two non-blocking regions.

Thehydrogen donor layer 20 is located on the side of thebarrier layer 30 remote from thesubstrate 10 and covers thebarrier layer 30. The hydrogenelement supply layer 20 serves to supply a hydrogen element to thesemiconductor layer 40 through the non-barrier region to make thesemiconductor layer 40 conductive at a position corresponding to the non-barrier region. By setting the thickness of thebarrier layer 30 in which the thickness of the non-barrier region is smaller than the thickness of the barrier region (the thickness of the non-barrier region of thebarrier layer 30 in fig. 7 is 0), and setting the thickness of the non-barrier region corresponding to theinterlayer insulating layer 60 to be smaller than the thickness of the barrier region (the thickness of the non-barrier region of the interlayer insulatinglayer 60 in fig. 7 is 0). Thereby realizing that the hydrogen element permeability of the barrier region is lower than that of the non-barrier region, and further, the conductor portion of thesemiconductor layer 40 is defined by thebarrier layer 30. The source S and the drain D are located on the side of the hydrogenelement supplying layer 20 away from thesubstrate 10. A first via is also included through thehydrogen donor layer 20 and thebarrier layer 30, and a second via is included through thehydrogen donor layer 20 and thebarrier layer 30. The source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-barrier region through a first via hole penetrating the hydrogenelement supply layer 20 and thebarrier layer 30, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-barrier region through a second via hole penetrating the hydrogenelement supply layer 20 and thebarrier layer 30, whereby the source electrode S and the drain electrode D are connected to the portion of thesemiconductor layer 40 corresponding to the conductor. In the process of manufacturing the thin film transistor having such a structure, it is also necessary to diffuse hydrogen in the hydrogenelement supply layer 20 to theconductive semiconductor layer 40 in thesemiconductor layer 40 by an annealing process, and then to provide the first via hole and the second via hole to connect the source/drain D to thesemiconductor layer 40.

Optionally, the vertical projection of the first via hole on thebarrier layer 30 is located in the non-blocking region, the edge distance between the vertical projection of the first via hole on thebarrier layer 30 and the edge of the non-blocking region where the vertical projection of the first via hole is located is greater than 0, the vertical projection of the second via hole on thebarrier layer 30 is located in the non-blocking region, and the edge distance between the vertical projection of the second via hole on thebarrier layer 30 and the edge of the non-blocking region where the vertical projection of the second via hole is located is greater than 0. To avoid contact with thebarrier layer 30 when the source S is connected to the conductive portion of thesemiconductor layer 40 through the first via; and preventing the drain electrode D from contacting thebarrier layer 30 when connected to the conductive portion of thesemiconductor layer 40 through the second via hole, thereby preventing thebarrier layer 30 from being a conductive material, which may affect the operating characteristics of the thin film transistor.

With continued reference to fig. 2-7, compared with the prior art, the thin film transistor structure provided by the above embodiment of the present invention does not need to etch the gate insulating layer to implement the conductor formation of the semiconductor layer, and the manufacturing process is simpler.

The embodiment of the invention provides a preparation method of a thin film transistor, which comprises the following steps:

providing a substrate;

forming a semiconductor layer, wherein the semiconductor layer is positioned on one side of the substrate;

forming a barrier layer between the hydrogen element supply layer and the semiconductor layer; the barrier layer comprises a barrier region and at least two non-barrier regions, and the hydrogen element transmittance of the barrier region is lower than that of the non-barrier regions; the vertical projection of the channel region of the semiconductor layer on the barrier layer is positioned in the barrier region;

forming a hydrogen element supply layer on a side of the semiconductor layer close to or far from the substrate; the hydrogen element supply layer contains hydrogen;

wherein the hydrogen element supplying layer is for supplying a hydrogen element to the semiconductor layer through the non-barrier region to make the semiconductor layer conductive at a position corresponding to the non-barrier region.

In the method for manufacturing a thin film transistor according to this embodiment, it is sufficient to ensure that the step of forming the barrier layer is located between the steps of forming the hydrogen element supply layer and forming the semiconductor layer, and the order of forming the semiconductor layer and forming the hydrogen element supply layer may be adjusted according to the actually required structure of the thin film transistor, which is not specifically limited herein.

According to the technical scheme provided by the embodiment of the invention, hydrogen is provided for the semiconductor layer through the hydrogen supply layer so as to make the semiconductor layer become conductive, the barrier layer is arranged between the hydrogen supply layer and the semiconductor layer and comprises the barrier region and at least two non-barrier regions, and the hydrogen transmittance of the barrier region is lower than that of the non-barrier regions, so that the channel region is not easy to become conductive, the semiconductor part of the semiconductor layer is limited through the barrier layer, the semiconductor of the channel region is reduced when the semiconductor source region and the semiconductor drain region are made conductive, the effective channel length is closer to the length of the grid electrode, the requirement of a TFT device is further met, and the uniformity of the distribution of the TFT channel length on the array substrate is improved.

Fig. 8 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention, which can be used to manufacture the thin film transistor shown in fig. 3; referring to fig. 8, the method of fabricating the thin film transistor includes:

and S110, providing a substrate.

S120, depositing a hydrogen element supply layer on the substrate, wherein the hydrogen element supply layer contains hydrogen; the barrier layer comprises a barrier region and at least two non-barrier regions, and the hydrogen element transmittance of the barrier region is lower than that of the non-barrier regions.

Specifically, the material of the hydrogenelement supply layer 20 may be silicon nitride. The raw material for forming silicon nitride includes hydrogen element, and thus hydrogen element remains in silicon nitride.

And S130, forming a barrier layer, wherein the barrier layer is positioned on one side of the hydrogen element supply layer far away from the substrate.

Specifically, an aluminum layer is formed on the hydrogenelement supplying layer 20, and the aluminum layer is patterned such that the thickness of the first barrier sublayer of the non-barrier region is smaller than the thickness of the first barrier sublayer of the barrier region, thereby defining the non-barrier region and the barrier region of thebarrier layer 30. The aluminum layer is then oxidized to form dense aluminum oxide by natural oxidation or "oxygen" containing plasma treatment, or annealing in an "oxygen" containing atmosphere.

Optionally, thebarrier layer 30 includes a first barrier sublayer, and a thickness of the first barrier sublayer of the non-barrier region is smaller than a thickness of the first barrier sublayer of the barrier region. By providing different thicknesses of the first barrier sublayer at different locations, non-barrier and barrier regions of thebarrier layer 30 are defined. Optionally, thebarrier layer 30 may further include a second barrier sublayer, which is located between the first barrier sublayer and thesemiconductor layer 40. The hydrogen element permeability of the first barrier sublayer is lower than that of the second barrier sublayer, and the thickness of the second barrier sublayer is positively correlated with the hydrogen content in the hydrogenelement supply layer 20. The amount of hydrogen diffused into thesemiconductor layer 40 can be limited by the second barrier sublayer, so that the condition of conductor diffusion is further improved, the effective channel length can be controlled, and the uniformity of the distribution of the TFT channel length on the array substrate is further improved.

S140, forming a semiconductor layer, wherein the semiconductor layer is positioned on one side of the barrier layer, which is far away from the substrate; wherein the hydrogen element supplying layer is used for supplying hydrogen elements to the semiconductor layer through the non-barrier region to make the position of the semiconductor layer corresponding to the non-barrier region conductive, and the vertical projection of the channel region of the semiconductor layer on the barrier region is positioned in the barrier region.

Specifically, thesemiconductor layer 40 is formed on the side of thebarrier layer 30 away from thesubstrate 10, and the hydrogenelement supply layer 20 supplies hydrogen element to thesemiconductor layer 40 through the non-barrier region to make thesemiconductor layer 40 conductive at a position corresponding to the non-barrier region.

And S150, sequentially forming a grid electrode insulating layer, a grid electrode layer, an interlayer insulating layer and a source drain electrode on the semiconductor layer.

Specifically, thegate insulating layer 50 is located between the gate electrode and thesemiconductor layer 40. The gate metal layer is patterned so that a gate can be formed over the gate location. The projection of the gate on thebarrier layer 30 is located in the barrier region of thebarrier layer 30. The interlayer insulatinglayer 60 serves to isolate the gate from the source S and drain D contacts. First and second via holes are formed, both penetrating theinterlayer insulating layer 60 and thegate insulating layer 50. A source S and a drain D are formed on theinterlayer insulating layer 60 at a side away from thesubstrate 10. The source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a first via hole penetrating theinterlayer insulating layer 60 and thegate insulating layer 50, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a second via hole penetrating theinterlayer insulating layer 60 and thegate insulating layer 50. Thereby connecting the source S and drain D to the conductive positions of thesemiconductor layer 40.

Alternatively, the position of thesemiconductor layer 40 corresponding to the non-barrier region may be rendered conductive by diffusing the hydrogen element in the hydrogenelement supply layer 20 from the non-barrier region of thebarrier layer 30 to thesemiconductor layer 40 by a thermal annealing process to render the position of thesemiconductor layer 40 corresponding to the non-barrier region conductive. The thermal annealing process may be performed before the first via and the second via are formed, or may be performed after the first via and the second via are formed.

Fig. 9 is a flowchart of another method for manufacturing a thin film transistor, which can be used to manufacture the thin film transistor shown in fig. 5, according to an embodiment of the present invention; referring to fig. 9, the method of fabricating the thin film transistor includes:

s210, providing a substrate.

And S220, sequentially forming a grid electrode and a grid electrode insulating layer on the substrate.

S230, forming a hydrogen element supply layer on one side, far away from the substrate, of the gate insulation layer; the hydrogenelement supply layer 20 contains hydrogen; the barrier layer comprises a barrier region and at least two non-barrier regions, and the hydrogen element transmittance of the barrier region is lower than that of the non-barrier regions.

And S240, forming a barrier layer, wherein the barrier layer is positioned on one side of the hydrogen element supply layer far away from the substrate.

Specifically, thebarrier layer 30 may also include a first barrier sublayer and a second barrier sublayer, which are not described in detail herein.

S250, forming a semiconductor layer, wherein the semiconductor layer is positioned on one side of the barrier layer, which is far away from the substrate; wherein the hydrogen element supplying layer is used for supplying hydrogen elements to the semiconductor layer through the non-barrier region to make the position of the semiconductor layer corresponding to the non-barrier region conductive, and the vertical projection of the channel region of the semiconductor layer on the barrier region is positioned in the barrier region.

And S260, sequentially forming an interlayer insulating layer and a source drain on the side, far away from the substrate, of the semiconductor layer.

Specifically, after the interlayer insulatinglayer 60 is formed, a first via hole and a second via hole are formed, and both the first via hole and the second via hole penetrate through the interlayer insulatinglayer 60. A source S and a drain D are formed on theinterlayer insulating layer 60 at a side away from thesubstrate 10. The source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a first via hole penetrating theinterlayer insulating layer 60, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a second via hole penetrating theinterlayer insulating layer 60. Thereby connecting the source S and drain D to the conductive positions of thesemiconductor layer 40.

Alternatively, the position of thesemiconductor layer 40 corresponding to the non-barrier region may be rendered conductive by diffusing the hydrogen element in the hydrogenelement supply layer 20 from the non-barrier region of thebarrier layer 30 to thesemiconductor layer 40 by a thermal annealing process to render the position of thesemiconductor layer 40 corresponding to the non-barrier region conductive. The thermal annealing process may be performed before the first via and the second via are formed, or may be performed after the first via and the second via are formed.

Fig. 10 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention, which can be used to manufacture the thin film transistor shown in fig. 6; referring to fig. 10, the method of fabricating the thin film transistor includes:

s310, providing a substrate.

And S320, forming a semiconductor layer, wherein the semiconductor layer is positioned on one side of the substrate.

S330, forming a barrier layer, wherein the barrier layer is positioned on one side of the semiconductor layer, which is far away from the substrate; wherein the barrier layer comprises a barrier region and at least two non-barrier regions.

Specifically, thebarrier layer 30 may also include a first barrier sublayer and a second barrier sublayer, which are not described in detail herein.

S340, forming a hydrogen element supply layer on one side, far away from the substrate, of the barrier layer, wherein the hydrogen element supply layer contains hydrogen; a hydrogen element supplying layer for supplying a hydrogen element to the semiconductor layer through the non-barrier region to make the semiconductor layer conductive at a position corresponding to the non-barrier region; the hydrogen element transmittance of the blocking region is lower than that of the non-blocking region, and the vertical projection of the channel region of the semiconductor layer on the blocking layer is positioned in the blocking region.

And S350, sequentially forming a gate insulating layer, a gate, an interlayer insulating layer and a source drain on the side, far away from the substrate, of the hydrogen element supply layer.

Specifically, the formation of the interlayer insulatinglayer 60 further includes forming a first via hole and a second via hole, and the first via hole and the second via hole both penetrate through the interlayer insulatinglayer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30. A source S and a drain D are formed on theinterlayer insulating layer 60 at a side away from thesubstrate 10. The source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a first via hole penetrating theinterlayer insulating layer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-blocking region through a second via hole penetrating theinterlayer insulating layer 60, thegate insulating layer 50, the hydrogenelement supply layer 20, and thebarrier layer 30. Thereby connecting the source S and drain D to the conductive positions of thesemiconductor layer 40.

Alternatively, the position of thesemiconductor layer 40 corresponding to the non-barrier region may be rendered conductive by diffusing the hydrogen element in the hydrogenelement supply layer 20 from the non-barrier region of thebarrier layer 30 to thesemiconductor layer 40 by a thermal annealing process to render the position of thesemiconductor layer 40 corresponding to the non-barrier region conductive. The thermal annealing process needs to be performed before the first via and the second via are formed.

Fig. 11 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention, which can be used to manufacture the thin film transistor shown in fig. 7; referring to fig. 11, the method of fabricating the thin film transistor includes:

s410, providing a substrate.

And S420, sequentially forming a grid electrode and a grid electrode insulating layer on the substrate.

And S430, sequentially forming a semiconductor layer and an interlayer insulating layer on the side, away from the substrate, of the gate insulating layer.

And S440, forming a barrier layer, wherein the barrier layer is positioned on one side of the interlayer insulating layer, which is far away from the substrate.

Specifically, the barrier layer may also include a first barrier sublayer and a second barrier sublayer, which are not described herein again.

S450, forming a hydrogen element supply layer on one side, far away from the substrate, of the barrier layer, wherein the hydrogen element supply layer contains hydrogen; the barrier layer comprises a barrier region and at least two non-barrier regions, the hydrogen element transmittance of the barrier region is lower than that of the non-barrier regions, and the vertical projection of the channel region of the semiconductor layer on the barrier layer is located in the barrier region.

And S460, forming a source drain electrode on the side, far away from the substrate, of the hydrogen element supply layer.

Specifically, the formation of the interlayer insulatinglayer 60 further includes forming a first via hole and a second via hole, and the first via hole and the second via hole both penetrate through the hydrogenelement supply layer 20, thebarrier layer 30, and the interlayer insulating layer. A source S and a drain D are formed on theinterlayer insulating layer 60 at a side away from thesubstrate 10. The source electrode S is electrically connected to thesemiconductor layer 40 corresponding to the non-barrier region through a first via hole penetrating the hydrogenelement supply layer 20, thebarrier layer 30, and the interlayer insulation, and the drain electrode D is electrically connected to thesemiconductor layer 40 corresponding to the non-barrier region through a second via hole penetrating the hydrogenelement supply layer 20, thebarrier layer 30, and the interlayer insulation. Thereby connecting the source S and drain D to the conductive positions of thesemiconductor layer 40.

Alternatively, the position of thesemiconductor layer 40 corresponding to the non-barrier region may be rendered conductive by diffusing the hydrogen element in the hydrogenelement supply layer 20 from the non-barrier region of thebarrier layer 30 to thesemiconductor layer 40 by a thermal annealing process to render the position of thesemiconductor layer 40 corresponding to the non-barrier region conductive. The thermal annealing process needs to be performed before the first via and the second via are formed.

The embodiment of the invention also discloses an array substrate which comprises the thin film transistor in any embodiment.

Optionally, fig. 12 is a schematic partial structure diagram of an array substrate according to an embodiment of the present invention, and referring to fig. 12, the array substrate further includes a capacitor, a first electrode C1 of the capacitor is located at the same layer as thesemiconductor layer 40 in the thin film transistor, and a second electrode C2 of the capacitor is located at the same layer as the gate G in the thin film transistor; at the capacitive location, the blocking layer includes a non-blocking region.

Specifically, the array substrate may include a metal structure on the same layer as the thin film transistor gate (the thin film transistor gate and the structure on the same layer as the thin film transistor gate are collectively referred to as a gate metal layer), such as a capacitor plate and a scan line, and the conventional scheme of conducting an oxide semiconductor (the GI etching scheme and the ion implantation scheme) cannot conduct an oxide semiconductor covered by the gate metal layer, so that a capacitor cannot be formed using a semiconductor layer and the gate metal layer. The embodiment of the invention can break through the limitation, can conduct conductor transformation on the oxide semiconductor covered by the grid metal layer, and forms the capacitor by using the oxide semiconductor and the grid metal layer, thereby simplifying the step of forming the capacitor in the array substrate. And the first electrode C1 of the capacitor is positioned at the same layer as thesemiconductor layer 40 in the thin film transistor, and the second electrode C2 of the capacitor is positioned at the same layer as the gate G in the thin film transistor, so that the thickness of the array substrate can be reduced.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A thin film transistor, comprising:

a substrate;

a semiconductor layer on one side of the substrate;

a hydrogen element supply layer on a side of the semiconductor layer close to or remote from the substrate; the hydrogen element supply layer contains hydrogen;

a barrier layer between the hydrogen element supply layer and the semiconductor layer; wherein the barrier layer comprises a barrier region and at least two non-barrier regions, the barrier region having a hydrogen element permeability that is lower than the hydrogen element permeability of the non-barrier regions; the vertical projection of the channel region of the semiconductor layer on the barrier layer is positioned in the barrier region;

wherein the hydrogen element supply layer is configured to supply a hydrogen element to the semiconductor layer through the non-barrier region to make a position of the semiconductor layer corresponding to the non-barrier region conductive.

2. The thin film transistor of claim 1, wherein the barrier layer comprises a first barrier sublayer, the first barrier sublayer of the non-barrier region having a thickness less than a thickness of the first barrier sublayer of the barrier region;

preferably, the material of the first barrier sublayer comprises aluminum oxide.

3. The thin film transistor of claim 2, wherein the first barrier sublayer of the non-blocking region has a thickness of zero.

4. The thin film transistor according to claim 2 or 3, wherein the barrier layer further comprises a second barrier sublayer, the second barrier sublayer being located between the first barrier sublayer and the semiconductor layer, a thickness of the second barrier sublayer being positively correlated with a hydrogen content in the hydrogen element supplying layer; the hydrogen element transmittance of the first barrier sublayer is lower than that of the second barrier sublayer;

preferably, the material of the second barrier sublayer comprises silicon oxide.

5. The thin film transistor according to claim 1, further comprising a gate electrode, a source electrode, and a drain electrode; the hydrogen element supply layer is positioned on one side of the semiconductor layer close to the substrate;

the grid electrode is positioned on one side of the semiconductor layer far away from the substrate; a gate insulating layer is further arranged between the gate and the semiconductor layer; the side, far away from the substrate, of the grid further comprises an interlayer insulating layer, and the source electrode and the drain electrode are located on the side, far away from the substrate, of the interlayer insulating layer; the source electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a first via hole penetrating the interlayer insulating layer and the gate insulating layer, and the drain electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a second via hole penetrating the interlayer insulating layer and the gate insulating layer;

or the grid is positioned on one side of the hydrogen element supply layer close to the substrate; the gate insulating layer is further arranged between the gate and the hydrogen element supply layer, the interlayer insulating layer is further arranged on one side, away from the substrate, of the semiconductor layer, and the source electrode and the drain electrode are located on one side, away from the substrate, of the interlayer insulating layer; the source electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a first via hole penetrating the interlayer insulating layer, and the drain electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a second via hole penetrating the interlayer insulating layer.

6. The thin film transistor according to claim 1, further comprising a gate electrode, a source electrode, and a drain electrode; the hydrogen element supply layer is positioned on one side of the semiconductor layer far away from the substrate;

the grid electrode is positioned on one side of the hydrogen element supply layer far away from the substrate; a gate insulating layer is further provided between the gate electrode and the hydrogen element supply layer; the side, far away from the substrate, of the grid further comprises an interlayer insulating layer, and the source electrode and the drain electrode are located on the side, far away from the substrate, of the interlayer insulating layer; the source electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a first via hole penetrating the interlayer insulating layer, the gate insulating layer, the hydrogen element supply layer, and the blocking layer, and the drain electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a second via hole penetrating the interlayer insulating layer, the gate insulating layer, the hydrogen element supply layer, and the blocking layer;

or the grid is positioned on one side of the semiconductor layer close to the substrate; the interlayer insulating layer is arranged between the grid electrode and the semiconductor layer; an interlayer insulating layer is further arranged between the semiconductor layer and the barrier layer, and the source electrode and the drain electrode are positioned on one side, away from the substrate, of the hydrogen element supply layer; the source electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a first via hole penetrating the hydrogen element supply layer, the barrier layer, and the interlayer insulating layer, and the drain electrode is electrically connected to the semiconductor layer corresponding to the non-blocking region through a second via hole penetrating the hydrogen element supply layer, the barrier layer, and the interlayer insulating layer;

preferably, the vertical projection of the first via hole on the blocking layer is located in the non-blocking area, the edge distance between the vertical projection of the first via hole on the blocking layer and the edge distance between the vertical projection of the first via hole on the non-blocking area is greater than 0, the vertical projection of the second via hole on the blocking layer is located in the non-blocking area, and the edge distance between the vertical projection of the second via hole on the blocking layer and the edge distance between the vertical projection of the second via hole on the non-blocking area is greater than 0.

7. A method for manufacturing a thin film transistor includes:

providing a substrate;

forming a semiconductor layer, wherein the semiconductor layer is positioned on one side of the substrate;

forming a hydrogen element supply layer on a side of the semiconductor layer close to or remote from the substrate; the hydrogen element supply layer contains hydrogen;

forming a barrier layer between the hydrogen element supplying layer and the semiconductor layer; wherein the barrier layer comprises a barrier region and at least two non-barrier regions, the barrier region having a hydrogen element permeability that is lower than the hydrogen element permeability of the non-barrier regions; the vertical projection of the channel region of the semiconductor layer on the barrier layer is positioned in the barrier region;

wherein the hydrogen element supply layer is configured to supply a hydrogen element to the semiconductor layer through the non-barrier region to make a position of the semiconductor layer corresponding to the non-barrier region conductive.

8. The method for manufacturing a thin film transistor according to claim 7, wherein the conductor-forming of the semiconductor layer at a position corresponding to the non-blocking region comprises:

the hydrogen element in the hydrogen element supplying layer is diffused from the non-barrier region of the barrier layer to the semiconductor layer by the thermal annealing process to make the position of the semiconductor layer corresponding to the non-barrier region conductive.

9. An array substrate comprising the thin film transistor according to any one of claims 1 to 6.

10. The array substrate of claim 9, further comprising a capacitor, wherein a first electrode of the capacitor is located at the same layer as the semiconductor layer of the thin film transistor, and a second electrode of the capacitor is located at the same layer as the gate of the thin film transistor;

at the capacitive location, the blocking layer includes a non-blocking region.

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