CN112992208A - Non-volatile memory - Google Patents

Abstract

The invention provides a non-volatile memory, comprising: the system comprises a plurality of memory modules, a WL control circuit, a BL control circuit and a SL control circuit; the memory module comprises a memory cell array formed by a plurality of same memory cells; the input port of the WL control circuit is connected with a WL address signal; WL ports of the memory cells in the same row form an array structure; WL ports in the same row are all connected with the same output port of the WL control circuit; the input port of the BL control circuit is connected with a BL address signal, and the BL ports of the same column of storage units are connected with the same output port of the BL control circuit; the input port of the SL control circuit is connected with SL address signals, and SL ports of storage units of the same storage module are connected with the same output port of the SL control circuit. The non-volatile memory of the invention prevents data reading errors by separately controlling the SL ports of the memory modules without increasing the area of the memory array.

Description

Non-volatile memory

Technical Field

The invention relates to the technical field of electronics, in particular to a non-volatile memory.

Background

The memory is a basic component of a modern computing system and can be generally divided into a volatile type and a non-volatile type, wherein the non-volatile type memory can still maintain data after the system is powered off. The non-volatile memory in the prior art mainly includes memories using charge and discharge mechanisms, such as an EEPROM (Electrically Erasable Programmable read only memory), a NOR Flash (NOR Flash memory), and a NAND Flash, and also memories using special materials and non-charge and discharge mechanisms, such as a resistive random access memory (RRAM or ReRAM), a magnetoresistive memory (MRAM), a Phase Change Memory (PCM), a ferroelectric memory (FeRAM), and a carbon nanotube memory (NRAM).

The memory cells in a memory typically have an array structure, forming an array of memory cells. Since EEPROM memory supports byte (usually 8 bits are 1 byte) erasure, there is a Byte Select Transistor (BST) for every 8 bits. Because the area occupied by the BST in the memory cell array is larger, the memory cell array architecture in the prior art removes the BST, and the byte-based erasing function of the EEPROM is realized by a method of separately controlling the SL (source line) according to bytes, so that the purpose of reducing the area of the EEPROM memory array is achieved. However, this array structure introduces an erase disturb problem on the same row (same control gate line CGL), and the erase operation requires proper selection of CGL voltage and SL voltage (Vsinh) of unselected bytes.

The conventional non-volatile memory has the problem of data reading errors under specific conditions such as specific data background, high temperature or radiation and the like. The main reason for this problem is that when reading a certain memory cell in the non-volatile memory array, the memory cells on the unselected WL on the same BL are connected in parallel with the selected WL cell, and if the off-state drain leakage current of the unselected cell is too large, the data misreading of the target cell may be caused. Taking EEPROM memory as an example, when the floating gate device stored in the unselected cell is low threshold (i.e. data "0"), the leakage current of the memory cell is mainly determined by the select transistor. When the capacity of the memory is large and the number of memory units connected in parallel on the same BL is large, the total off-state drain leakage current of the select transistor is large, especially under the condition of high temperature or radiation, the off-state drain leakage current of the select transistor is also large, and if the off-state drain leakage current exceeds the reading judgment current of the reading circuit, data can be read incorrectly. This problem is manifested in terms of characteristics related to the capacity of the memory, to the background of the stored data, to conditions such as temperature or radiation. Memories such as NOR Flash, NAND Flash, RRAM, MRAM, and PCM also have a similar problem in that read data is affected by background data. In addition, NOR Flash also has the problem of over-erasing, and it is to be ensured that the memory cell cannot be over-erased, that is, the threshold of the memory cell cannot be less than 0V, and an over-erased cell or an excessive number of critical over-erased cells, especially at high temperature, may cause a cell misreading on the same BL, which requires strict control of the threshold distribution of the erased state of the memory cell, and may make the erase algorithm more complicated.

Disclosure of Invention

The invention aims to provide a non-volatile memory, which can overcome the defects in the prior art and prevent errors in reading data from a selected memory cell of the non-volatile memory under the conditions of specific data background, high temperature, radiation and the like.

In order to achieve the above object, the present invention provides a nonvolatile memory, comprising: the system comprises a plurality of memory modules, a WL control circuit, a BL control circuit and a SL control circuit;

the memory module comprises a memory cell array formed by a plurality of same memory cells; the memory cell comprises at least one WL port, one BL port and one SL port;

the input port of the WL control circuit is connected with a WL address signal; WL ports of the memory cells in the same row form an array structure; the WL ports in the same row are connected with the same output port of the WL control circuit, and the WL ports in different rows are connected with different output ports of the WL control circuit;

the input port of the BL control circuit is connected with BL address signals, the BL ports of the same column of storage units are connected with the same output port of the BL control circuit, and the BL ports of different columns of storage units are connected with different output ports of the BL control circuit;

the input port of the SL control circuit is connected with SL address signals, the SL ports of the storage units of the same storage module are connected with the same output port of the SL control circuit, and the SL ports of the storage units of different storage modules are connected with different output ports of the SL control circuit.

Preferably, the nonvolatile memory comprises N m memory cells, and the N m memory cells have an array structure of N rows and m columns;

the plurality of storage modules are respectively 1 st to nth storage modules, and n is more than 1; wherein the ith storage module is b_iAn array structure of rows and m columns comprising b_iX m memory cells, i ∈ [1, n ]]，

Preferably, the memory cell is any one of a 2T memory cell, a 1.5T memory cell, a 1T memory cell, an MT memory cell, and a 1T1R memory cell.

Preferably, the 2T memory cell includes: a selection tube, a storage tube, a WL port, a CG port, a BL port and a SL port; the WL port of the 2T memory cell is connected with the grid electrode of the 2T memory cell selection tube; the CG port of the 2T memory cell is connected with the grid electrode of the storage tube of the 2T memory cell; the BL port of the 2T memory cell is connected with the drain electrode of the 2T memory cell selection tube; the source electrode of the 2T storage unit selection tube is connected with the drain electrode of the 2T storage unit storage tube; the source of the 2T memory cell storage tube is connected with the SL port of the 2T memory cell.

Preferably, the 2T memory cell includes: a selection tube, a storage tube, a WL port, a BL port and a SL port; the WL port of the 2T memory cell is connected with the grid electrode of the 2T memory cell selection tube; the BL port of the 2T storage unit is connected with the drain electrode of the storage tube of the 2T storage unit; the source electrode of the 2T storage unit storage tube is connected with the drain electrode of the 2T storage unit selection tube; the source of the 2T memory cell selection tube is connected with the SL port of the 2T memory cell.

Preferably, the 1.5T memory cell includes: the system comprises a double-gate storage tube, a WL port, a CG port, a BL port and an SL port; the single-layer grid electrode of the double-grid storage tube is connected with the WL port of the 1.5T storage unit; the upper grid electrode of the double-layer grid electrode of the double-grid storage tube is connected with the CG port of the 1.5T storage unit; the lower grid electrode of the double-layer grid electrode of the double-grid storage tube is floating; the drain electrode of the double-gate storage tube is connected with the BL port of the 1.5T storage unit; and the source electrode of the double-gate storage tube is connected with the SL port of the 1.5T storage unit.

Preferably, the 1T memory cell includes: a storage tube, a WL port, a BL port and a SL port; the grid electrode of the storage tube of the 1T storage unit is connected with the WL port of the 1T storage unit; the drain electrode of the 1T memory cell is connected with the BL port of the 1T memory cell; the source of the 1T memory cell is connected to the SL port of the 1T memory cell.

Preferably, the MT memory unit includes: first to kWL th ports, a BL port and a SL port arranged in this order; WL ports of m MT memory units in the same row form a k multiplied by m array structure; the MT memory unit further includes: the first selection tube, the first to the k-th storage tubes and the second selection tube are connected in sequence; the drain electrode of the first selection tube of the MT memory cell is connected with the BL port of the MT memory cell; the source electrode of the first selection tube of the MT storage unit is connected with the drain electrode of the first storage tube of the MT storage unit; the source electrode of the jth storage tube of the MT storage unit is connected with the drain electrode of a jth +1 storage tube, wherein j belongs to [1, k-1 ]; the gate of the ith storage tube of the MT storage unit is connected with the iWL th port, wherein i belongs to [1, k ]; the source electrode of the kth storage tube of the MT storage unit is connected with the drain electrode of the second selection tube of the MT storage unit; the source of the second selection tube of the MT memory cell is connected with the SL port of the MT memory cell.

Preferably, the 1T1R memory cell comprises a select transistor and a two-port memory device, a WL port, a BL port, and a SL port; the gate of the 1T1R memory cell selection transistor is connected to the WL port of the 1T1R memory cell; the drain of the 1T1R memory cell selection transistor is connected to the BL port of the 1T1R memory cell; the source of the 1T1R memory cell select transistor is connected to one end of a two-port memory device, and the other end of the two-port memory device is connected to the SL port of the 1T1R memory cell.

Preferably, the 1T1R memory cell comprises a select transistor and a two-port memory device, a WL port, a BL port, and a SL port; the gate of the 1T1R memory cell selection transistor is connected to the WL port of the 1T1R memory cell; the source of the 1T1R cell select transistor is connected to the SL port of the 1T1R cell; the drain of the selection tube is connected with one end of the two-port memory device, and the other end of the two-port memory device is connected with the BL port of the 1T1R memory cell.

Preferably, the two-port memory device is any one of a resistive memory device, a magnetoresistive memory device, a phase change memory device, a ferroelectric memory device, and a carbon nanotube memory device.

Preferably, b_i×I_{Leakage current}＜I_{Judging the current}(ii) a Wherein b is_iThe number of rows of the storage units contained in the ith storage module; i is an e [1, n ]]；I_{Leakage current}Leakage current in the off state of the memory cell, I_{Judging the current}The judgment current is used for reading the data of the memory cell.

Compared with the prior art, the invention has the beneficial effects that:

the nonvolatile memory of the invention adopts a new memory array framework, and greatly reduces the leakage current index requirement of the memory device under the condition of high temperature or radiation by increasing the number of the SL ports of the memory array and the SL control circuit under the condition of not increasing the area of the memory array. The invention can be applied to high-capacity automobile electronic equipment and anti-radiation memory products, and solves the problem of reading errors of the high-capacity automobile electronic equipment and the anti-radiation memory in the prior art.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are an embodiment of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts according to the drawings:

FIG. 1 is a schematic diagram of a prior art non-volatile memory cell;

FIGS. 2A-2E are schematic circuit diagrams of a 2T memory cell, a 1.5T memory cell, a 1T memory cell, an MT memory cell, and a 1T1R memory cell, respectively, according to the prior art;

FIG. 3 is a diagram of a prior art floating gate EEPROM memory cell;

FIG. 4 is a graph of the current-voltage characteristic of a prior art EEPROM memory cell in the high-threshold, low-threshold state;

FIG. 5A is a diagram of a prior art EEPROM memory array structure;

FIG. 5B is a schematic diagram illustrating leakage current generated by the EEPROM memory shown in FIG. 5A;

FIG. 6A is a schematic diagram of an EEPROM memory array in accordance with a first embodiment of the invention;

FIG. 6B is a schematic diagram illustrating leakage current generated by the EEPROM memory shown in FIG. 6A;

FIG. 7 is a diagram of a NOR Flash type memory array according to a third embodiment of the present invention;

FIG. 8 is a schematic diagram of a NAND Flash type memory array in accordance with a fourth embodiment of the present invention;

FIG. 9 is a schematic diagram of a RRAM memory array in accordance with a fifth embodiment of the invention;

FIG. 10 is a circuit diagram of a nonvolatile memory according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, the nonvolatile memory includes a plurality of memory cells, each of which includes at least one WL (word line) port, one BL (bit line) port, and one SL (source line) port.

The memory cells typically contain memory devices and select devices. The memory device is used for storing data and may be a floating gate transistor, a charge trapping device (e.g., SONOS). The selection device is used for gating read-write signals and can be a MOS transistor, a diode, a specific threshold device or a nonlinear device and the like. Some memory cells integrate a memory device and a selection device into one device, for example, a floating gate type NOR Flash memory cell can be used as both a memory device and a selection device.

Fig. 2A to 2D are schematic circuit diagrams illustrating a MOS transistor as a non-volatile memory cell in the prior art.

Of these, fig. 2A is a 2T memory cell, typically represented as an EEPROM type memory cell.

FIG. 2B is a 1.5T memory cell, typically represented as an embedded non-volatile memory cell, such asESF 3. The 1.5T memory cell is composed of a double-gate double-channel transistor, wherein the drain end of the transistor is connected with the BL port of the transistor, the source end of the transistor is connected with the SL port of the transistor, a single-layer grid used as a selection tube is connected with the WL port of the transistor, and a control grid used as a double-layer grid for storing data is connected with the CG port of the transistor. The upper and lower positions of the single-layer grid and the double-layer grid can be exchanged. Some 1.5T memory cells also have an Erase Gate (EG) for erasing the charge in the floating gate.

Fig. 2C is a 1T memory cell, typically represented as a NOR Flash type memory cell.

Fig. 2D is an MT memory cell, typically represented as a NAND Flash type memory cell. The MT storage unit is composed of two selection pipes and a plurality of storage pipes, and the storage pipes are connected in series between the two selection pipes. The selection transistor of the MT memory cell may be a MOS transistor, and the storage transistor thereof may be a floating gate transistor or a charge trapping device.

FIG. 2E is a 1T memory cell, consisting of a select transistor and a two-port memory device. Typical examples of such a structure include nonvolatile memory cells using a non-charge/discharge mechanism, such as a Resistive Random Access Memory (RRAM), a magnetoresistive memory (MRAM), a Phase Change Memory (PCM), a ferroelectric memory (FeRAM), and a carbon nanotube memory. The memory devices of the memory cells can be represented by resistance variable devices, and the resistance change mechanisms of different types of memory devices are different.

The following takes a floating gate type EEPROM as an example to describe a prior art memory array architecture. As shown in fig. 3, in a floating gate EEPROM cell, a Floating Gate (FG) is in a floating state, and electrons are injected into or erased from the floating gate during a program or erase operation, and a change in the amount of stored charge in the floating gate changes the threshold voltage of a floating gate device. As shown in fig. 4, when a specific voltage (usually called a read voltage, denoted by Vrd) is applied to the Control Gate (CG), the read circuit compares the read current (BL current) of the memory cell with the judgment current, and when the memory cell is at a high threshold, the read current is smaller than the judgment current, and the data is "1"; when the memory cell is at a low threshold, the read current is greater than the judgment current, and the data is "0". The definitions of the different memory product data "1" and "0" may differ.

In the prior art, the non-volatile memory is an array structure formed by a plurality of memory cells, the array structure layout is generally as shown in fig. 5A, in each row of memory cells, sequentially, every 8 memory cells form a byte (some memories with check bit or ECC bit, each byte may be more than 8 bits), and the drain terminal of the memory cell select transistor in the same column is connected to a same Bit Line (BL). The source terminals of all the memory cells are connected to one and the same Source Line (SL). In the dotted circle of fig. 5B, a target read memory cell is shown, a WL select middle voltage Vsel (typically, a power supply voltage) connected to the target read memory cell is generally connected to 0.8V for BL connected to the target read memory cell, a CG read voltage Vrd (typically, 0 to 1V) connected to the target read memory cell is connected to 0V for SL. The WL of the memory cells in other unselected rows are tied to 0V, and the BL of the memory cells in other unselected columns are floating.

The nonvolatile memory shown in fig. 5A has a data read error problem under certain conditions. As shown in fig. 5B, when the memory cell current is read, the read current turns on a certain BL, and the read current is actually the sum of the currents of all the memory cells on the certain BL, including the currents of the selected memory cells and the unselected memory cells in the same column. Because all memory cells connected to the same BL are in parallel, the total BL current is the sum of the currents of each memory cell. BL of different columns is not connected to BL corresponding to target reading memory cell, and the reading current is not influenced.

When the floating gate transistor of the unselected memory cell is in a low threshold (usually, this state is defined as data "0"), the floating gate transistor is in a conducting state, and the leakage current of the memory cell is mainly determined by the select transistor. Under a higher temperature condition, such as 85 ℃ or above 125 ℃, the threshold voltage of the MOS transistor is a negative temperature coefficient, the threshold voltage of the MOS transistor is lower, and the leakage current in the off state of the MOS transistor is larger. When the memory capacity is large, the number of unselected cells on the same BL is large, and the high threshold of the target read cell is erroneously determined as the low threshold, that is, no current is determined as current (data "1" changes to "0").

For example, in the prior art, one memory array is 1024 rows, the leakage current of each unselected memory cell in the high temperature or radiation condition for storing data "0" is 10nA, and with the prior art array architecture, the leakage current of the unselected other 1023 memory cells in the same column reaches 10.23uA, which usually exceeds the read judgment current, and leads to data misreading. It is characterized in that data read failure is related to memory capacity, data background and temperature, and data "1" is most easily misread as "0" when the capacity is larger, the temperature is higher, the number of "0" in background data is larger. This problem is most severe in products that are in demand for high temperature applications, such as in the automotive electronics field. There are also applications where radiation, such as X-rays or gamma rays, can cause increased leakage in the memory select transistor, presenting similar problems as well as capacity and data context related characteristics.

To solve the problem, the conventional solution is to optimize the process or device parameters of the memory cell, reduce the leakage current of the select transistor at high temperature, or perform radiation-resistant reinforcement on the memory cell to reduce the radiation-induced leakage current, which may result in a significant increase in the process development difficulty, a long process development period, or a significant increase in the memory cell area.

The invention provides a non-volatile memory, comprising: the system comprises a plurality of memory modules, a WL control circuit, a BL control circuit and a SL control circuit;

the memory module comprises a memory cell array formed by a plurality of same memory cells; the memory cell comprises at least one WL port, one BL port and one SL port;

the input port of the WL control circuit is connected with a WL address signal; WL ports of the memory cells in the same row form an array structure; the WL ports in the same row are connected with the same output port of the WL control circuit, and the WL ports in different rows are connected with different output ports of the WL control circuit;

the input port of the BL control circuit is connected with BL address signals, the BL ports of the same column of storage units are connected with the same output port of the BL control circuit, and the BL ports of different columns of storage units are connected with different output ports of the BL control circuit;

the input port of the SL control circuit is connected with SL address signals, the SL ports of the storage units of the same storage module are connected with the same output port of the SL control circuit, and the SL ports of the storage units of different storage modules are connected with different output ports of the SL control circuit. The output port of the SL control circuit corresponding to the unselected memory module is floated, so that a leakage current path of the memory unit in the unselected module is cut off, and the unselected memory module is prevented from influencing the reading of the data of the memory unit in the selected memory module.

Preferably, the nonvolatile memory comprises N m memory cells, and the N m memory cells have an array structure of N rows and m columns;

the plurality of storage modules are respectively 1 st to nth storage modules, and n is more than 1; wherein the ith storage module is b_iAn array structure of rows and m columns comprising b_iX m memory cells, i ∈ [1, n ]]，

The number of rows of memory cells contained in each memory module may be different.

As shown in fig. 10, in sequence, first row to b-th row₁The memory cells of a row form a first memory module comprising b₁Xm memory cells; b th₁+1 line to b₁+b₂The memory cells of a row form a second memory module comprising b₂Xm memory cells, and so on.

As shown in fig. 10, BL <1> to BL < m > are m input ports of the BL control circuit, respectively. The output port of each BL control circuit is connected with the BL ports of the memory units in the same column.

When the memory cell includes one WL port, as shown in FIG. 10, the WL control circuit includes WL <1> to WL < n > < b_nTotal N output ports. WL < p > < q > is connected to the WL port of the q-th row of memory cells of the p-th memory module.

In fig. 10, SL <1> to SL < n > are n output ports of the SL control circuit, respectively, and the SL ports of the memory cells of each memory module are all connected to the output port of the same SL control circuit.

In the invention, a method for separately controlling the output ports of the SL control circuit is adopted, and the number of rows of the memory cells sharing one SL output port and the leakage current of the memory cells are compromised, so that the data of the nonvolatile memory can be prevented from being read by mistake. In a specific method, b_i×I_{Leakage current}＜I_{Judging the current}(ii) a Wherein b is_iThe number of rows of the storage units contained in the ith storage module; i is an e [1, n ]]；I_{Leakage current}Leakage current in the off state of the memory cell, I_{Judging the current}The judgment current is used for reading the data of the memory cell. I.e. by selecting in each memory moduleThe number of rows of the memory cells is included to prevent the data of the nonvolatile memory from being read by mistake.

Preferably, the memory cell is any one of an EEPROM type memory cell, a NOR Flash type memory cell, a NAND Flash type memory, a RRAM type memory cell, an MRAM type memory cell, and a PCM type memory cell.

In a first embodiment of the present invention, as shown in fig. 6A, the memory cells in the non-volatile memory are EEPROM type memory cells, and each memory module contains a row of memory cells. As shown in fig. 6A and 2A, the EEPROM memory cell includes: one select tube, one storage tube, one WL port, one CG port, one BL port and one SL port. The WL port of the EEPROM type memory cell is connected with the grid electrode of the EEPROM type memory cell selection tube; the CG port of the EEPROM type memory cell is connected with the grid electrode of the memory tube of the EEPROM type memory cell; the BL port of the EEPROM type memory cell is connected with the drain electrode of the EEPROM type memory cell selection tube; the source electrode of the EEPROM type memory cell selection tube is connected with the drain electrode of the EEPROM type memory cell storage tube; the source electrode of the EEPROM type memory cell storage tube is connected with the SL port of the EEPROM type memory cell. WL <0> to WL <3> in FIG. 6A represent different output ports of the WL control circuit, and are connected to different rows of EEPROM type memory cells, respectively; BL <0> to BL <15> represent different output ports of the BL control circuit and are respectively connected with EEPROM type memory cells in different columns; SL <0> to SL <3> represent different output ports of the SL control circuit, and EEPROM memory cells in different rows are connected to the output ports. As shown in FIG. 6B, when the selected memory cell is the memory cell in the first row and the first column indicated by the dashed circle, the SL <0> is turned on and SL <1> to SL <3> are floated by separately controlling the output port of the SL control circuit, so that other unselected memory cells in the first column do not have any influence on the selected memory cell.

In the first embodiment, sequentially, each 8 memory cells in the same row constitute a byte memory cell (here, 8 are taken as an example) for storing one byte of data. The nonvolatile memory further includes N' ═ N × m/8 byte selector tubes BST. One byte selection pipe BST corresponds to one byte storage unit, and different byte selection pipes BST correspond to different byte storage units. The grid electrode of each memory cell memory tube in one byte memory cell is connected with the source electrode of the corresponding byte selection tube BST. The byte select transistor BST gate is connected to an output port of the WL control circuit, and the output port of the WL control circuit corresponds to the byte memory cell to which the byte select transistor BST is connected.

In the first embodiment, as shown in FIG. 6A, the non-volatile memory specifically comprises m/8 control gates CG. In fig. 6A, CG <0> and CG <1> represent different control deletions. In sequence, each eight columns of memory cells of the non-volatile memory are a memory group, each memory group corresponds to one array control gate CG, and different memory groups correspond to different control gates CG. The array control gate CG is connected with the drain electrode of the byte selection tube BST in the corresponding storage group.

In a second embodiment of the present invention (not shown), the EEPROM type memory cell includes: one select tube, one storage tube, one WL port, one CG port, one BL port and one SL port. The WL port of the EEPROM type memory cell is connected with the grid electrode of the EEPROM type memory cell selection tube; the BL port of the EEPROM type memory cell is connected with the drain electrode of the storage tube of the EEPROM type memory cell; the source electrode of the EEPROM type memory cell storage tube is connected with the drain electrode of the EEPROM type memory cell selection tube; the source electrode of the EEPROM type memory cell selection tube is connected with the SL port of the EEPROM type memory cell.

In a third embodiment of the present invention, as shown in fig. 7, the memory cells in the non-volatile memory are NOR Flash type memory cells, and each memory module contains 64 lines of NOR Flash type memory cells. The NOR Flash type memory cell includes: one storage tube, one WL port, one BL port and one SL port. The grid electrode of the storage tube of the NOR Flash type storage unit is connected with the WL port of the NOR Flash type storage unit; the drain electrode of the storage tube of the NOR Flash type storage unit is connected with the BL port of the NOR Flash type storage unit; the source electrode of the storage tube of the NOR Flash type storage unit is connected with the SL port of the NOR Flash type storage unit.

In a third embodiment, 64 lines of NOR Flash type memory cells are connected to each SL control circuit output port. SelectingWhen any NOR Flash type memory cell is selected to be read, only the other 63 NOR Flash type memory cells in the same column with the same memory module and the NOR Flash type memory cell will affect the read memory cell. But because 64 xI is satisfied_{Leakage current}＜I_{Judging the current}Therefore, the 63 NOR Flash type memory cells do not affect the data of the NOR Flash type memory cells read. In practical application, can be in I_{Leakage current}A trade-off is made with the number of rows of memory cells contained in each memory module.

In a fourth embodiment of the present invention, as shown in fig. 8, the memory units in the non-volatile memory are NAND Flash type memory units, and each memory module contains one row of NAND Flash type memory units. Two memory modules are shown in fig. 8. As shown in fig. 8, the NAND Flash type memory cell includes: first to 32 nd WL ports, a BL port, and a SL port, which are sequentially provided; WL ports of m NAND Flash type memory units in the same row form a 32 x m array structure. The NAND Flash type memory cell further includes: the first selection pipe, the first to the 32 th storage pipes and the second selection pipe are connected in sequence; as shown in fig. 8 and 2D, the drain of the first selection transistor of the NAND Flash type memory unit is connected to the BL port of the NAND Flash type memory unit; the source electrode of the first selection tube of the NAND Flash type storage unit is connected with the drain electrode of the first storage tube of the NAND Flash type storage unit; the source electrode of the jth storage tube of the NAND Flash type storage unit is connected with the drain electrode of the jth +1 storage tube, wherein j belongs to [1,31 ]; the grid electrode of the ith storage tube of the NAND Flash type storage unit is connected with the iWL th port of the NAND Flash type storage unit, wherein i belongs to [1,32 ]; the source electrode of the 32 th storage tube of the NAND Flash type storage unit is connected with the drain electrode of the second selection tube of the NAND Flash type storage unit; and the source electrode of the second selection tube of the NAND Flash type storage unit is connected with the SL port of the NAND Flash type storage unit.

In a fourth embodiment, N SGD ports and N SGS ports are also included. The grid electrodes of the first selection tubes of the NAND Flash type storage units in each row are connected with the same SGD port, and the grid electrodes of the first selection tubes of the NAND Flash type storage units in different rows are connected with different SGD ports; the grid electrode of the second selection tube of each row of the NAND Flash type storage units is connected with the SGS port, and the grid electrodes of the second selection tubes of different rows of the NAND Flash type storage units are connected with different SGS ports.

In the fourth embodiment, NAND Flash type memory cells in the same row are connected to 32 different output ports of the WL control circuit. In this embodiment, since the same memory module has only one row of NAND Flash type memory cells, the read-out current is not affected by any other cells.

In a fifth embodiment of the present invention, as shown in fig. 9, the memory cells in the nonvolatile memory are RRAM memory cells, and each memory module includes 16 rows of RRAM type memory cells. The RRAM type memory unit comprises a selection tube, a two-port non-volatile memory device, a WL port, a BL port and a SL port which are connected with each other; the grid electrode of the RRAM type memory cell selection tube is connected with the WL port of the RRAM type memory cell; the drain electrode of the RRAM type memory cell selection tube is connected with the BL port of the RRAM type memory cell; the source electrode of the RRAM type memory cell selection tube is connected with one end of the two-port non-volatile memory device, and the other end of the two-port non-volatile memory device is connected with the SL port of the RRAM type memory cell.

In a fifth embodiment of the present invention, the memory cells in the non-volatile memory are RRAM memory cells, and each memory module contains 16 rows of RRAM type memory cells. The RRAM type memory unit comprises a selection tube, a two-port non-volatile memory device, a WL port, a BL port and a SL port which are connected with each other; the grid electrode of the RRAM type memory cell selection tube is connected with the WL port of the RRAM type memory cell; one end of the two-port non-volatile memory device is connected with the BL port of the RRAM type memory unit; the other end of the two-port non-volatile memory device is connected with the source electrode of the RRAM type memory cell selection tube; the source of RRAM type memory cell selection tube is connected with SL port of RRAM type memory cell.

In a sixth embodiment of the present invention, the memory cells in the nonvolatile memory are MRAM type memory cells, each memory module includes 16 rows of MRAM type memory cells, and the schematic structural diagram of the nonvolatile memory array in the sixth embodiment is the same as that in fig. 9. The MRAM type memory unit comprises a selection tube, a two-port non-volatile memory device, a WL port, a BL port and a SL port which are connected with each other; the grid electrode of the MRAM type memory cell selection tube is connected with the WL port of the RRAM type memory cell; the drain electrode of the MRAM type memory cell selection tube is connected with the BL port of the MRAM type memory cell; the source of the MRAM memory cell selection tube is connected to one end of the two-port non-volatile memory device, and the other end of the two-port non-volatile memory device is connected to the SL port of the MRAM memory cell.

In a seventh embodiment of the present invention, the memory cells in the non-volatile memory are PCM type memory cells, each memory module comprises 16 rows of PCM type memory cells, and the schematic structure of the non-volatile memory array in the seventh embodiment is the same as that in fig. 9. The PCM type memory unit comprises a selection tube, a two-port non-volatile memory device, a WL port, a BL port and a SL port which are connected with each other; the grid of the PCM type memory cell selection tube is connected with the WL port of the PCM type memory cell; the drain electrode of the PCM type memory cell selection tube is connected with the BL port of the PCM type memory cell; the source of the PCM type memory cell selection tube is connected with one end of a two-port non-volatile memory device, and the other end of the two-port non-volatile memory device is connected with the SL port of the PCM type memory cell.

In an eighth embodiment of the present invention, the memory cells in the non-volatile memory are ferroelectric memory cells, each memory module includes 16 rows of ferroelectric memory cells, and the schematic structure of the non-volatile memory array in the eighth embodiment is the same as that in fig. 9. The ferroelectric memory unit comprises a selection tube, a two-port non-volatile ferroelectric memory device, a WL port, a BL port and a SL port which are connected with each other; the grid electrode of the ferroelectric memory cell selection tube is connected with the WL port of the ferroelectric memory cell; the drain electrode of the ferroelectric memory cell selection tube is connected with the BL port of the ferroelectric memory cell; the source electrode of the ferroelectric memory cell selection tube is connected with one end of the two-port non-volatile memory device, and the other end of the two-port non-volatile memory device is connected with the SL port of the ferroelectric memory cell.

In a ninth embodiment of the present invention, the memory cells in the non-volatile memory are carbon nanotube-type memory cells, each memory module includes 16 rows of carbon nanotube-type memory cells, and the schematic structure of the non-volatile memory array in the ninth embodiment is the same as that in fig. 9. The carbon nanotube type memory unit comprises a selection tube, a two-port non-volatile memory device, a WL port, a BL port and an SL port which are connected with each other; the grid electrode of the carbon nanotube type memory cell selection tube is connected with the WL port of the carbon nanotube type memory cell; the drain electrode of the carbon nanotube type memory cell selection tube is connected with the BL port of the carbon nanotube type memory cell; the source electrode of the carbon nanotube type memory cell selection tube is connected with one end of the two-port non-volatile memory device, and the other end of the two-port non-volatile memory device is connected with the SL port of the carbon nanotube type memory cell.

In the fifth, sixth, seventh, eighth, ninth embodiments, 16 rows of memory cells are connected per SL control circuit output port. When any memory cell is selected to be read, only the other 15 memory cells in the same column with the memory module and the memory cell will affect the read memory cell. Only need to satisfy 16 × I_{Leakage current}＜I_{Judging the current}The memory cell data can be prevented from being read incorrectly.

The invention has the beneficial effects that:

the nonvolatile memory of the invention adopts a new memory array framework, and greatly reduces the leakage current index requirement of the memory device under the condition of high temperature or radiation only by increasing the number of SL output ports of the memory array and a smaller SL control circuit under the condition of not increasing the area of the memory array. The invention can be applied to high-capacity automobile electronic equipment and anti-radiation memory products, and solves the problem of reading errors of the high-capacity automobile electronic equipment and the anti-radiation memory in the prior art.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (12)

1. A non-volatile memory, comprising: the system comprises a plurality of memory modules, a WL control circuit, a BL control circuit and a SL control circuit;

the memory module comprises a memory cell array formed by a plurality of same memory cells; the memory cell comprises at least one WL port, one BL port and one SL port;

the input port of the WL control circuit is connected with a WL address signal; WL ports of the memory cells in the same row form an array structure; the WL ports in the same row are connected with the same output port of the WL control circuit, and the WL ports in different rows are connected with different output ports of the WL control circuit;

the input port of the BL control circuit is connected with BL address signals, the BL ports of the same column of storage units are connected with the same output port of the BL control circuit, and the BL ports of different columns of storage units are connected with different output ports of the BL control circuit;

the input port of the SL control circuit is connected with SL address signals, the SL ports of the storage units of the same storage module are connected with the same output port of the SL control circuit, and the SL ports of the storage units of different storage modules are connected with different output ports of the SL control circuit.

2. The non-volatile memory according to claim 1, wherein the non-volatile memory comprises N x m memory cells having an array structure of N rows and m columns;

the plurality of storage modules are respectively 1 st to nth storage modules, and n is more than 1; wherein the ith storage module is b_iAn array structure of rows and m columns comprising b_iX m memory cells, i ∈ [1, n ]]，

3. The non-volatile memory according to claim 2, wherein the memory cell is any one of a 2T memory cell, a 1.5T memory cell, a 1T memory cell, an MT memory cell, and a 1T1R memory cell.

4. The non-volatile memory of claim 3, wherein the 2T memory cell comprises: a selection tube, a storage tube, a WL port, a CG port, a BL port and a SL port; the WL port of the 2T memory cell is connected with the grid electrode of the 2T memory cell selection tube; the CG port of the 2T memory cell is connected with the grid electrode of the storage tube of the 2T memory cell; the BL port of the 2T memory cell is connected with the drain electrode of the 2T memory cell selection tube; the source electrode of the 2T storage unit selection tube is connected with the drain electrode of the 2T storage unit storage tube; the source of the 2T memory cell storage tube is connected with the SL port of the 2T memory cell.

5. The non-volatile memory of claim 3, wherein the 2T memory cell comprises: a selection tube, a storage tube, a WL port, a BL port and a SL port; the WL port of the 2T memory cell is connected with the grid electrode of the 2T memory cell selection tube; the BL port of the 2T storage unit is connected with the drain electrode of the storage tube of the 2T storage unit; the source electrode of the 2T storage unit storage tube is connected with the drain electrode of the 2T storage unit selection tube; the source of the 2T memory cell selection tube is connected with the SL port of the 2T memory cell.

6. The non-volatile memory of claim 3, wherein the 1.5T memory cell comprises: the system comprises a double-gate storage tube, a WL port, a CG port, a BL port and an SL port; the single-layer grid electrode of the double-grid storage tube is connected with the WL port of the 1.5T storage unit; the upper grid electrode of the double-layer grid electrode of the double-grid storage tube is connected with the CG port of the 1.5T storage unit; the lower grid electrode of the double-layer grid electrode of the double-grid storage tube is floating; the drain electrode of the double-gate storage tube is connected with the BL port of the 1.5T storage unit; and the source electrode of the double-gate storage tube is connected with the SL port of the 1.5T storage unit.

7. The non-volatile memory of claim 3, wherein the 1T memory cell comprises: a storage tube, a WL port, a BL port and a SL port; the grid electrode of the storage tube of the 1T storage unit is connected with the WL port of the 1T storage unit; the drain electrode of the 1T memory cell is connected with the BL port of the 1T memory cell; the source of the 1T memory cell is connected to the SL port of the 1T memory cell.

8. The non-volatile memory according to claim 3, wherein said MT memory cell comprises: first to kWL th ports, a BL port and a SL port arranged in this order; WL ports of m MT memory units in the same row form a k multiplied by m array structure; the MT memory unit further includes: the first selection tube, the first to the k-th storage tubes and the second selection tube are connected in sequence; the drain electrode of the first selection tube of the MT memory cell is connected with the BL port of the MT memory cell; the source electrode of the first selection tube of the MT storage unit is connected with the drain electrode of the first storage tube of the MT storage unit; the source electrode of the jth storage tube of the MT storage unit is connected with the drain electrode of a jth +1 storage tube, wherein j belongs to [1, k-1 ]; the gate of the ith storage tube of the MT storage unit is connected with the iWL th port, wherein i belongs to [1, k ]; the source electrode of the kth storage tube of the MT storage unit is connected with the drain electrode of the second selection tube of the MT storage unit; the source of the second selection tube of the MT memory cell is connected with the SL port of the MT memory cell.

9. The non-volatile memory of claim 3 wherein said 1T1R memory cell comprises a select transistor and a two port memory device, a WL port, a BL port, a SL port; the gate of the 1T1R memory cell selection transistor is connected to the WL port of the 1T1R memory cell; the drain of the 1T1R memory cell selection transistor is connected to the BL port of the 1T1R memory cell; the source of the 1T1R memory cell select transistor is connected to one end of a two-port memory device, and the other end of the two-port memory device is connected to the SL port of the 1T1R memory cell.

10. The non-volatile memory of claim 3 wherein said 1T1R memory cell comprises a select transistor and a two port memory device, a WL port, a BL port, a SL port; the gate of the 1T1R memory cell selection transistor is connected to the WL port of the 1T1R memory cell; the source of the 1T1R cell select transistor is connected to the SL port of the 1T1R cell; the drain of the selection tube is connected with one end of the two-port memory device, and the other end of the two-port memory device is connected with the BL port of the 1T1R memory cell.

11. The non-volatile memory according to any one of claims 9 or 10, wherein the two-port memory device is any one of a resistive memory device, a magnetoresistive memory device, a phase-change memory device, a ferroelectric memory device, and a carbon nanotube memory device.

12. A non-volatile memory according to any one of claims 4 to 10 wherein b is_i×I_{Leakage current}＜I_{Judging the current}(ii) a Wherein b is_iThe number of rows of the storage units contained in the ith storage module; i is an e [1, n ]]；I_{Leakage current}Leakage current in the off state of the memory cell, I_{Judging the current}The judgment current is used for reading the data of the memory cell.

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