CN112947738A - Intelligent terminal power supply system and intelligent terminal standby and wake-up method - Google Patents

Abstract

Translated fromChinese

本发明提出了一种智能终端电源系统及智能终端待机、唤醒方法，用以满足多种唤醒源的唤醒需求，降低功耗。智能终端电源系统包括PMU、CMU和电源域，电源域包括CPU电源域，休眠不掉电电源域和休眠可掉电电源域，CPU处于CPU电源域，唤醒源、DRAM存储单元、WPCTL、休眠标记寄存器、休眠类型寄存器和恢复地址寄存器处于休眠不掉电电源域，除唤醒源以外的其他功能模块、DRAM控制单元、GIC处于休眠可掉电电源域；所述WPCTL，用于控制唤醒源的唤醒通路；时钟管理单元，用于为唤醒源提供时钟信号；PMU，用于为各个电源域供电。

The present invention proposes an intelligent terminal power supply system and an intelligent terminal standby and wake-up method, which are used to meet the wake-up requirements of various wake-up sources and reduce power consumption. The intelligent terminal power system includes PMU, CMU, and power domain. The power domain includes the CPU power domain, the power domain that cannot be powered down during sleep, and the power domain that can be powered off during sleep. The CPU is in the CPU power domain, and the wake-up source, DRAM storage unit, WPCTL, and sleep flags The registers, the sleep type register and the recovery address register are in the power supply domain without power down, and other functional modules except the wake-up source, DRAM control unit, and GIC are in the power supply domain that can be powered down during sleep; the WPCTL is used to control the wake-up of the wake-up source channel; clock management unit, used to provide clock signals for wake-up sources; PMU, used to supply power to each power domain.

Description

Intelligent terminal power supply system and intelligent terminal standby and wake-up method

Technical Field

The invention relates to the technical field of intelligent terminals, in particular to an intelligent terminal power supply system and intelligent terminal standby and awakening methods.

Background

Compare traditional terminal, intelligent terminal is to characteristic data's snatching and data preprocessing ability improve greatly. The intelligent terminal has the following characteristics: 1) the intelligent terminal has high performance, the intelligent terminal is developed very quickly, new applications emerge endlessly, and the intelligent terminal is required to have high performance for a large number of applications; 2) the intelligent terminal has high integration level and is very sensitive to the size, so that the processor is required to have higher integration level, more devices can be integrated on a smaller size, the size of the whole terminal can be controlled, the complexity of design can be reduced, and the reliability of the system is improved.

In addition, since the intelligent terminal is usually powered by a battery, the intelligent terminal is very sensitive to system power consumption and requires a processor to have low power consumption. In the prior art, the following two schemes are generally adopted to reduce the power consumption of the intelligent terminal system:

the first scheme is that aiming at a system on chip using a Monitor CPU: the Monitor CPU and its ram are charged in the standby scene. The Monitor CPU circularly monitors whether a wake-up source input exists or not, and if so, the wake-up flow is taken to wake up the system. In the scheme, the Monitor CPU and ram thereof are electrified during standby, so that the standby power consumption is still high.

Scheme two, use PMU (power management unit) on/off key: only a dram (dynamic random access memory) storage unit and other necessary resources are charged in the standby state, the dram storage unit enters a self-refreshing low-power-consumption mode, and the standby power consumption is low. The PMU on/off key is required to be manually pressed when the device is awakened. The disadvantage of this method is that the wake-up source only supports PMU manual wake-up, and cannot meet the wake-up requirements of various wake-up sources.

Disclosure of Invention

The embodiment of the invention provides an intelligent terminal power supply system and an intelligent terminal standby and awakening method, which are used for meeting the awakening requirements of various awakening sources in an intelligent terminal and reducing the power consumption of the intelligent terminal system.

In a first aspect, an intelligent terminal power supply system is provided, which includes a power management unit PMU, a clock management unit CMU and a power domain, where the power domain includes a CPU power domain, a hibernate non-powered down power domain and a hibernate powered down power domain, where a CPU is in the CPU power domain, a wake-up source, a DRAM memory unit, a wake-up controller WPCTL, a hibernate flag register, a hibernate type register and a resume address register are in the hibernate non-powered down power domain, and other functional modules except the wake-up source, a DRAM control unit and a general interrupt controller GIC in the intelligent terminal are in the hibernate powered down power domain; wherein:

the WPCTL is used for controlling a wake-up path of a wake-up source;

the clock management unit is used for providing a clock signal for the awakening source;

and the power management unit is used for supplying power to each power domain.

In one embodiment, the sleep levels of the intelligent terminal include a primary sleep and a secondary sleep, wherein the primary sleep is a CPU power domain only sleep, and the secondary sleep is a CPU power domain, a sleep power-down power domain sleep and a sleep power-down power domain non-sleep.

In a second aspect, a standby method for primary dormancy of an intelligent terminal is provided, which includes:

writing a CPU recovery address in a recovery address register;

assigning the sleep type register to be a first-level sleep;

enabling a CPU wake-up path between the output end of the interrupt controller and the wake-up controller and between the interrupt controller and the power management unit;

setting a sleep flag register;

and powering down the CPU power domain.

In a third aspect, a method for waking up a primary sleep of an intelligent terminal is provided, which includes:

when the GIC receives an interrupt request, sending a CPU power domain power-on request to the PMU through the wake-up path;

and after the CPU power domain is powered on, the CPU controls and executes a bootstrap program.

The method for controlling and executing the bootstrap program by the CPU specifically comprises the following steps:

the CPU judges whether the dormancy flag register is set;

if the sleep flag register is set, the sleep flag register is cleared, and if the sleep flag register is judged to be in the first-level sleep according to the sleep type register, the wake-up path is closed, and the system is skipped to the recovery address register to execute the system recovery process; if the sleep type register judges that the sleep is the secondary sleep, executing a secondary awakening process;

and if the sleep register is judged not to be set, the CPU controls to enter a normal system boot flow.

In a fourth aspect, a standby method for secondary dormancy of an intelligent terminal is provided, which includes:

awakening the source to enable the Clk gaming and/or Power gaming of the source;

setting a wake-up condition, and enabling a wake-up path between a wake-up source and the WPCTL and the PMU;

writing a CPU recovery address into a recovery address register;

assigning the sleep type register to be a secondary sleep;

setting the sleep flag register;

the CPU power domain and the sleep power down capable power domain are powered down.

In one embodiment, after the wake-up source enables its own Clk and/or Power Gating, the method further includes:

and the wake-up source switches the clock source of the wake-up source to the low-frequency clock source.

In one embodiment, before powering down the CPU power domain and the hibernate powerdown capable power domain, the method further comprises:

locking the critical section code into a CPU cache or copying the critical section code to a static random access memory (Sram);

and executing the critical section codes and controlling the Dram memory cell to enter a self-refreshing low-power-consumption mode.

In a fifth aspect, a method for waking up a secondary sleep of an intelligent terminal is provided, which includes:

after receiving a wake-up signal sent by the wake-up source, the WPCTL sends a CPU power domain power-on request to the PMU;

and after the CPU power domain is powered on, the CPU controls and executes a bootstrap program.

The method for controlling and executing the boot program by the CPU specifically comprises the following steps:

the CPU judges whether the dormancy flag register is set;

if the dormancy flag register is set, the dormancy flag register is cleared, and if the dormancy type register is judged to be a first-level dormancy, a first-level awakening process is executed; if the secondary dormancy is judged according to the dormancy type register, the CPU controls the PMU to power on the dormancy power-down domain; controlling the Dram to exit from the self-refreshing low-power-consumption mode, closing the awakening path, and jumping to a recovery address register to execute a system recovery process;

and if the sleep flag register is not set, the CPU controls to enter a normal system boot flow.

By adopting the technical scheme, the invention at least has the following advantages:

in the intelligent terminal power supply system and the intelligent terminal standby and awakening method, the intelligent terminal power supply domain is divided into the CPU power supply domain, the three parts of the dormant non-power-down power supply domain and the dormant power-down power supply domain are respectively controlled, the awakening controller is additionally arranged in the dormant non-power-down power supply domain, and an awakening signal generated by an awakening source is taken over when the CPU power supply domain enters a dormant state, so that when the awakening signal is generated, a PMU (power management unit) can be rapidly notified to power on the CPU power supply domain to start the system, and the energy consumption of the intelligent terminal is reduced while various awakening requirements of the awakening source are met.

Drawings

Fig. 1 is a schematic structural diagram of an intelligent terminal power supply system according to an embodiment of the invention;

fig. 2a is a schematic flow chart illustrating an implementation of a standby method for primary dormancy of an intelligent terminal according to an embodiment of the present invention;

fig. 2b is a schematic flow chart of an implementation of a wake-up method for primary sleep of an intelligent terminal according to an embodiment of the present invention;

fig. 3a is a schematic flow chart illustrating an implementation of a standby method for secondary sleep of an intelligent terminal according to an embodiment of the present invention;

fig. 3b is a schematic flow chart illustrating an implementation process of a method for waking up a secondary sleep of an intelligent terminal according to an embodiment of the present invention.

Detailed Description

To further explain the technical means and effects of the present invention adopted to achieve the intended purpose, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.

It should be noted that the terms "first", "second", and the like in the description and the claims of the embodiments of the present invention and in the drawings described above are used for distinguishing similar objects and not necessarily for describing a particular order or sequence. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein.

Reference herein to "a plurality or a number" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Referring to fig. 1, which is a schematic structural diagram of an intelligent terminal Power supply system according to an embodiment of the present invention, the intelligent terminal Power supply system according to an embodiment of the present invention includes a PMU (Power management unit) 11, a CMU (clock management unit) 12, and a Power Domain, where the Power Domain includes a CPU (central processing unit) Power Domain (CPU Power Domain)131, an Always-on Power Domain (Always-off Power Domain) 132, and a sleep Power-down Power Domain (Other Power Domain)133, where the CPU is located in the CPU Power Domain, a Wake-up Source (Wake-up Source), a WPCTL (Wake-up controller), a DRAM (dynamic random access memory) Storage unit (DRAM Storage), a sleep Flag register (Standby Flag), a sleep Type register (Standby Type register), and a Resume Address register (Resume Address) are located in the sleep Power-down Power Domain, and Other function modules (devices) in the intelligent terminal than the Wake-up Source and the Wake-up Source are located in the sleep Power-down Power Domain, The DRAM control unit (Dram Controller), GIC (general interrupt Controller) is in the dormant powered down power domain. The WPCTL is used for controlling a wake-up path of a wake-up source; the clock management unit is used for providing a clock signal for the awakening source; and the power management unit is used for supplying power to each power domain.

During specific implementation, the wake-up source may be a functional module in the intelligent terminal device, for example, an infrared module, a bluetooth module, a wifi (wireless fidelity) module, a usb (universal serial bus) module, and the like.

In the intelligent terminal power supply system shown in fig. 1:

1) and the PMU unit is used for supplying power to each power domain. The main power domains are: CPU power domain, dormancy non-power-down power domain and dormancy power-down power domain.

2) And the CMU unit is used for providing a clock source for each device on the system.

3) CPU unit, and program executing mechanism.

4) And the wake-up source mainly comprises a device which can generate a wake-up signal (Wakeup Irq) during the sleep period of the system and inform the PMU of powering on the CPU unit through the WPCTL.

5) GIC Distributor, a device interrupt controller during normal operation of the system.

6) And the WPCTL is used for controlling a path of each wake-up source device to send a power-on instruction to the PMU.

7) The Dram memory cells, i.e., the memory cells for program instructions and data, may enter a self-refresh low power consumption state.

8) And the Dram control unit is used for controlling the Dram to enter and exit the self-refreshing low-power consumption state.

9) And critical section codes refer to operation codes related to self-refresh states of the Dram memory cells, power-down operation codes of partial power domains and the like.

According to the intelligent terminal power domain provided by the embodiment of the invention, a system power supply is divided into a CPU power domain, a dormant non-power-down power domain and a dormant power-down power domain. Based on this, in the embodiment of the present invention, the sleep level of the intelligent terminal may include a primary sleep and a secondary sleep, where:

the first-level dormancy is that only the CPU power domain sleeps, other power domains work normally, the dormancy level is usually used in the normal working period of the system, and the CPU can have a short rest scene. For example, the power-down scenario may be entered when the CPU executes an idle thread.

The secondary dormancy is that the CPU power domain, the dormancy power-down power domain are powered off, and the dormancy power-down-free power domain is not powered off, namely the dormancy power-down-free power domain keeps a power-on state. In this sleep level, other functional modules except the enabled wake-up source turn off their Power Gating (Power Gating) and/or clock Gating (Clk Gating), the enabled wake-up source remains powered on, and its clock source can be switched to the low-frequency clock source to generate the wake-up signal. The Dram storage unit keeps supplying power and enters a self-refreshing low-power consumption mode, the Dram control unit is powered down, and the dormancy marking register, the dormancy type register and the restoration address register keep supplying power.

In the embodiment of the invention, a CPU System is in an independent power domain, and can be independently powered down temporarily when a CPU idle is in use.

In specific implementation, the wake-up source, the Dram Storage unit (Dram Storage), the wake-up controller (WPCTL), the sleep flag register, the sleep type register and the resume address register are powered by the sleep non-power-down power domain, and are powered on when the CPU system is in sleep.

The WPCTL is in a power domain with no power failure during sleep and is used for controlling the awakening paths of the awakening sources of all paths. The wake-up source is in the dormant non-power-down power domain for generating a system wake-up signal, and the corresponding power gating/clk gating can be used to control whether the wake-up source device enables the wake-up function. The Dram storage unit is in a sleep power-off-free domain and is used for saving the program execution environment during sleep, and the program execution environment can be quickly restored after awakening. The Standby Flag/Standby Type/Resume Address register is located in the power-off-sleep domain, is used for recording a sleep Flag, a sleep Type and a recovery entry, and is used for controlling the program flow of the wake-up stage.

In specific implementation, the GIC general interrupt Controller (GIC distributor), the Dram control unit (Dram Controller) and other functional modules except the wake-up source use the sleep power-down power domain to supply power, and the power is down when the CPU system is in sleep.

And other functional modules except the awakening source are in a dormant power-down power domain, and can be powered down during the dormancy of the secondary dormancy system. And the Dram control unit can be powered down after the Dram memory cell enters the self-refreshing low-power consumption state. The interrupt controller (GIC) in normal operation of the system can be powered down in sleep, and the relevant wake-up signal is taken over by the WPCTL.

Based on the intelligent terminal power supply system, the embodiment of the invention also provides a standby method and a wake-up method of the primary dormancy and the secondary dormancy of the intelligent terminal respectively, which are introduced in combination with the attached drawings of the specification respectively.

As shown in fig. 2a, a schematic flow chart of an implementation of a standby method for primary dormancy of an intelligent terminal according to an embodiment of the present invention may include the following steps:

s201, writing a CPU recovery address in the recovery address register.

S202, assigning the sleep type register as a primary sleep.

In this step, the value of the sleep type register is set to the primary sleep.

And S203, enabling a CPU wake-up path between the output end of the interrupt controller and the wake-up controller and the power management unit.

In this step, c) enables a CPU wakeup path of the GIC Out (GIC output terminal) - > WPCTL- > PMU so as to wake up the CPU when a system interrupt request is received.

S204, setting the sleep flag register.

In this step, the Standby Flag is set, so that the Flag is queried in the Boot flow when the CPU is powered on again.

And S205, powering down the CPU power domain.

Correspondingly, an embodiment of the present invention further provides a method for waking up a primary sleep of an intelligent terminal, as shown in fig. 2b, which may include the following steps:

s211, when the GIC receives the interrupt request, the CPU power domain power-on request is sent to the PMU through the enabled wake-up path.

In specific implementation, a functional module in the intelligent terminal sends an interrupt request to the GIC, and after the GIC receives the interrupt request, the GIC sends a CPU Power Domain Power-on request to the PMU through GIC- > WPCTL- > PMU.

S212, powering on a CPU power domain.

In this step, after the PMU powers up the CPU system again, the CPU executes the boot program.

Specifically, the execution of the boot program by the CPU may include the steps of:

s213, judging whether the sleep flag register is set, if so, executing the step S214, otherwise, executing the step S217.

S214, clearing the dormancy flag register.

S215, acquiring the value of the sleep type register, executing the step S216 if the sleep type register is a primary sleep type register, and executing the step S219 if the sleep type register is a secondary sleep type register.

S216, closing the wake-up path, and executing the step S218.

In this step, the GIC- > WPCTL- > PMU awakening path is closed.

And S217, the CPU controls to enter a normal system boot flow, and the flow is ended.

In this step, if the sleep register is not set, the normal system boot process is entered.

S218, jumping to the recovery address register to execute the system recovery process, and ending the process.

And S219, executing a secondary awakening process.

The secondary wake-up process may be the process shown in fig. 3b in the embodiment of the present invention, and details are not described here.

As shown in fig. 3a, an implementation flow diagram of a standby method for secondary hibernation of an intelligent terminal according to an embodiment of the present invention may include the following steps:

s301, enabling the Clk playing and/or Power playing of the awakening source.

And S302, enabling a wake-up path between the wake-up source and the WPCTL and the PMU.

In this step, the wake-up source sets a wake-up condition and enables a wake-up path from the wake-up source to the WPCTL and then to the PMU.

S303, writing the CPU recovery address into the recovery address register.

And S304, assigning the sleep type register to be a secondary sleep.

In this step, the value of the sleep type register is set to be the second level sleep.

S305, setting the sleep flag register.

S306, the Dram memory cell enters a self-refresh low power consumption mode.

And S307, powering down the CPU power domain and the sleep power-down domain.

In this step, the CPU power domain and the hibernate powerdown capable power domain (including the Dram control unit) are powered down.

During specific implementation, a clock used as a wake-up source can select a high-frequency clock source and a low-frequency clock source, the wake-up source selects the high-frequency clock to complete a normal function when working normally, and in a system sleep stage, in order to further reduce the power consumption of the intelligent terminal, the wake-up source switches the clock source of the wake-up source to the low-frequency clock source and only enables the wake-up function, so that the standby power consumption of the intelligent terminal can be further saved.

In specific implementation, before executing step S306, the following steps may be further included: locking the critical section code into a CPU cache or copying the critical section code into a static random access memory (Sram); the critical section code is executed. By executing the steps, the standby power consumption of the intelligent terminal can be further saved. Through the step, the critical section codes (mainly comprising the Dram self-refresh codes and the power domain power-off codes) can be locked to the CPU Cache or copied to the Sram, and the Dram is prevented from being accessed after entering the self-refresh low-power-consumption mode.

Correspondingly, an embodiment of the present invention further provides a method for waking up the secondary sleep method of the intelligent terminal, as shown in fig. 3b, the method may include the following steps:

and S311, after receiving the wake-up signal sent by the wake-up source, the WPCTL sends a CPU power domain power-on request to the PMU.

In specific implementation, the wake-up source generates a wake-up signal when the set wake-up condition is met, and sends the wake-up signal to the WPCTL. The WPCTL sends a CPU power domain power-up request to the PMU.

And S312, powering on the CPU power domain.

In this step, the system is restarted, and after the CPU power domain is powered on, the CPU controls to execute the boot program, which may specifically include the following steps;

s313, judging whether the sleep flag register is set, if so, executing step S314, and if not, executing step S319.

And S314, clearing the dormancy flag register.

In specific implementation, if the sleep Flag register is set in step S313, the Standby Flag register is cleared.

S315, obtaining the value of the sleep type register, if the sleep type register is a secondary sleep type register, executing the step S316, and if the sleep type register is a primary sleep type register, executing the step S321.

And S316, powering up the power-down power domain.

Specifically, the CPU controls the PMU to power up the sleep power down domain (including the Dram control unit).

And S317, controlling Dram to exit the self-refreshing low-power-consumption mode.

S318, closing the wake-up path and executing the step S320.

In the step, a WPCTL- > PMU awakening path is closed.

And S319, the CPU controls to enter a normal system boot flow, and the flow is ended.

In this step, if the sleep register is not set, the normal system boot process is entered.

S320, jumping to a recovery address register to execute a system recovery process, and ending the process.

S321, executing a primary awakening process.

In specific implementation, the implementation of step S321 may refer to the flow shown in the table of fig. 2, which is not described herein again.

In the intelligent terminal power supply system and the intelligent terminal Standby and wake-up method provided by the embodiment of the invention, the wake-up source, the wake-up path and the power-down related power domain are enabled and the Standby Flag is set before the CPU system enters the sleep state. After the wake-up signal is generated, the wake-up controller informs a PMU to power on the system for restarting, and the start-up process determines whether to go a normal boot process or a system recovery process by judging the Standby Flag. And when the system is in a dormant state, the dormancy flag register is set, so that when the system is restarted, whether the normal starting process or the system recovery process is carried out is determined by judging the flag, and on the basis of meeting the low power consumption and the low cost, the diversified awakening requirements can be met.

While the invention has been described in connection with specific embodiments thereof, it is to be understood that it is intended by the appended drawings and description that the invention may be embodied in other specific forms without departing from the spirit or scope of the invention.

Claims (10)

1. An intelligent terminal power supply system is characterized by comprising a Power Management Unit (PMU), a Clock Management Unit (CMU) and a power domain, wherein the power domain comprises a Central Processing Unit (CPU) power domain, a dormant non-power-down power domain and a dormant power-down power domain, a CPU is positioned in the CPU power domain, a wake-up source, a Dynamic Random Access Memory (DRAM) storage unit, a wake-up controller (WPCTL), a dormancy marking register, a dormancy type register and a recovery address register are positioned in the dormant non-power-down power domain, and other functional modules except the wake-up source, the DRAM control unit and a General Interrupt Controller (GIC) in an intelligent terminal are positioned in the dormant power-down power domain; wherein:

the WPCTL is used for controlling a wake-up path of a wake-up source;

the clock management unit is used for providing a clock signal for the awakening source;

and the power management unit is used for supplying power to each power domain.

2. The system of claim 1, wherein the sleep levels of the intelligent terminal comprise a primary sleep and a secondary sleep, wherein the primary sleep is a CPU-only power domain sleep, and the secondary sleep is a CPU power domain, a sleep power-down capable power domain power down, and a sleep power-down free power domain power down.

3. A standby method for one-level hibernation of an intelligent terminal according to claim 2, comprising:

writing a CPU recovery address in a recovery address register;

assigning the sleep type register to be a first-level sleep;

enabling a CPU wake-up path between the output end of the interrupt controller and the wake-up controller and between the interrupt controller and the power management unit;

setting a sleep flag register;

and powering down the CPU power domain.

4. A wake-up method for the standby method of the intelligent terminal as claimed in claim 3, comprising:

when the GIC receives an interrupt request, sending a CPU power domain power-on request to the PMU through the wake-up path;

and after the CPU power domain is powered on, the CPU controls and executes a bootstrap program.

5. The method according to claim 4, wherein the CPU controls execution of the boot program, and specifically comprises:

the CPU judges whether the dormancy flag register is set;

if the sleep flag register is set, the sleep flag register is cleared, and if the sleep flag register is judged to be in the first-level sleep according to the sleep type register, the wake-up path is closed, and the system is skipped to the recovery address register to execute the system recovery process; if the sleep type register judges that the sleep is the secondary sleep, executing a secondary awakening process;

and if the sleep register is judged not to be set, the CPU controls to enter a normal system boot flow.

6. A standby method for secondary dormancy of the intelligent terminal according to claim 2, comprising:

waking up a source to enable clock gating and/or power gating of the source itself;

setting a wake-up condition, and enabling a wake-up path between a wake-up source and the WPCTL and the PMU;

writing a CPU recovery address into a recovery address register;

assigning the sleep type register to be a secondary sleep;

setting the sleep flag register;

the CPU power domain and the sleep power down capable power domain are powered down.

7. The method of claim 6, wherein after waking up a source to enable its clock gating and/or power gating, further comprising:

and the wake-up source switches the clock source of the wake-up source to the low-frequency clock source.

8. The method of claim 6 or 7, wherein prior to powering down the CPU power domain and the hibernating powerdown capable power domain, further comprising:

locking the critical section code into a CPU cache or copying the critical section code to a static random access memory (Sram);

and executing the critical section codes and controlling the Dram memory cell to enter a self-refreshing low-power-consumption mode.

9. A wake-up method for the standby method of the intelligent terminal as claimed in claim 6, 7 or 8, comprising:

after receiving a wake-up signal sent by the wake-up source, the WPCTL sends a CPU power domain power-on request to the PMU;

and after the CPU power domain is powered on, the CPU controls and executes a bootstrap program.

10. The method according to claim 9, wherein the CPU controls execution of a boot program, specifically comprising:

the CPU judges whether the dormancy flag register is set;

if the dormancy flag register is set, the dormancy flag register is cleared, and if the dormancy type register is judged to be a first-level dormancy, a first-level awakening process is executed; if the secondary dormancy is judged according to the dormancy type register, the CPU controls the PMU to power on the dormancy power-down domain; controlling the Dram to exit from the self-refreshing low-power-consumption mode, closing the awakening path, and jumping to a recovery address register to execute a system recovery process;

and if the sleep flag register is not set, the CPU controls to enter a normal system boot flow.

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