CN112925641A - Satellite power supply lower computer system with 1553B interface chip replacing data storage - Google Patents

Abstract

A1553B interface chip replaces a satellite power supply lower computer system of a data memory and comprises a CPU minimum system module, a communication module, a telemetering acquisition module and an instruction execution module; the CPU minimum system module comprises a CPU and a peripheral circuit, wherein the CPU is used for executing a stored program, sending generated data to the communication module and reading required data from the communication module; the communication module comprises a 1553B interface chip and a peripheral circuit, the 1553B interface chip completes 1553B communication with the integrated electronic subsystem and simultaneously stores data sent by the CPU minimum system module; the telemetering acquisition module acquires various telemetering measurements and converts the telemetering measurements into digital quantity; the instruction execution module performs level instruction control on the power controller control mechanism through the latch and performs OC instruction control on the power controller control mechanism through the decoder and the OC instruction chip. The invention removes the data memory, and uses the memory space of the 1553B interface chip to access the data cache; the resource waste is avoided, the cost is saved, and the reliability is improved.

Description

Satellite power supply lower computer system with 1553B interface chip replacing data storage

Technical Field

The invention belongs to the field of satellite lower computers, and relates to a satellite power supply lower computer system with a 1553B interface chip replacing a data memory.

Background

In the application process of the lower computer of the satellite power supply controller, when the 1553B interface chip is used, the communication protocol does not always use all 1553B memory space for data transmission. Meanwhile, the space utilization rate of the data memory by the CPU is often low.

Due to the limitation of information transmission quantity of a satellite measurement and control system, telemetering data transmitted by the power controller to the integrated electronics through 1553B one-time communication is generally in the order of tens of bytes to hundreds of bytes, the memory capacity of a commonly used 1553B interface chip is 8192 bytes, most of memory space is redundant space, and the part of memory cannot be used in the whole satellite process.

The data caching capacity required in the whole lower computer program of the power controller is about hundreds to two kilobytes, which depends on the program coding mode, the memory capacity of a data memory commonly used by a lower computer system of the power controller is 8192 bytes, and most memory space is not used.

The 1553B interface chip and the data storage are aerospace-level chips with the smallest available memory space in the same type, and a small-capacity memory chip cannot be replaced, so that the memory space waste is caused to a certain extent on the premise of meeting the memory space derating.

Disclosure of Invention

The technical problem solved by the invention is as follows: the satellite power supply lower computer system overcomes the defects of the prior art and provides a 1553B interface chip for replacing a data memory.

The technical scheme of the invention is as follows:

A1553B interface chip replaces a satellite power supply lower computer system of a data memory and comprises a CPU minimum system module, a communication module, a telemetering acquisition module and an instruction execution module;

CPU minimum system module: the CPU is used for executing a stored program, sending data generated in the execution process to the communication module, and reading data required by the subsequent execution of the program from the communication module; acquiring digital quantity data converted by the telemetering acquisition module, and sending the data to the communication module; carrying out communication protocol analysis and decoding on the ground instruction transmitted by the communication module to obtain data and a control signal, and sending the data and the control signal to the instruction execution module;

a communication module: the system comprises a 1553B interface chip and a peripheral circuit thereof, and is used for receiving a ground instruction forwarded by an on-satellite integrated electronic subsystem and transmitting the ground instruction to a CPU minimum system module; simultaneously storing data sent by the CPU minimum system module;

a telemetry acquisition module: various remote measurements in the power controller are acquired through a multi-channel gate and an analog-to-digital converter, converted into digital quantity and sent to a CPU minimum system module;

the instruction execution module: the power controller control mechanism is subjected to level instruction control through the latch, and is subjected to OC instruction control through the decoder and the OC instruction chip.

Selecting a sub-address which is not used in a 1553B communication protocol as a memory space of a 1553B interface chip to ensure that the memory space is not accessed in a normal communication process

The communication module stores the data sent by the CPU minimum system module as follows:

step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin by the CPU through IO port operation;

step 2: the CPU selects a 1553B interface chip through bus writing operation, and writes low-byte data of data to be written into the memory into an address;

and step 3: and (3) shifting the address in the step (2) by 1 binary bit to the left, selecting a 1553B interface chip through bus writing operation, and writing the high byte data of the data to be written into the memory into the address after the left shift.

The way for the CPU minimum system module to read the data required by the subsequent execution of the program from the communication module is as follows:

step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin by the CPU through IO port operation;

step 2: the CPU selects a 1553B interface chip through bus reading operation, reads low-byte data of data to be read out of the memory of the 1553B interface chip into the CPU from a corresponding address, discards the data and regards the data as a sub-reading operation;

and step 3: the CPU selects the 1553B interface chip through bus reading operation, reads low-byte data of the data stored in the 1553B interface chip to be read out into the CPU from a corresponding address again, and stores the data;

and 4, step 4: and (3) leftwards shifting the address in the step (3) by 1 binary bit, selecting a 1553B interface chip through bus reading operation, reading high-byte data of the data to be read out of the memory of the 1553B interface chip into a CPU from a corresponding address, and storing the data.

The program stored in the CPU comprises an application layer, a system layer and an interface layer; wherein:

the application layer completes each specific function of the on-satellite software;

the system layer completes CPU initialization, OC instruction chip initialization, level instruction chip initialization, 1553B interface chip interrupt control, timing interrupt control, on-track code injection verification and injection;

the interface layer completes the input and output management of all software external interface data, and the management comprises interface initialization of a 1553B interface chip, data input and output management of the 1553B interface chip, reset drive management of the 1553B interface chip, data cache storage of the 1553B interface chip, drive management of an analog-to-digital converter, OC instruction drive management and level instruction drive management.

In the instruction execution module, the latch converts data in the data bus into a level instruction and outputs the level instruction to the power controller control mechanism.

In the instruction execution module, the decoder converts the control signal into a channel chip selection for selecting the OC instruction chip; and the OC instruction chip converts the channel chip selection into an OC instruction of a corresponding output port and outputs the OC instruction to the power controller control mechanism.

The capacity of the 1553B interface chip can simultaneously meet all data caching requirements of an appointed program and 1553B data communication caching requirements.

Compared with the prior art, the invention has the beneficial effects that:

according to the invention, the unused memory space of the 1553B interface chip is utilized, so that the data memory chip is saved, and the cost is saved; 1553B interface chip resources are fully utilized, and resource waste is avoided; meanwhile, the use of components is reduced, and the reliability of the lower computer module of the satellite power supply controller is improved.

Drawings

FIG. 1 is a schematic diagram of a lower computer system of a power supply controller of the present invention;

FIG. 2 is a diagram of the software platform architecture of the CPU minimal system of the present invention;

FIG. 3 is a flow chart of the data caching function write of the present invention;

FIG. 4 is a flow chart of the data caching function read-out of the present invention.

Detailed Description

The invention is further elucidated with reference to the drawing.

According to the invention, a data memory is removed from a lower computer system of the power controller, and the memory space of a 1553B interface chip is used for accessing the data cache; under the condition of certain quality grade, the number of components is reduced, and the reliability of the module is improved.

The specific design is as follows.

As shown in fig. 1, the invention provides a system for replacing a data memory by a 1553B interface chip based on a satellite power controller. The system comprises a CPU minimum system module, a communication module, a telemetry acquisition module and an instruction execution module. The minimum system module of the CPU is a CPU and a peripheral circuit, and completes the execution of a program and the realization of functions; the communication module is mainly used for executing the stored program, sending data generated in the executing process to the communication module, and reading data required by the subsequent execution of the program from the communication module; acquiring digital quantity data converted by the telemetering acquisition module, and sending the data to the communication module; and analyzing and decoding the communication protocol of the ground instruction transmitted by the communication module to obtain a level instruction and an OC instruction, and sending the level instruction and the OC instruction to the instruction execution module.

The communication module completes 1553B communication with the integrated electronic subsystem (or the measurement and control subsystem or the data transmission subsystem). The system comprises a CPU minimum system module, a ground command receiving module, a ground command transmitting module and a ground command transmitting module, wherein the ground command is used for receiving a ground command transmitted by an on-satellite integrated electronic subsystem and transmitting the ground command to the CPU minimum system module; and simultaneously storing the data sent by the minimum system module of the CPU.

The telemetering acquisition module finishes acquisition of telemetering data and converts the telemetering data into digital quantity through a multi-channel gate, a telemetering voltage filter circuit and an analog-to-digital (AD) converter, and the multi-channel gate selects one of a plurality of channels of input analog quantity to output through a control signal; the voltage filter circuit filters high-frequency noise of the telemetering signal and improves driving capability. The instruction execution module executes the level instruction through the latch, and executes the OC instruction through the decoder and the OC driving chip (the instruction execution module can also execute the OC instruction through the latch and the triode). Wherein the CPU minimum system module does not contain a data memory.

The CPU minimum system module comprises a CPU, a crystal oscillator, a bus buffer, an address latch, a program memory, a hardware watchdog, a chip selection decoder and no data memory; CPU executes corresponding program function, and does not contain large capacity on-chip data memory; the crystal oscillator generates a square wave with fixed frequency to provide a clock input signal for the CPU; the bus buffer enhances the driving current capability of the CPU to a data bus or an address bus; the address latch latches a data bus of the data low byte and enhances the driving current capability from the CPU to the address bus; the program memory stores the burned binary program codes and the CPU reads the internal program; the hardware watchdog resets the CPU when the CPU is affected by single event upset and the like to cause the program to run away; the chip selection decoder converts the address signal in the address bus into a chip selection signal to carry out the gating of the device.

The CPU communicates with the bus by writing or reading corresponding data of the 1553B interface chip; the capacity of the 1553B interface chip can simultaneously meet all data caching requirements of the appointed program function and 1553B data communication caching requirements.

And the instruction execution unit comprises a latch, a decoder and an OC instruction chip. The latch converts the data in the data bus into a level instruction and outputs the level instruction; the decoder converts the control signal into channel chip selection for selecting the OC instruction chip; the OC instruction chip converts the channel chip selection into an OC instruction of a corresponding output port.

Fig. 2 is a block diagram showing a software implementation stored in the CPU of the present invention. The software platform stored in the CPU of the invention comprises an application layer, a system layer and an interface layer. Wherein:

the application layer mainly completes various specific functions of satellite software, such as receiving, analyzing and executing of remote control instructions of comprehensive electronic forwarding, framing and packaging of telemetering acquired data, balancing management of the storage battery, ampere-hour meter estimation of the storage battery, overcharge/overdischarge protection of the storage battery and the like.

The system layer comprises control on a minimum system layer and mainly completes CPU initialization, OC instruction chip initialization, level instruction initialization, 1553B interrupt control, timing interrupt control, on-track code injection verification and injection and the like.

The interface layer comprises all software external interface data input and output management and mainly completes interface initialization of a 1553B interface chip, data input and output management of the 1553B interface chip, reset drive management of the 1553B interface chip, data cache storage of the 1553B interface chip, drive management of an analog-to-digital converter, OC instruction drive management, level instruction drive management and the like.

As shown in fig. 3, the data caching function performs a data storage process, and the CPU puts the data to be stored into the 1553B interface chip through the following steps.

Step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin through IO port operation;

step 2: selecting a 1553B interface chip through bus writing operation, and writing low-byte data of data to be written into the memory into an address;

and step 3: and (3) shifting the address in the step (2) by 1 binary bit to the left, selecting a 1553B interface chip through bus writing operation, and writing the high byte data of the data to be written into the memory into the address after the left shift.

As shown in fig. 4, a flow of data reading by the data cache storage function exists, because there is a sub-read operation on the read sequence of the 1553B interface chip, that is, an address needs to be written into the interface chip when the first chip selection is enabled, the same address needs to be written and data needs to be read when the second chip selection is enabled, and the CPU reads the data cache to be stored from the 1553B interface chip to the CPU by the following steps.

Step 1: selecting a memory/register pin of a 1553B interface chip as a level corresponding to the memory pin by the CPU through IO port operation;

step 2: selecting a 1553B interface chip through bus reading operation, reading low-byte data of data to be read out of a 1553B memory into a CPU from a corresponding address, discarding the data, and regarding the data as a sub-reading operation;

and step 3: selecting a 1553B interface chip through bus reading operation, reading low-byte data of data to be read out of a 1553B memory into a CPU (central processing unit) from a corresponding address again, and storing the data;

and 4, step 4: and (3) leftwards shifting the address in the step (2) or the step (3) by 1 binary bit, selecting a 1553B interface chip through bus reading operation, reading high-byte data of the data to be read out of the 1553B memory into a CPU from a corresponding address, and storing the data.

In addition, before program coding, a 1553B memory space corresponding to each variable needs to be allocated in advance, and a sub-address which is not used in a communication protocol is selected to ensure that the memory space is not accessed in a normal communication process; the read-write drive function is divided into two versions called by a main program and an interrupt program respectively, otherwise if the read-write drive function is interrupted when executed in the main program, local variables in the read-write drive function are rewritten, so that read-write data after the interruption is skipped are incorrect; and configuring a fixed sub-address for a 1553B memory space corresponding to the variable, and configuring the sub-address into illegal transmission, reception and broadcasting, thereby avoiding misoperation of the sub-address by comprehensive electrons.

According to the invention, a 1553B interface chip is used for replacing a data memory, and under the condition that 1553B bus communication is used in a lower computer system of a satellite power supply controller, a lower computer CPU minimum system does not comprise the data memory; when the program reads and writes the data cache, the corresponding variables are stored in the memory of the 1553B interface chip, and the driver is programmed to read and write the data in the memory of the 1553B interface chip.

In the hardware composition of the invention, a 1553B interface chip is used for replacing a data memory, and when the software code is realized, the data is cached and stored in the 1553B interface chip.

According to the invention, the unused memory space of the 1553B interface chip is utilized, the cost is saved, and the reliability of the lower computer module of the satellite power supply controller is improved. Its advantages and beneficial effects are:

1) the lower computer system of the satellite power supply controller saves a data memory chip and saves cost;

2) 1553B interface chip resources are fully utilized, and resource waste is avoided;

3) the use of components is reduced, and the reliability of model products is improved.

Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.

Claims (8)

Translated fromChinese

1.一种1553B接口芯片代替数据存储器的卫星电源下位机系统，其特征在于：包括CPU最小系统模块、通信模块、遥测采集模块和指令执行模块；1. a 1553B interface chip replaces the satellite power supply lower computer system of data memory, it is characterized in that: comprise CPU minimum system module, communication module, telemetry acquisition module and instruction execution module;CPU最小系统模块：包括CPU及外围电路，所述CPU用于执行存储的程序，并将执行过程中产生的数据发送给通信模块，同时从通信模块中读取程序后续执行需要的数据；获取遥测采集模块转换的数字量数据，将数据发送给通信模块；对通信模块传送的地面指令进行通信协议解析和译码，得到数据和控制信号，发送给指令执行模块；CPU minimum system module: including CPU and peripheral circuits, the CPU is used to execute the stored program, send the data generated during the execution process to the communication module, and read the data required for subsequent execution of the program from the communication module at the same time; obtain telemetry Collect the digital data converted by the module, and send the data to the communication module; perform communication protocol analysis and decoding on the ground commands transmitted by the communication module, obtain data and control signals, and send them to the command execution module;通信模块：包括1553B接口芯片及其外围电路，用于接收星上综合电子分系统转发的地面指令，并传送给CPU最小系统模块；同时存储CPU最小系统模块发送的数据；Communication module: including the 1553B interface chip and its peripheral circuits, which are used to receive ground commands forwarded by the onboard integrated electronic subsystem, and transmit them to the minimum system module of the CPU; at the same time, store the data sent by the minimum system module of the CPU;遥测采集模块：通过多路选通器和模数转换器采集电源控制器中的各类遥测量，并将其转换为数字量，发送给CPU最小系统模块；Telemetry acquisition module: collect all kinds of telemetry in the power supply controller through multiplexers and analog-to-digital converters, convert them into digital quantities, and send them to the minimum system module of the CPU;指令执行模块：根据数据和控制信号，通过锁存器对电源控制器控制机构进行电平指令控制，通过译码器和OC指令芯片对电源控制器控制机构进行OC指令控制。Command execution module: According to the data and control signals, the power supply controller control mechanism is controlled by the level command through the latch, and the power controller control mechanism is controlled by the OC command through the decoder and the OC command chip.2.根据权利要求1所述的一种1553B接口芯片代替数据存储器的卫星电源下位机系统，其特征在于，选取1553B通信协议中不使用的子地址作为1553B接口芯片的内存空间，确保该内存空间在正常的通信过程中不被访问。2. a kind of 1553B interface chip according to claim 1 replaces the satellite power supply lower computer system of data storage, it is characterized in that, choose the sub-address not used in 1553B communication protocol as the memory space of 1553B interface chip, ensure this memory space Not accessed during normal communication.3.根据权利要求1所述的一种1553B接口芯片代替数据存储器的卫星电源下位机系统，其特征在于，通信模块存储CPU最小系统模块发送数据的方式如下：3. a kind of 1553B interface chip according to claim 1 replaces the satellite power supply lower computer system of data memory, it is characterized in that, the mode that communication module stores CPU minimum system module to send data is as follows:步骤1：CPU通过IO口操作将1553B接口芯片的内存/寄存器引脚选择为内存引脚对应的电平；Step 1: The CPU selects the memory/register pin of the 1553B interface chip as the level corresponding to the memory pin through the IO port operation;步骤2：CPU通过总线写操作选择1553B接口芯片，将待写入内存的数据的低字节数据写入地址中；Step 2: The CPU selects the 1553B interface chip through the bus write operation, and writes the low-byte data of the data to be written into the memory into the address;步骤3：将所述步骤2中的地址左移1个二进制位，通过总线写操作选择1553B接口芯片，将待写入内存的数据的高字节数据写入左移后的地址中。Step 3: Shift the address in the step 2 to the left by 1 binary bit, select the 1553B interface chip through the bus write operation, and write the high-byte data of the data to be written into the memory into the left-shifted address.4.根据权利要求1所述的一种1553B接口芯片代替数据存储器的卫星电源下位机系统，其特征在于，CPU最小系统模块从通信模块中读取程序后续执行需要的数据的方式如下：4. a kind of 1553B interface chip according to claim 1 replaces the satellite power supply lower computer system of data memory, it is characterized in that, the mode that CPU minimum system module reads the data required for subsequent execution of program from communication module is as follows:步骤1：CPU通过IO口操作将1553B接口芯片的内存/寄存器引脚选择为内存引脚对应的电平；Step 1: The CPU selects the memory/register pin of the 1553B interface chip as the level corresponding to the memory pin through the IO port operation;步骤2：CPU通过总线读操作选择1553B接口芯片，将待读出1553B接口芯片内存的数据的低字节数据从对应地址读入CPU中，并将该数据丢弃，视作一次亚读操作；Step 2: The CPU selects the 1553B interface chip through the bus read operation, reads the low-byte data of the data to be read out of the memory of the 1553B interface chip into the CPU from the corresponding address, and discards the data as a sub-read operation;步骤3：CPU通过总线读操作选择1553B接口芯片，将待读出1553B接口芯片内存的数据的低字节数据再次从对应地址读入CPU中，并将该数据保存；Step 3: The CPU selects the 1553B interface chip through the bus read operation, reads the low-byte data of the data to be read out of the memory of the 1553B interface chip from the corresponding address into the CPU again, and saves the data;步骤4：将所述步骤3中的地址左移1个二进制位，通过总线读操作选择1553B接口芯片，将待读出1553B接口芯片内存的数据的高字节数据从对应地址读入CPU中，并将该数据保存。Step 4: Shift the address in the step 3 to the left by 1 binary bit, select the 1553B interface chip through the bus read operation, and read the high-byte data of the data in the memory of the 1553B interface chip to be read into the CPU from the corresponding address, and save the data.5.根据权利要求1所述的一种1553B接口芯片代替数据存储器的卫星电源下位机系统，其特征在于，CPU中存储的程序包括应用层、系统层和接口层；其中：5. a kind of 1553B interface chip according to claim 1 replaces the satellite power supply lower computer system of data memory, it is characterized in that, the program stored in CPU comprises application layer, system layer and interface layer; Wherein:应用层完成星上软件各具体功能；The application layer completes the specific functions of the on-board software;系统层完成CPU初始化、OC指令芯片初始化、电平指令芯片初始化、1553B接口芯片中断控制、定时中断控制、在轨上注代码校验与注入；The system layer completes CPU initialization, OC command chip initialization, level command chip initialization, 1553B interface chip interrupt control, timing interrupt control, on-track code verification and injection;接口层完成所有软件对外接口数据输入输出管理，包括1553B接口芯片接口初始化、1553B接口芯片数据输入输出管理、1553B接口芯片复位驱动管理、1553B接口芯片数据缓存存储、模数转换器驱动管理、OC指令驱动管理、电平指令驱动管理。The interface layer completes all software external interface data input and output management, including 1553B interface chip interface initialization, 1553B interface chip data input and output management, 1553B interface chip reset drive management, 1553B interface chip data cache storage, analog-to-digital converter drive management, OC instruction Drive management, level command drive management.6.根据权利要求1所述的一种1553B接口芯片代替数据存储器的卫星电源下位机系统，其特征在于，指令执行模块中，所述锁存器将数据总线中的数据转换为电平指令输出给电源控制器控制机构。6. a kind of 1553B interface chip according to claim 1 replaces the satellite power supply lower computer system of data memory, it is characterised in that in the instruction execution module, the latch converts the data in the data bus into a level command output to the power controller to control the mechanism.7.根据权利要求1所述的一种1553B接口芯片代替数据存储器的卫星电源下位机系统，其特征在于，指令执行模块中，所述译码器将控制信号转换为选择OC指令芯片的通道片选；所述OC指令芯片将通道片选转换为相应输出端口的OC指令输出给电源控制器控制机构。7. the satellite power supply lower computer system that a kind of 1553B interface chip according to claim 1 replaces data memory, it is characterized in that, in the instruction execution module, described decoder converts control signal into the channel slice that selects OC instruction chip The OC command chip converts the channel chip selection into the OC command of the corresponding output port and outputs it to the power controller control mechanism.8.根据权利要求1所述的一种1553B接口芯片代替数据存储器的卫星电源下位机系统，其特征在于，1553B接口芯片的容量同时满足约定程序的所有数据缓存需求和1553B数据通信缓存需求。8. the satellite power supply lower computer system that a kind of 1553B interface chip according to claim 1 replaces the data memory, it is characterized in that, the capacity of 1553B interface chip satisfies all data buffer requirements and 1553B data communication buffer requirements of the contract program simultaneously.

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