CN112909026A - Oxide thin film transistor array substrate and preparation method thereof - Google Patents

Abstract

The invention relates to the technical field of array substrates, in particular to an oxide thin film transistor array substrate and a preparation method thereof, and the oxide thin film transistor array substrate comprises a glass substrate and a buffer layer arranged on one side surface of the glass substrate, wherein at least one groove is formed in a capacitor area on one side surface of the buffer layer far away from the glass substrate, a first electrode layer is filled in the groove, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially laminated and covered on one side surface of the first electrode layer far away from the buffer layer, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor so as to form two capacitors, therefore, the capacitance capacity is further increased, the occupied area of the capacitor can be reduced, and the PPI panel and the frame size of the panel are improved.

Description

Oxide thin film transistor array substrate and preparation method thereof

Technical Field

The invention relates to the technical field of array substrates, in particular to an oxide thin film transistor array substrate and a preparation method thereof.

Background

With the development of active matrix organic light emitting diode displays (AMOLEDs) and high performance Active Matrix Liquid Crystal Displays (AMLCDs), in order to obtain high resolution and high frame rate displays, how to design and fabricate high performance and small size array substrate structures is an increasingly challenging research topic.

IGZO is an amorphous oxide containing indium, gallium and zinc, the carrier mobility is 20-30 times of that of amorphous silicon, the charge and discharge rate of a TFT (Thin Film Transistor, english is called a Thin Film Transistor) to a pixel electrode can be greatly increased, the response speed of a pixel is increased, the panel refresh rate is higher, and an ultrahigh-resolution display panel can be realized. Meanwhile, the existing amorphous silicon production line can be compatible with the IGZO process only by slightly changing, so that the cost is more competitive than that of low-temperature polycrystalline silicon (LTPS).

The oxide semiconductor mobility (10-30cm2/V.s) can meet the driving requirement of the AMOLED display array substrate, the IGZO TFT device has a better Ioff compared with a low-temperature polysilicon TFT, the pixel TFT can inhibit the electric leakage problem only by a single grid electrode, the miniaturization of the TFT device is facilitated, and the manufacturing of the ultra-high resolution TFT substrate is realized. Therefore, the high-resolution OLED display matched with the IGZO TFT drive circuit has good market prospect and is a research and development hotspot of main panel manufacturing factories at home and abroad at present.

The GOA technology (GOA: Gate Driver IC on Array) is a new type of panel development in recent years, which directly etches the IC driving the Gate signal on the panel, and saves the cost of the Gate Driver IC and the process of binding the IC on the panel, and more importantly, because the Gate Driver IC and the display panel are integrated, the product is thinner, the resolution is higher, and the stability and the vibration resistance are better. At present, the GOA technology has become the mainstream of the mobile terminal industry, and smart phones almost use the liquid crystal panel.

In order to make the driving circuit have a better voltage stabilizing effect in the array substrate, a capacitor with a larger capacity is usually required to be arranged, which causes the occupied area of the driving circuit to be larger, and the frame size and the pixel size of the display panel cannot be further reduced.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: an oxide thin film transistor array substrate capable of improving capacitance capacity and a method for manufacturing the same are provided.

In order to solve the above technical problems, a first technical solution adopted by the present invention is:

an oxide thin film transistor array substrate comprises a glass substrate and a buffer layer arranged on one side face of the glass substrate, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, a first electrode layer is filled in the groove, and a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially stacked and covered on one side face, far away from the buffer layer, of the first electrode layer;

a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer are sequentially laminated and covered on a TFT region on one side face, away from the glass substrate, of the buffer layer, a first through hole is formed in the second etching barrier layer, the second transparent conducting layer is filled in the first through hole, a second through hole is formed in the second transparent conducting layer, a third through hole is formed in the source drain electrode metal layer, the third through hole and the second through hole are oppositely arranged and communicated, and the second passivation layer is filled in the second through hole and the third through hole;

the material of the first electrode layer is the same as that of the first active layer;

the material of the second electrode layer is the same as that of the first transparent conducting layer;

the material of the third electrode layer is the same as that of the second transparent conducting layer.

The second technical scheme adopted by the invention is as follows:

a preparation method of an oxide thin film transistor array substrate comprises the following steps:

s1, providing a glass substrate, wherein the surface of the glass substrate is covered with a buffer layer; forming at least one groove in a capacitor area on one side surface of the buffer layer, which is far away from the glass substrate;

s2, forming a first electrode layer and a first active layer, wherein the first electrode layer is filled in the groove, and the first active layer covers the TFT area on one side face, far away from the glass substrate, of the buffer layer;

s3, forming a first insulating layer and a grid insulating layer, wherein the first insulating layer covers the surface of the first electrode layer, and the grid insulating layer covers the surface of the first active layer;

s4, forming a second electrode layer and a first transparent conducting layer, wherein the second electrode layer covers the surface of the first insulating layer, and the first transparent conducting layer covers the surface of the gate insulating layer;

s5, forming a grid metal layer and covering the surface of the first transparent conductive layer;

s6, forming a first etching barrier layer and a second etching barrier layer, wherein the first etching barrier layer covers the surface of the second electrode layer, and the second etching barrier layer covers the surface of the gate metal layer; forming a first via hole in the second etch-barrier layer;

s7, forming a third electrode layer and a second transparent conducting layer, wherein the third electrode layer covers the surface of the first etching barrier layer, and the second transparent conducting layer covers the surface of the second etching barrier layer; a second transparent conducting layer is filled in the first via hole; forming a second via hole in the second transparent conductive layer;

s8, forming a source drain metal layer, wherein the source drain metal layer covers the surface of the second transparent conducting layer; forming a third via hole in the source drain metal layer, wherein the third via hole is opposite to and communicated with the second via hole;

and S9, forming a first passivation layer and a second passivation layer, wherein the first passivation layer covers the surface of the third electrode layer, the second passivation layer covers the surface of the source drain electrode metal layer, and the second passivation layer is filled in the second through hole and the third through hole.

The invention has the beneficial effects that:

the capacitor comprises a buffer layer, a glass substrate, a capacitor body and a first electrode layer, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially overlapped on one side face, far away from the buffer layer, of the first electrode layer, the second electrode layer, the third electrode layer and the first passivation layer are respectively used as electrode layers of the capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor; the TFT region on one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the first active layer, the material of the second electrode layer is the same as that of the first transparent conducting layer, and the material of the third electrode layer is the same as that of the second transparent conducting layer, so that the capacitance can be further improved, the occupied area of a capacitor can be reduced, and the TFT LCD panel has the advantages of improving PPI (Pixels on diagonal lines of every Inch) of a panel and reducing the size of a panel frame.

Drawings

Fig. 1 is a schematic structural view of an oxide thin film transistor array substrate according to the present invention;

FIG. 2 is a flowchart illustrating a method for fabricating an oxide thin film transistor array substrate according to the present invention;

description of reference numerals:

1. a glass substrate;

2. a buffer layer;

3. a capacitive region; 31. a first electrode layer; 32. a first insulating layer; 33. a second electrode layer; 34. a first etch stop layer; 35. a third electrode layer; 36. a first passivation layer;

4. a TFT region; 41. a first active layer; 42. a gate insulating layer; 43. a first transparent conductive layer; 44. a gate metal layer; 45. a second etch stop layer; 46. a second transparent conductive layer; 47. a source drain metal layer; 48. a second passivation layer.

Detailed Description

In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

Referring to fig. 1, a technical solution provided by the present invention:

an oxide thin film transistor array substrate comprises a glass substrate and a buffer layer arranged on one side face of the glass substrate, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, a first electrode layer is filled in the groove, and a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially stacked and covered on one side face, far away from the buffer layer, of the first electrode layer;

a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer are sequentially laminated and covered on a TFT region on one side face, away from the glass substrate, of the buffer layer, a first through hole is formed in the second etching barrier layer, the second transparent conducting layer is filled in the first through hole, a second through hole is formed in the second transparent conducting layer, a third through hole is formed in the source drain electrode metal layer, the third through hole and the second through hole are oppositely arranged and communicated, and the second passivation layer is filled in the second through hole and the third through hole;

the material of the first electrode layer is the same as that of the first active layer;

the material of the second electrode layer is the same as that of the first transparent conducting layer;

the material of the third electrode layer is the same as that of the second transparent conducting layer.

From the above description, the beneficial effects of the present invention are:

the capacitor comprises a buffer layer, a glass substrate, a capacitor body and a first electrode layer, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially overlapped on one side face, far away from the buffer layer, of the first electrode layer, the second electrode layer, the third electrode layer and the first passivation layer are respectively used as electrode layers of the capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor; the TFT area of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the first active layer, the material of the second electrode layer is the same as that of the first transparent conducting layer, and the material of the third electrode layer is the same as that of the second transparent conducting layer, so that the capacitance capacity can be further improved, meanwhile, the occupied area of the capacitor can be reduced, and the PPI of the panel is improved, and the frame size of the panel is reduced.

Furthermore, the first electrode layer is made of indium tin oxide, and the thickness range of the first electrode layer is

As can be seen from the above description, the first electrode layer is made of ITO and has a thickness in the range of

The capacitance capacity can be further improved.

Further, the first electrode layer in the groove is in contact with the glass substrate.

Further, the vertical cross section of the groove is square.

Furthermore, the number of the first via holes is two, and the second via hole and the third via hole are both located between the two first via holes.

Referring to fig. 2, another technical solution provided by the present invention:

a preparation method of an oxide thin film transistor array substrate comprises the following steps:

s1, providing a glass substrate, wherein the surface of the glass substrate is covered with a buffer layer; forming at least one groove in a capacitor area on one side surface of the buffer layer, which is far away from the glass substrate;

s2, forming a first electrode layer and a first active layer, wherein the first electrode layer is filled in the groove, and the first active layer covers the TFT area on one side face, far away from the glass substrate, of the buffer layer;

s3, forming a first insulating layer and a grid insulating layer, wherein the first insulating layer covers the surface of the first electrode layer, and the grid insulating layer covers the surface of the first active layer;

s4, forming a second electrode layer and a first transparent conducting layer, wherein the second electrode layer covers the surface of the first insulating layer, and the first transparent conducting layer covers the surface of the gate insulating layer;

s5, forming a grid metal layer and covering the surface of the first transparent conductive layer;

s6, forming a first etching barrier layer and a second etching barrier layer, wherein the first etching barrier layer covers the surface of the second electrode layer, and the second etching barrier layer covers the surface of the gate metal layer; forming a first via hole in the second etch-barrier layer;

s7, forming a third electrode layer and a second transparent conducting layer, wherein the third electrode layer covers the surface of the first etching barrier layer, and the second transparent conducting layer covers the surface of the second etching barrier layer; a second transparent conducting layer is filled in the first via hole; forming a second via hole in the second transparent conductive layer;

s8, forming a source drain metal layer, wherein the source drain metal layer covers the surface of the second transparent conducting layer; forming a third via hole in the source drain metal layer, wherein the third via hole is opposite to and communicated with the second via hole;

and S9, forming a first passivation layer and a second passivation layer, wherein the first passivation layer covers the surface of the third electrode layer, the second passivation layer covers the surface of the source drain electrode metal layer, and the second passivation layer is filled in the second through hole and the third through hole.

From the above description, the beneficial effects of the present invention are:

the capacitor comprises a buffer layer, a glass substrate, a capacitor body and a first electrode layer, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially overlapped on one side face, far away from the buffer layer, of the first electrode layer, the second electrode layer, the third electrode layer and the first passivation layer are respectively used as electrode layers of the capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor; the TFT area of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the first active layer, the material of the second electrode layer is the same as that of the first transparent conducting layer, and the material of the third electrode layer is the same as that of the second transparent conducting layer, so that the capacitance capacity can be further improved, meanwhile, the occupied area of the capacitor can be reduced, and the PPI of the panel is improved, and the frame size of the panel is reduced.

Furthermore, the first electrode layer is made of indium tin oxide, and the thickness range of the first electrode layer is

As can be seen from the above description, the first electrode layer is made of ITO and has a thickness in the range of

The capacitance capacity can be further improved.

Further, the first electrode layer in the groove is in contact with the glass substrate.

Further, the vertical cross section of the groove is square.

Furthermore, the number of the first via holes is two, and the second via hole and the third via hole are both located between the two first via holes.

Referring to fig. 1, a first embodiment of the present invention is:

an oxide thin film transistor array substrate comprises a glass substrate 1 and abuffer layer 2 arranged on one side face of the glass substrate 1, wherein at least one groove is formed in a capacitor area 3 on one side face, far away from the glass substrate 1, of thebuffer layer 2, afirst electrode layer 31 is filled in the groove, and a first insulatinglayer 32, asecond electrode layer 33, a firstetching barrier layer 34, athird electrode layer 35 and afirst passivation layer 36 are sequentially stacked and covered on one side face, far away from thebuffer layer 2, of thefirst electrode layer 31;

a firstactive layer 41, agate insulating layer 42, a firsttransparent conducting layer 43, agate metal layer 44, a secondetching barrier layer 45, a secondtransparent conducting layer 46, a sourcedrain metal layer 47 and asecond passivation layer 48 are sequentially laminated and covered on the TFT region 4 on one side surface of thebuffer layer 2, which is far away from the glass substrate 1, wherein a first through hole is formed in the secondetching barrier layer 45, the secondtransparent conducting layer 46 is filled in the first through hole, a second through hole is formed in the secondtransparent conducting layer 46, a third through hole is formed in the source drainmetal layer 47, the third through hole and the second through hole are oppositely arranged and communicated, and thesecond passivation layer 48 is filled in the second through hole and the third through hole;

the material of thefirst electrode layer 31 is the same as that of the firstactive layer 41; the thickness of the firstactive layer 41 is in the range of

Preferably, it is

The material of thesecond electrode layer 33 is the same as that of the first transparentconductive layer 43; the thickness range of the first transparentconductive layer 43 is

Preferably, it is

The material of thethird electrode layer 35 is the same as that of the second transparentconductive layer 46; the second transparentconductive layer 46 has a thickness in the range of

Preferably, it is

The thickness range of thefirst electrode layer 31 is

Preferably, it is

Thefirst electrode layer 31 is made of indium tin oxide, and the thickness of thefirst electrode layer 31 is within a range

Thefirst electrode layer 31 in the recess is in contact with the glass substrate 1.

The vertical cross-sectional shape of the groove is square or semi-cylindrical.

The number of the first via holes is two, and the second via holes and the third via holes are located between the two first via holes.

The thickness range of thebuffer layer 2 is 0.2-3 μm, preferably 2 μm; thebuffer layer 2 can be made of organic photosensitive materials, PI, SiOx, SiNx, titanium oxide and the like;

the thickness of thegate metal layer 44 is in the range of

Preferably, it is

Thegate metal layer 44 may be made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with good conductivity, and alloys;

the thickness of the first insulatinglayer 32 is in the range of

Preferably, it is

Thegate insulating layer 42 has a thickness in the range of

Preferably, it is

The first insulatinglayer 32 and thegate insulating layer 42 are made of the same material, and may be made of SiOx, SiNx, titanium oxide, aluminum oxide, or the like;

the thickness range of thesecond electrode layer 33 is

Preferably, it is

Thesecond electrode layer 33 and the first transparentconductive layer 43 are made of the same material, and may be made of metal oxide such as IGZO, IZO, IGZTO, etc.;

the thickness range of thethird electrode layer 35 is

Preferably, it is

Thethird electrode layer 35 and the second transparentconductive layer 46 are made of the same material, and indium tin oxide can be used;

the thickness of the firstetch stop layer 34 ranges from

Preferably, it is

The thickness of the secondetch stop layer 45 ranges from

Preferably, it is

The firstetching barrier layer 34 and the secondetching barrier layer 45 are made of the same material, and may be selected from SiOx, SiNx, titanium oxide, aluminum oxide, and the like;

the thickness range of the source/drain metal layer 47 is

Preferably, it is

The source/drain metal layer 47 may be made of one or more metals with good conductivity, such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and alloys;

the thickness of thefirst passivation layer 36 ranges from

Preferably, it is

The thickness of thesecond passivation layer 48 ranges from

Preferably, it is

Thefirst passivation layer 36 and thesecond passivation layer 48 are made of the same material, and may be made of SiOx, SiNx, titanium oxide, aluminum oxide, or the like;

the second transparentconductive layer 46 is made of indium tin oxide, and the source layer and the source drainmetal layer 47 are connected in a bridging manner by using the indium tin oxide, so that ohmic contact resistance can be reduced, and the electrical performance of the TFT can be improved;

in the actual process, thefirst electrode layer 31 and the firstactive layer 41 are the same film layer distributed in different regions, and are formed simultaneously during the evaporation process;

the first insulatinglayer 32 and thegate insulating layer 42 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;

thesecond electrode layer 33 and the first transparentconductive layer 43 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;

the firstetching barrier layer 34 and the secondetching barrier layer 45 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;

thethird electrode layer 35 and the second transparentconductive layer 46 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;

thefirst passivation layer 36 and thesecond passivation layer 48 are the same film layer distributed in different regions, and are formed simultaneously during the evaporation process;

according to the array substrate with the high-capacity capacitor structure, under the condition that the capacity is kept equal, the actually occupied area of the three-dimensional grid-shaped capacitor is smaller than that of a flat capacitor, and the theoretical capacitor area can be further reduced by 50%.

Referring to fig. 2, the second embodiment of the present invention is:

a preparation method of an oxide thin film transistor array substrate comprises the following steps:

s1, providing a glass substrate 1, and covering abuffer layer 2 on the surface of the glass substrate 1; at least one groove is formed in a capacitor area 3 on one side surface of thebuffer layer 2 away from the glass substrate 1;

s2, forming afirst electrode layer 31 and a firstactive layer 41, wherein thefirst electrode layer 31 is filled in the groove, and the firstactive layer 41 covers the TFT area 4 on one side surface of thebuffer layer 2, which is far away from the glass substrate 1;

s3, forming a first insulatinglayer 32 and agate insulating layer 42, wherein the first insulatinglayer 32 covers the surface of thefirst electrode layer 31, and thegate insulating layer 42 covers the surface of the firstactive layer 41;

s4, forming asecond electrode layer 33 and a firsttransparent conducting layer 43, wherein thesecond electrode layer 33 covers the surface of the first insulatinglayer 32, and the firsttransparent conducting layer 43 covers the surface of thegate insulating layer 42;

s5, forming agate metal layer 44 covering the surface of the first transparentconductive layer 43;

s6, forming a firstetching barrier layer 34 and a secondetching barrier layer 45, wherein the firstetching barrier layer 34 covers the surface of thesecond electrode layer 33, and the secondetching barrier layer 45 covers the surface of thegate metal layer 44; forming a first via hole in the secondetch stopper layer 45;

s7, forming athird electrode layer 35 and a secondtransparent conducting layer 46, wherein thethird electrode layer 35 covers the surface of the firstetching barrier layer 34, and the secondtransparent conducting layer 46 covers the surface of the secondetching barrier layer 45; the first via hole is filled with a second transparentconductive layer 46; forming a second via in the second transparentconductive layer 46;

s8, forming a sourcedrain metal layer 47, wherein the source drainmetal layer 47 covers the surface of the secondtransparent conducting layer 46; forming a third via hole in the source-drain metal layer 47, wherein the third via hole is opposite to and communicated with the second via hole;

and S9, forming afirst passivation layer 36 and asecond passivation layer 48, wherein thefirst passivation layer 36 covers the surface of thethird electrode layer 35, thesecond passivation layer 48 covers the surface of the source and drainmetal layer 47, and the second and third via holes are filled with thesecond passivation layer 48.

Thefirst electrode layer 31 is made of indium tin oxide, and the thickness of thefirst electrode layer 31 is within a range

Preferably, it is

Thefirst electrode layer 31 in the recess is in contact with the glass substrate 1.

The vertical cross-sectional shape of the groove is square or semi-cylindrical.

The number of the first via holes is two, and the second via holes and the third via holes are located between the two first via holes.

In summary, according to the oxide thin film transistor array substrate and the preparation method thereof provided by the present invention, at least one groove is formed in a capacitor region on one side surface of the buffer layer away from the glass substrate, the groove is filled with the first electrode layer, the first insulating layer, the second electrode layer, the first etching barrier layer, the third electrode layer and the first passivation layer are sequentially stacked and covered on one side surface of the first electrode layer away from the buffer layer, the first electrode layer, the second electrode layer, the first etching barrier layer and the third electrode layer are respectively used as electrode layers of a capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor, so as to form two capacitors connected in parallel, thereby further increasing the capacitance capacity; the TFT area of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the first active layer, the material of the second electrode layer is the same as that of the first transparent conducting layer, and the material of the third electrode layer is the same as that of the second transparent conducting layer, so that the capacitance capacity can be further improved, meanwhile, the occupied area of the capacitor can be reduced, and the PPI of the panel is improved, and the frame size of the panel is reduced.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.

Claims (10)

Translated fromChinese

1.一种氧化物薄膜晶体管阵列基板，其特征在于，包括玻璃基板和设置在玻璃基板一侧面的缓冲层，所述缓冲层远离玻璃基板的一侧面的电容区域开设有至少一个的凹槽，所述凹槽中填充有第一电极层，所述第一电极层远离缓冲层的一侧面上依次层叠覆盖有第一绝缘层、第二电极层、第一蚀刻阻挡层、第三电极层和第一钝化层；1. An oxide thin film transistor array substrate, characterized in that it comprises a glass substrate and a buffer layer arranged on one side of the glass substrate, wherein the buffer layer is provided with at least one groove in the capacitor region of one side away from the glass substrate, The groove is filled with a first electrode layer, and one side of the first electrode layer away from the buffer layer is sequentially stacked and covered with a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and the first passivation layer;所述缓冲层远离玻璃基板的一侧面的TFT区域上依次层叠覆盖有第一有源层、栅极绝缘层、第一透明导电层、栅极金属层、第二蚀刻阻挡层、第二透明导电层、源漏极金属层和第二钝化层，所述第二蚀刻阻挡层上开设有第一过孔，所述第一过孔中均填充有第二透明导电层，所述第二透明导电层上开设有第二过孔，所述源漏极金属层上开设有第三过孔，所述第三过孔与第二过孔相对设置且相通，所述第二过孔和第三过孔中均填充有第二钝化层；A first active layer, a gate insulating layer, a first transparent conductive layer, a gate metal layer, a second etching barrier layer, and a second transparent conductive layer are stacked and covered in sequence on the TFT region on the side of the buffer layer away from the glass substrate. layer, a source-drain metal layer and a second passivation layer, the second etching barrier layer is provided with a first via hole, the first via hole is filled with a second transparent conductive layer, the second transparent conductive layer is The conductive layer is provided with a second via hole, the source-drain metal layer is provided with a third via hole, the third via hole is opposite to and communicated with the second via hole, and the second via hole and the third via hole are arranged oppositely. The via holes are filled with a second passivation layer;所述第一电极层的材质与第一有源层的材质相同；The material of the first electrode layer is the same as the material of the first active layer;所述第二电极层的材质与第一透明导电层的材质相同；The material of the second electrode layer is the same as the material of the first transparent conductive layer;所述第三电极层的材质与第二透明导电层的材质相同。The material of the third electrode layer is the same as that of the second transparent conductive layer.2.根据权利要求1所述的氧化物薄膜晶体管阵列基板，其特征在于，所述第一电极层的材质为氧化铟锡，所述第一电极层的厚度范围为

2 . The oxide thin film transistor array substrate according to claim 1 , wherein the material of the first electrode layer is indium tin oxide, and the thickness of the first electrode layer ranges from

3.根据权利要求1所述的氧化物薄膜晶体管阵列基板，其特征在于，所述凹槽中的第一电极层与玻璃基板接触。3 . The oxide thin film transistor array substrate according to claim 1 , wherein the first electrode layer in the groove is in contact with the glass substrate. 4 .4.根据权利要求1所述的氧化物薄膜晶体管阵列基板，其特征在于，所述凹槽的竖直截面形状为方形。4 . The oxide thin film transistor array substrate according to claim 1 , wherein the vertical cross-sectional shape of the groove is square. 5 .5.根据权利要求1所述的氧化物薄膜晶体管阵列基板，其特征在于，所述第一过孔的数量为两个，所述第二过孔和第三过孔均位于两个第一过孔之间。5 . The oxide thin film transistor array substrate according to claim 1 , wherein the number of the first via holes is two, and both the second via hole and the third via hole are located in the two first via holes. 6 . between the holes.6.一种权利要求1所述的氧化物薄膜晶体管阵列基板的制备方法，其特征在于，包括以下步骤：6. A method for preparing an oxide thin film transistor array substrate according to claim 1, characterized in that it comprises the following steps:S1、提供一玻璃基板，在所述玻璃基板表面覆盖有缓冲层；在所述缓冲层远离玻璃基板的一侧面的电容区域形成至少一个的凹槽；S1. Provide a glass substrate, and the surface of the glass substrate is covered with a buffer layer; at least one groove is formed in the capacitor region on one side of the buffer layer away from the glass substrate;S2、形成第一电极层和第一有源层，所述第一电极层填充于凹槽内，所述第一有源层覆盖于缓冲层远离玻璃基板的一侧面的TFT区域上；S2, forming a first electrode layer and a first active layer, the first electrode layer is filled in the groove, and the first active layer covers the TFT area on the side of the buffer layer away from the glass substrate;S3、形成第一绝缘层和栅极绝缘层，所述第一绝缘层覆盖于第一电极层表面，所述栅极绝缘层覆盖于第一有源层表面；S3, forming a first insulating layer and a gate insulating layer, the first insulating layer covers the surface of the first electrode layer, and the gate insulating layer covers the surface of the first active layer;S4、形成第二电极层和第一透明导电层，所述第二电极层覆盖于第一绝缘层表面，所述第一透明导电层覆盖于栅极绝缘层表面；S4, forming a second electrode layer and a first transparent conductive layer, the second electrode layer covers the surface of the first insulating layer, and the first transparent conductive layer covers the surface of the gate insulating layer;S5、形成栅极金属层，且覆盖于第一透明导电层表面；S5, forming a gate metal layer and covering the surface of the first transparent conductive layer;S6、形成第一蚀刻阻挡层和第二蚀刻阻挡层，所述第一蚀刻阻挡层覆盖于第二电极层表面，所述第二蚀刻阻挡层覆盖于栅极金属层表面；在所述第二蚀刻阻挡层中形成第一过孔；S6, forming a first etching barrier layer and a second etching barrier layer, the first etching barrier layer covers the surface of the second electrode layer, and the second etching barrier layer covers the surface of the gate metal layer; forming a first via hole in the etching barrier layer;S7、形成第三电极层和第二透明导电层，所述第三电极层覆盖于第一蚀刻阻挡层表面，所述第二透明导电层覆盖于第二蚀刻阻挡层表面；所述第一过孔中填充有第二透明导电层；在所述第二透明导电层中形成第二过孔；S7, forming a third electrode layer and a second transparent conductive layer, the third electrode layer covers the surface of the first etching barrier layer, and the second transparent conductive layer covers the surface of the second etching barrier layer; The hole is filled with a second transparent conductive layer; a second via hole is formed in the second transparent conductive layer;S8、形成源漏极金属层，所述源漏极金属层覆盖于第二透明导电层表面；在源漏极金属层中形成第三过孔，所述第三过孔与第二过孔相对设置且相通；S8, forming a source-drain metal layer, the source-drain metal layer covering the surface of the second transparent conductive layer; forming a third via hole in the source-drain metal layer, the third via hole is opposite to the second via hole set and communicated;S9、形成第一钝化层和第二钝化层，所述第一钝化层覆盖于第三电极层表面，所述第二钝化层覆盖于源漏极金属层表面，且所述第二过孔和第三过孔中均填充有第二钝化层。S9, forming a first passivation layer and a second passivation layer, the first passivation layer covers the surface of the third electrode layer, the second passivation layer covers the surface of the source/drain metal layer, and the first passivation layer covers the surface of the source/drain metal layer. Both the second via hole and the third via hole are filled with a second passivation layer.7.根据权利要求1所述的氧化物薄膜晶体管阵列基板的制备方法，其特征在于，所述第一电极层的材质为氧化铟锡，所述第一电极层的厚度范围为

7 . The method for preparing an oxide thin film transistor array substrate according to claim 1 , wherein the material of the first electrode layer is indium tin oxide, and the thickness of the first electrode layer ranges from

8.根据权利要求1所述的氧化物薄膜晶体管阵列基板的制备方法，其特征在于，所述凹槽中的第一电极层与玻璃基板接触。8 . The method for preparing an oxide thin film transistor array substrate according to claim 1 , wherein the first electrode layer in the groove is in contact with the glass substrate. 9 .9.根据权利要求1所述的氧化物薄膜晶体管阵列基板的制备方法，其特征在于，所述凹槽的竖直截面形状为方形。9 . The method for manufacturing an oxide thin film transistor array substrate according to claim 1 , wherein the vertical cross-sectional shape of the groove is square. 10 .10.根据权利要求1所述的氧化物薄膜晶体管阵列基板的制备方法，其特征在于，所述第一过孔的数量为两个，所述第二过孔和第三过孔均位于两个第一过孔之间。10 . The method for manufacturing an oxide thin film transistor array substrate according to claim 1 , wherein the number of the first via holes is two, and the second via holes and the third via holes are located at two between the first vias.

Images