技术领域Technical field
本公开涉及半导体领域，具体地，涉及NOR型存储器件及其制造方法以及包括这种存储器件的电子设备。The present disclosure relates to the field of semiconductors, and in particular, to NOR type memory devices and manufacturing methods thereof, as well as electronic devices including such memory devices.
背景技术Background technique
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，水平型器件不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件更容易缩小。In a horizontal device such as a metal oxide semiconductor field effect transistor (MOSFET), the source, gate and drain are arranged in a direction generally parallel to the substrate surface. Due to this arrangement, horizontal devices cannot be easily shrunk further. In contrast, in a vertical device, the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical devices are easier to shrink than horizontal devices.
对于竖直型器件，可以通过彼此叠置来增加集成密度。但是，这可能会导致性能变差。因为为了方便叠置多个器件，通常使用多晶硅来作为沟道材料，导致与单晶硅的沟道材料相比电阻变大。另外，也期望能够单独调节源/漏区与沟道中的掺杂水平。For vertical devices, integration density can be increased by stacking them on top of each other. However, this may result in poor performance. Because in order to facilitate the stacking of multiple devices, polysilicon is usually used as the channel material, resulting in a greater resistance compared with the channel material of single crystal silicon. In addition, it is also desirable to be able to independently adjust the doping levels in the source/drain regions and the channel.
发明内容Contents of the invention
有鉴于此，本公开的目的至少部分地在于提供一种具有改进性能的NOR型存储器件及其制造方法以及包括这种存储器件的电子设备。In view of this, an object of the present disclosure is, at least in part, to provide a NOR type memory device with improved performance, a method of manufacturing the same, and an electronic device including such a memory device.
根据本公开的一个方面，提供了一种竖直型存储器件，包括：叠置在衬底上的多个器件层，其中，每个器件层包括在竖直方向上处于相对两端的第一源/漏区和第二源/漏区以及在竖直方向上处于第一源/漏区与第二源/漏区之间的沟道区；以及相对于衬底竖直延伸以穿过各个器件层的栅堆叠，栅堆叠包括栅导体层和设置在栅导体层与器件层之间的存储功能层，在栅堆叠与器件层相交之处限定存储单元，其中，第一源/漏区和第二源/漏区中的掺杂浓度在竖直方向上朝向沟道区减小。According to an aspect of the present disclosure, a vertical memory device is provided, including: a plurality of device layers stacked on a substrate, wherein each device layer includes first sources at opposite ends in a vertical direction. /drain region and the second source/drain region and a channel region vertically between the first source/drain region and the second source/drain region; and extending vertically relative to the substrate to pass through each device A gate stack of layers, the gate stack includes a gate conductor layer and a memory function layer disposed between the gate conductor layer and the device layer, a memory cell is defined at the intersection of the gate stack and the device layer, wherein the first source/drain region and the third The doping concentration in the two source/drain regions decreases in the vertical direction toward the channel region.
根据本公开的另一方面，提供了一种竖直型存储器件，包括：叠置在衬底上的多个器件层，其中，每个器件层包括在竖直方向上处于相对两端的第一源/漏区和第二源/漏区以及在竖直方向上处于第一源/漏区与第二源/漏区之间的沟道区；以及相对于衬底竖直延伸以穿过各个器件层的栅堆叠，栅堆叠包括栅导体层和设置在栅导体层与器件层之间的存储功能层，在栅堆叠与器件层相交之处限定存储单元，其中，NOR型存储器件还包括第一源/漏区与沟道区之间的界面层以及第二源/漏区与沟道区之间的界面层。According to another aspect of the present disclosure, a vertical memory device is provided, including: a plurality of device layers stacked on a substrate, wherein each device layer includes first devices at opposite ends in a vertical direction. The source/drain region and the second source/drain region and the channel region vertically between the first source/drain region and the second source/drain region; and extending vertically relative to the substrate to pass through each A gate stack of the device layer. The gate stack includes a gate conductor layer and a memory function layer disposed between the gate conductor layer and the device layer. A memory cell is defined at the intersection of the gate stack and the device layer, wherein the NOR type memory device also includes a third An interface layer between a source/drain region and the channel region and an interface layer between a second source/drain region and the channel region.
根据本公开的另一方面，提供了一种制造竖直型存储器件的方法，包括：在衬底上交替设置多个器件层和多个含掺杂剂的固相掺杂剂源层，使得每一器件层在竖直方向上介于固相掺杂剂源层之间；形成相对于衬底竖直延伸以穿过各个器件层的加工通道；通过退火将掺杂剂从固相掺杂剂源层驱入器件层的相对两端；以及在加工通道中形成栅堆叠，栅堆叠包括栅导体层和设置在栅导体层与器件层之间的存储功能层，在栅堆叠与器件层相交之处限定存储单元。According to another aspect of the present disclosure, a method of manufacturing a vertical memory device is provided, including: alternately arranging a plurality of device layers and a plurality of solid-phase dopant source layers containing dopants on a substrate, such that Each device layer is vertically interposed between solid phase dopant source layers; processing channels extending vertically relative to the substrate are formed through each device layer; dopants are doped from the solid phase by annealing driving the agent source layer into opposite ends of the device layer; and forming a gate stack in the processing channel, the gate stack including a gate conductor layer and a storage function layer disposed between the gate conductor layer and the device layer, where the gate stack intersects the device layer where to define the storage unit.
根据本公开的另一方面，提供了一种电子设备，包括上述NOR型存储器件。According to another aspect of the present disclosure, an electronic device is provided, including the above-mentioned NOR type memory device.
根据本公开的实施例，可以使用单晶材料的叠层作为构建模块，来建立三维(3D)NOR型存储器件。因此，在彼此叠置多个存储单元时，可以抑制电阻的增大。另外，可以利用固相掺杂剂源层通过扩散来进行源/漏掺杂，有助于形成陡峭的高源/漏掺杂。。According to embodiments of the present disclosure, three-dimensional (3D) NOR-type memory devices can be built using stacks of single crystal materials as building blocks. Therefore, when a plurality of memory cells are stacked on each other, an increase in resistance can be suppressed. Additionally, a solid phase dopant source layer can be used to perform source/drain doping via diffusion, helping to create steep, high source/drain doping. .
附图说明Description of drawings
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
图1至11(c)示出了根据本公开实施例的制造NOR型存储器件的流程中部分阶段的示意图；1 to 11(c) illustrate schematic diagrams of some stages in a process of manufacturing a NOR type memory device according to an embodiment of the present disclosure;
图12(a)和12(b)示出了根据本公开另一实施例的制造NOR型存储器件的流程中部分阶段的示意图；12(a) and 12(b) illustrate a schematic diagram of some stages in a process of manufacturing a NOR type memory device according to another embodiment of the present disclosure;
图13示出了根据本公开另一实施例的制造NOR型存储器件的流程中部分阶段的示意图；Figure 13 shows a schematic diagram of some stages in a process of manufacturing a NOR type memory device according to another embodiment of the present disclosure;
图14示出了根据本公开另一实施例的制造NOR型存储器件的流程中部分阶段的示意图；14 shows a schematic diagram of some stages in a process of manufacturing a NOR type memory device according to another embodiment of the present disclosure;
图15示出了根据本公开实施例的制造NOR型存储器件的流程中部分阶段的示意图；Figure 15 shows a schematic diagram of some stages in a process of manufacturing a NOR type memory device according to an embodiment of the present disclosure;
图16至19示出了根据本公开实施例的制造NOR型存储器件的流程中部分阶段的示意图；16 to 19 illustrate schematic diagrams of some stages in a process of manufacturing a NOR type memory device according to embodiments of the present disclosure;
图20示意性示出了根据本公开实施例的NOR型存储器件的等效电路图，20 schematically shows an equivalent circuit diagram of a NOR type memory device according to an embodiment of the present disclosure,
其中，图2(a)、7(a)、11(a)、12(a)是俯视图，图2(a)中示出了AA′线、BB′线的位置，Among them, Figures 2(a), 7(a), 11(a), and 12(a) are top views, and Figure 2(a) shows the positions of line AA′ and line BB′,
图1、2(b)、3至6、7(b)、8(a)、9(a)、10(a)、11(b)、12(b)、16至19是沿AA′线的截面图，Figures 1, 2(b), 3 to 6, 7(b), 8(a), 9(a), 10(a), 11(b), 12(b), 16 to 19 are along line AA′ cross-sectional view,
图7(c)、8(b)、9(b)、10(b)、11(c)、13至15是沿BB′线的截面图。Figures 7(c), 8(b), 9(b), 10(b), 11(c), and 13 to 15 are cross-sectional views along line BB'.
贯穿附图，相同或相似的附图标记表示相同或相似的部件。Throughout the drawings, the same or similar reference numbers refer to the same or similar parts.
具体实施方式Detailed ways
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily confusing the concepts of the present disclosure.
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The drawings are not drawn to scale, with certain details exaggerated and may have been omitted for purposes of clarity. The shapes of the various regions and layers shown in the figures, as well as the relative sizes and positional relationships between them are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art will base their judgment on actual situations. Additional regions/layers with different shapes, sizes, and relative positions can be designed as needed.
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present between them. element. Additionally, if one layer/element is "on" another layer/element in one orientation, then the layer/element can be "under" the other layer/element when the orientation is reversed.
根据本公开实施例的存储器件基于竖直型器件。竖直型器件可以包括在衬底上沿竖直方向(大致垂直于衬底表面的方向)设置的有源区，包括设于上下两端的源/漏区以及位于源/漏区之间的沟道区。源/漏区之间可以通过沟道区形成导电通道。在有源区中，源/漏区和沟道区例如可以通过掺杂浓度来限定。The memory device according to the embodiment of the present disclosure is based on a vertical type device. The vertical device may include an active region arranged in a vertical direction on the substrate (a direction roughly perpendicular to the surface of the substrate), including source/drain regions located at the upper and lower ends and a trench between the source/drain regions. Road area. A conductive channel can be formed between the source/drain regions through the channel region. In the active region, the source/drain regions and the channel region may be defined by doping concentration, for example.
根据本公开的实施例，有源区可以通过衬底上的器件层来限定。例如，器件层可以是半导体材料的叠层，源/漏区可以分别形成在该叠层在竖直方向上的相对两端，而沟道区可以形成在该叠层在竖直方向上的中部。或者，可以在该叠层(也可称为“基体层”)的侧壁上生长另外的半导体层，源/漏区可以分别形成在半导体层在竖直方向上的相对两端，而沟道区可以形成在半导体层在竖直方向上的中部。栅堆叠可以延伸穿过器件层，从而有源区可以围绕栅堆叠的外周。在此，栅堆叠可以包括存储功能层如电荷捕获材料或铁电材料中至少之一，以便实现存储功能。这样，栅堆叠同与之相对的有源区相配合而限定存储单元。在此，存储单元可以是闪存(flash)单元。According to embodiments of the present disclosure, the active area may be defined by a device layer on the substrate. For example, the device layer may be a stack of semiconductor materials, the source/drain regions may be formed at opposite ends of the stack in the vertical direction, and the channel region may be formed in the middle of the stack in the vertical direction. . Alternatively, another semiconductor layer can be grown on the sidewalls of the stack (also referred to as the "base layer"), the source/drain regions can be formed at opposite ends of the semiconductor layer in the vertical direction, and the channel The region may be formed in the middle of the semiconductor layer in the vertical direction. The gate stack may extend through the device layer such that the active region may surround the periphery of the gate stack. Here, the gate stack may include at least one of a storage function layer such as a charge trapping material or a ferroelectric material to implement a storage function. In this way, the gate stack cooperates with the opposing active region to define the memory cell. Here, the storage unit may be a flash memory unit.
可以设置多个栅堆叠以穿过器件层，从而在这多个栅堆叠与器件层相交之处限定多个存储单元。这些存储单元在器件层所在的平面内排列成与该多个栅堆叠相对应的阵列(例如，通常是按行和列排列的二维阵列)。A plurality of gate stacks may be disposed through the device layer to define a plurality of memory cells where the plurality of gate stacks intersect the device layer. The memory cells are arranged in an array corresponding to the plurality of gate stacks in the plane of the device layer (eg, typically a two-dimensional array arranged in rows and columns).
由于竖直型器件易于叠置的特性，根据本公开实施例的存储器件可以是三维(3D)阵列。具体地，可以在竖直方向上设置多个这样的器件层。栅堆叠可以竖直延伸，从而穿过这多个器件层。这样，对于单个栅堆叠而言，与竖直方向上叠置的这多个器件层相交而限定在竖直方向上叠置的多个存储单元。Due to the ease of stacking of vertical devices, memory devices according to embodiments of the present disclosure may be three-dimensional (3D) arrays. Specifically, a plurality of such device layers may be arranged in the vertical direction. The gate stack can extend vertically through the multiple device layers. In this way, for a single gate stack, the intersection with the plurality of vertically stacked device layers defines a plurality of vertically stacked memory cells.
在NOR(“或非”)型存储器件中，各存储单元可以连接到公共的源极线。鉴于这种配置，为节省布线，在竖直方向上，两个相邻的存储单元可以共用相同的源极线连接。例如，对于这两个相邻的存储单元，它们各自处于近端(即，这两个存储单元彼此靠近的一端)的源/漏区可以作为源区，并因此例如通过公共的接触部而电连接到源极线；它们各自处于远端(即，这两个存储单元彼此远离的一端)的源/漏区可以作为漏区，并可以分别连接到不同的位线。In NOR (not-or) type memory devices, each memory cell can be connected to a common source line. Given this configuration, to save wiring, two adjacent memory cells in the vertical direction can share the same source line connection. For example, for these two adjacent memory cells, their respective source/drain regions at the proximal end (ie, the end where the two memory cells are close to each other) can serve as the source region, and thus are electrically connected, for example, through a common contact. Connected to the source line; their respective source/drain regions at the far end (ie, the end of the two memory cells away from each other) can serve as drain regions and can be connected to different bit lines respectively.
器件层可以通过外延生长而形成，并可以为单晶半导体材料。与形成彼此叠置的多个栅堆叠，再形成穿过这些栅堆叠的竖直有源区的常规工艺相比，更容易形成单晶的有源区(特别是沟道区)。The device layer may be formed by epitaxial growth and may be a single crystal semiconductor material. Compared with the conventional process of forming multiple gate stacks stacked on top of each other and then forming vertical active regions passing through these gate stacks, it is easier to form a single-crystal active region (especially a channel region).
器件层在生长时可以被原位掺杂，并可以限定沟道区中的掺杂特性。另外，源/漏区的掺杂可以通过扩散形成。例如，可以在各器件层的相对两端设置固相掺杂剂源层(也用作存储单元之间的隔离层)，并将固相掺杂剂源层中的掺杂剂驱入器件层(例如，上述叠层或在叠层的侧壁上生长的半导体层)中，以形成源/漏区。于是，可以单独调节源/漏区、沟道区的掺杂分布，并可以形成陡峭的高源/漏掺杂。Device layers can be doped in situ as they are grown, and the doping characteristics in the channel region can be defined. In addition, the doping of the source/drain regions can be formed by diffusion. For example, a solid-phase dopant source layer (also used as an isolation layer between memory cells) can be provided at opposite ends of each device layer, and the dopants in the solid-phase dopant source layer can be driven into the device layer (for example, the above-described stack or a semiconductor layer grown on the sidewalls of the stack) to form source/drain regions. Therefore, the doping distribution of the source/drain region and the channel region can be adjusted independently, and steep high source/drain doping can be formed.
在源/漏区和沟道区形成于上述叠层中的情况下，该叠层可以看作体(bulk)材料，且因此沟道区形成在体材料中。这种情况下，工艺较为简单。另外，在沟道区形成于半导体层的情况下，该半导体层可以形成为纳米片或纳米线，且因此沟道区形成在纳米片或纳米线中(存储单元成为纳米片或纳米线器件)。这种情况下，可以实现良好的短沟道效应控制。另外，如下所述，在该半导体层中，还可以形成超陡后退阱(Super Steep RetrogradedWell，SSRW)，这有助于控制短沟道效应。In the case where the source/drain regions and the channel region are formed in the above-mentioned stack, the stack can be regarded as a bulk material, and therefore the channel region is formed in the bulk material. In this case, the process is relatively simple. In addition, in the case where the channel region is formed in the semiconductor layer, the semiconductor layer may be formed as a nanosheet or nanowire, and therefore the channel region is formed in the nanosheet or nanowire (the memory cell becomes a nanosheet or nanowire device) . In this case, good short channel effect control can be achieved. In addition, as described below, a Super Steep Retrograded Well (SSRW) can also be formed in the semiconductor layer, which helps to control the short channel effect.
这种竖直型存储器件例如可以如下制造。具体地，可以在衬底上交替设置多个器件层和多个含掺杂剂的固相掺杂剂源层，使得每一器件层在竖直方向上介于固相掺杂剂源层之间。器件层可以通过外延生长来提供。在外延生长时，固相掺杂剂源的位置可以由牺牲层限定，且牺牲层随后可以替换为固相掺杂剂源层。另外，在外延生长时，可以进行原位掺杂，以实现所需的掺杂极性和掺杂浓度。Such a vertical memory device can be manufactured as follows, for example. Specifically, a plurality of device layers and a plurality of solid-phase dopant source layers containing dopants may be alternately disposed on the substrate, such that each device layer is vertically interposed between the solid-phase dopant source layers. between. Device layers can be provided by epitaxial growth. During epitaxial growth, the location of the solid phase dopant source may be defined by a sacrificial layer, and the sacrificial layer may subsequently be replaced with a solid phase dopant source layer. In addition, during epitaxial growth, in-situ doping can be performed to achieve the required doping polarity and doping concentration.
可以形成相对于衬底竖直延伸以穿过各个器件层的加工通道。在加工通道中，可以露出牺牲层的侧壁，从而可以将之替换为固相掺杂剂源层。在加工通道中，可以形成栅堆叠。另外，可以通过退火，将掺杂剂从隔离层驱入器件层的相对两端，以形成源/漏区。可以将固相掺杂剂源层替换为隔离层。Processing channels may be formed extending vertically relative to the substrate to pass through various device layers. In the processing channel, the sidewalls of the sacrificial layer can be exposed so that they can be replaced with a solid phase dopant source layer. In the processing channel, a gate stack can be formed. Additionally, dopants can be driven from the isolation layer into opposite ends of the device layer through annealing to form source/drain regions. The solid phase dopant source layer can be replaced by an isolation layer.
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离，导电材料用于形成电极、互连结构等)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。The disclosure may be presented in various forms, some examples of which are described below. In the following description, various material selections are addressed. In addition to considering their functions (for example, semiconductor materials are used to form active areas, dielectric materials are used to form electrical isolation, conductive materials are used to form electrodes, interconnect structures, etc.), the selection of materials also considers etching selectivity. In the following description, the required etch selectivity may or may not be indicated. It should be clear to those skilled in the art that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then this etching Can be selective, and the layer of material can be etching selective relative to other layers exposed to the same etching recipe.
图1至11(c)示出了根据本公开实施例的制造NOR型存储器件的流程中部分阶段的示意图。1 to 11(c) illustrate schematic diagrams of some stages in a process of manufacturing a NOR type memory device according to an embodiment of the present disclosure.
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底如Si晶片为例进行描述。As shown in Figure 1, a substrate 1001 is provided. The substrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like. In the following description, for convenience of explanation, a bulk Si substrate such as a Si wafer is taken as an example.
在衬底1001上，可以如下所述形成存储器件，例如NOR型闪存(flash)。存储器件中的存储单元(cell)可以是n型器件或p型器件。在此，以n型存储单元为例进行描述，为此衬底1001中可以形成有p型阱。因此，以下的描述，特别是关于掺杂类型的描述，针对n型器件的形成。但是，本公开不限于此。On the substrate 1001, a memory device, such as a NOR type flash memory, may be formed as follows. The memory cells (cells) in the memory device can be n-type devices or p-type devices. Here, an n-type memory cell is taken as an example for description. For this purpose, a p-type well may be formed in the substrate 1001. Therefore, the following description, particularly with respect to doping types, is directed to the formation of n-type devices. However, the present disclosure is not limited thereto.
在衬底1001上，可以通过例如外延生长，形成用于限定隔离层的牺牲层10031以及用于限定存储单元的有源区的器件层10051。On the substrate 1001, a sacrificial layer 10031 for defining an isolation layer and a device layer 10051 for defining an active region of a memory cell may be formed by, for example, epitaxial growth.
衬底1001上所生长的各层可以是单晶的半导体层。这些层由于分别生长或者掺杂，从而彼此之间可以具有晶体界面或掺杂浓度界面。Each layer grown on the substrate 1001 may be a single crystal semiconductor layer. Since these layers are grown or doped separately, they may have crystal interfaces or doping concentration interfaces with each other.
牺牲层10031随后可以被替换为用于将器件与衬底隔离的隔离层，其厚度可以对应于希望形成的隔离层的厚度，例如为约10nm-50nm。根据电路设计，也可以不设置牺牲层10031。器件层10051随后限定存储单元的有源区，厚度例如可以为约40nm-200nm。The sacrificial layer 10031 may then be replaced with an isolation layer for isolating the device from the substrate, the thickness of which may correspond to the thickness of the isolation layer desired to be formed, for example, about 10 nm-50 nm. Depending on the circuit design, the sacrificial layer 10031 may not be provided. Device layer 10051 then defines the active region of the memory cell and may, for example, have a thickness of about 40 nm-200 nm.
这些半导体层可以包括各种合适的半导体材料，例如元素半导体材料如Si或Ge、化合物半导体材料如SiGe等。考虑以下将牺牲层10031替换为隔离层的工艺，牺牲层10031可以相对于器件层10051具备刻蚀选择性。例如，牺牲层10031可以包括SiGe(Ge的原子百分比例如为约15％-30％)，器件层10051可以包括Si。These semiconductor layers may include various suitable semiconductor materials, such as elemental semiconductor materials such as Si or Ge, compound semiconductor materials such as SiGe, and the like. Considering the following process of replacing the sacrificial layer 10031 with an isolation layer, the sacrificial layer 10031 may have etching selectivity relative to the device layer 10051 . For example, the sacrificial layer 10031 may include SiGe (the atomic percentage of Ge is, for example, about 15%-30%), and the device layer 10051 may include Si.
在生长器件层10051时，可以对其进行原位掺杂。例如，对于n型器件，可以进行p型掺杂，掺杂浓度为约1E17-1E19cm-3。这种掺杂可以限定随后形成的沟道区中的掺杂特性，以例如调节器件阈值电压(Vt)、控制短沟道效应等。在此，在竖直方向上，掺杂浓度可以具有非均匀的分布，以优化器件性能。例如，在与漏区(之后连接到位线)接近的区域中浓度相对较高以减少短沟道效应，而在与源区(之后连接到源极线)接近的区域中浓度相对较低以降低沟道电阻。这可以通过在生长的不同阶段引入不同剂量的掺杂剂来实现。As device layer 10051 is grown, it may be doped in situ. For example, for n-type devices, p-type doping can be performed with a doping concentration of approximately 1E17-1E19cm-3 . This doping can define the doping characteristics in the subsequently formed channel region to, for example, adjust the device threshold voltage (Vt ), control short channel effects, etc. Here, the doping concentration can have a non-uniform distribution in the vertical direction to optimize device performance. For example, the concentration is relatively high in the region close to the drain region (later connected to the bit line) to reduce the short channel effect, while the concentration is relatively low in the region close to the source region (later connected to the source line) to reduce Channel resistance. This can be achieved by introducing different doses of dopants at different stages of growth.
为增加集成密度，可以设置多个器件层。例如，可以通过外延生长，在器件层10051上设置器件层10052、10053、10054，器件层之间通过用于限定隔离层的牺牲层10032、10033、10034间隔开。尽管图1中仅示出了四个器件层，但是本公开不限于此。根据电路设计，某些器件层之间也可以不设置隔离层。器件层10052、10053、10054可以具有与器件层10051相同或相似的厚度和/或材料，也可以具有不同的厚度和/或材料。在此，仅为方便描述起见，假设各器件层具有相同的配置。To increase integration density, multiple device layers can be provided. For example, device layers 10052 , 10053 , and 1005 4 can be provided on the device layer 10051 through epitaxial growth, and the device layers are separated by sacrificial layers 10032 , 10033 , and 10034 for defining isolationlayers . Although only four device layers are shown in Figure 1, the present disclosure is not limited thereto. Depending on the circuit design, isolation layers may not be provided between some device layers. Device layers 10052 , 10053 , 10054 may have the same or similar thickness and/or material as device layer 10051 , or may have different thicknesses and/or materials. Here, for convenience of description only, it is assumed that each device layer has the same configuration.
在衬底1001上形成的这些层上，可以设置硬掩模层1015，以方便构图。例如，硬掩模层1015可以包括氮化物(例如，氮化硅)，厚度为约50nm-200nm。On these layers formed on substrate 1001, a hard mask layer 1015 may be provided to facilitate patterning. For example, hard mask layer 1015 may include nitride (eg, silicon nitride) with a thickness of about 50 nm-200 nm.
在硬掩模层1015与器件层10054之间，也可以设置用于限定隔离层的牺牲层10035。关于牺牲层10032至10035，可以参见以上关于牺牲层10031的描述。A sacrificial layer 10035 for defining an isolation layer may also be provided between the hard mask layer 1015 and the device layer 10054 . Regarding the sacrificial layers 10032 to 10035 , please refer to the above description about the sacrificial layer 10031 .
以下，一方面，需要能到达牺牲层的加工通道，以便将牺牲层替换为隔离层；另一方面，需要限定用于形成栅的区域。根据本公开的实施例，这两者可以结合进行。具体地，可以利用加工通道来限定栅区域。In the following, on the one hand, a processing channel is required to reach the sacrificial layer in order to replace the sacrificial layer with an isolation layer; on the other hand, the area for forming the gate needs to be defined. According to embodiments of the present disclosure, the two may be combined. In particular, machining channels may be used to define gate areas.
例如，如图2(a)和2(b)所示，可以在硬掩模层1015上形成光刻胶1017，并通过光刻将其构图为具有一系列开口，这些开口可以限定加工通道的位置。开口可以是各种合适的形状，例如圆形、矩形、方形、多边形等，并具有合适的大小，例如直径或边长为约20nm-500nm。在此，这些开口(特别是在器件区中)可以排列成阵列形式，例如沿图2(a)中纸面内水平方向和竖直方向的二维阵列。该阵列随后可以限定存储单元的阵列。尽管在图2(a)中将开口示出为以基本上一致的大小、大致均匀的密度形成在衬底(包括随后将制作存储单元的器件区以及随后将制作接触部的接触区)上，但是本公开不限于此。开口的大小和/或密度可以改变，例如接触区中开口的密度可以小于器件区中开口的密度，以降低接触区中的电阻。For example, as shown in Figures 2(a) and 2(b), photoresist 1017 can be formed on hard mask layer 1015 and patterned by photolithography to have a series of openings that can define the processing channels. Location. The openings may be in various suitable shapes, such as circles, rectangles, squares, polygons, etc., and have suitable sizes, such as a diameter or side length of about 20 nm to 500 nm. Here, the openings (especially in the device area) can be arranged in the form of an array, for example a two-dimensional array along the horizontal and vertical directions within the plane of the paper in Figure 2(a). This array may then define an array of memory cells. Although the openings are shown in FIG. 2(a) as being formed at a substantially uniform size and at a substantially uniform density on the substrate (including the device region where the memory cells will subsequently be fabricated and the contact regions where the contacts will subsequently be fabricated), However, the present disclosure is not limited to this. The size and/or density of the openings may be varied, for example the density of openings in the contact area may be less than the density of openings in the device area to reduce resistance in the contact area.
如图3所示，可以如此构图的光刻胶1017作为刻蚀掩模，通过各向异性刻蚀如反应离子刻蚀(RIE)，来刻蚀衬底1001上的各层，以便形成加工通道T。RIE可以沿大致竖直的方向(例如，垂直于衬底表面的方向)进行，并可以进行到衬底1001中。于是，在衬底1001上留下了一系列竖直的加工通道T。器件区中的加工通道T还限定了栅区域。之后，可以去除光刻胶1017。As shown in FIG. 3 , the photoresist 1017 thus patterned can be used as an etching mask to etch various layers on the substrate 1001 through anisotropic etching such as reactive ion etching (RIE) to form processing channels. T. RIE may be performed in a generally vertical direction (eg, perpendicular to the substrate surface) and may be performed into substrate 1001 . Thus, a series of vertical processing channels T are left on the substrate 1001. The processing channel T in the device area also defines the gate area. Afterwards, the photoresist 1017 can be removed.
当前，牺牲层的侧壁在加工通道T中露出。于是，可以经由露出的侧壁，将牺牲层替换为隔离层。考虑到替换时对器件层10051至10054的支撑功能，可以形成支撑层。Currently, the side walls of the sacrificial layer are exposed in the processing channel T. The sacrificial layer can then be replaced with an isolation layer via the exposed sidewalls. The support layer may be formed considering the support function of the device layers 10051 to 10054 during replacement.
例如，如图4所示，可以通过例如淀积如化学气相淀积(CVD)等，在衬底1001上形成支撑材料层。支撑材料层可以大致共形的方式形成。考虑到刻蚀选择性，特别是相对于硬掩模层1015(在该示例中为氮化物)以及随后形成的隔离层(在该示例中为氧化物)，支撑材料层可以包括例如SiC。可以例如通过形成光刻胶1021，并配合光刻胶1021进行选择性刻蚀如RIE，去除部分加工通道T中的支撑材料层，而保留其余加工通道T中的支撑材料层。留下的支撑材料层形成支撑层1019。这样，一方面可以通过其中没有形成支撑层1019的加工通道来替换牺牲层，另一方面可以通过其他加工通道中的支撑层1019来支撑器件层10051至10054。之后，可以去除光刻胶1021。For example, as shown in FIG. 4 , a layer of support material may be formed on the substrate 1001 by, for example, deposition such as chemical vapor deposition (CVD). The layer of support material may be formed in a generally conformal manner. With regard to etch selectivity, particularly with respect to the hard mask layer 1015 (nitride in this example) and the subsequently formed isolation layer (oxide in this example), the support material layer may include, for example, SiC. For example, by forming a photoresist 1021 and performing selective etching such as RIE in conjunction with the photoresist 1021, the support material layer in part of the processing channels T can be removed, while the support material layer in the remaining processing channels T can be retained. The remaining layer of support material forms support layer 1019. In this way, on the one hand, the sacrificial layer can be replaced by a processing channel in which the support layer 1019 is not formed, and on the other hand, the device layers 10051 to 10054 can be supported by the support layer 1019 in other processing channels. Afterwards, the photoresist 1021 can be removed.
其中形成有支撑层1019的加工通道与其中没有形成支撑层1019的加工通道的排布可以通过光刻胶1021的构图来实现，并且为了工艺的一致性和均匀性，它们可以大致均匀地分布。如图4中所示，其中形成有支撑层1019的加工通道与其中没有形成支撑层1019的加工通道可以交替排列。The arrangement of the processing channels in which the support layer 1019 is formed and the processing channels in which the support layer 1019 is not formed can be achieved by patterning the photoresist 1021, and for the sake of process consistency and uniformity, they can be distributed approximately evenly. As shown in FIG. 4 , processing channels in which the support layer 1019 is formed and processing channels in which the support layer 1019 is not formed may be arranged alternately.
然后，如图5所示，可以经由加工通道T，通过选择性刻蚀，去除牺牲层10031至10035。由于支撑层1019的存在，可以保持器件层10051至10054不会坍塌。在由于牺牲层的去除而留下的空隙中，可以通过例如淀积(优选为原子层淀积(ALD)，以更好地控制膜厚)然后回蚀(例如，竖直方向的RIE)的工艺，填充电介质材料以形成隔离层10231、10232、10233、10234和10235。Then, as shown in FIG. 5 , the sacrificial layers 10031 to 10035 can be removed by selective etching through the processing channel T. Due to the presence of the support layer 1019, the device layers 10051 to 10054 can be kept from collapsing. In the void left by the removal of the sacrificial layer, it can be removed by, for example, deposition (preferably atomic layer deposition (ALD) to better control the film thickness) and then etching back (e.g., RIE in the vertical direction). Process, filling dielectric material to form isolation layers 10231 , 10232 , 10233 , 10234 and 10235 .
根据本公开的实施例，为实现源/漏掺杂，隔离层10231至10235中可以包含有掺杂剂(对于n型存储单元为n型掺杂剂，对于p型存储单元为p型掺杂剂)。于是，隔离层10231至10235可以成为固相掺杂剂源层。例如，隔离层10231至10235可以包括磷(P)含量为约0.1％-10％的磷硅玻璃(PSG)(对于n型存储单元)，或者硼(B)含量为约0.1％-10％的硼硅玻璃(BSG)(对于p型存储单元)。According to embodiments of the present disclosure, to achieve source/drain doping, the isolation layers 10231 to 10235 may include dopants (n-type dopants for n-type memory cells, p-type dopants for p-type memory cells). dopants). Thus, the isolation layers 10231 to 10235 may become solid phase dopant source layers. For example, the isolation layers 10231 to 10235 may include phosphosilicate glass (PSG) with a phosphorus (P) content of about 0.1%-10% (for n-type memory cells), or a boron (B) content of about 0.1%-10% % of borosilicate glass (BSG) (for p-type memory cells).
在该示例中，源/漏掺杂通过固相掺杂剂源层而非原位掺杂实现，这可以实现陡峭的高源/漏掺杂，并可以抑制外延生长时进行原位生长而可能导致的交叉污染。In this example, source/drain doping is achieved through a solid phase dopant source layer rather than in-situ doping, which allows for steep, high source/drain doping and inhibits epitaxial growth that would otherwise be possible with in-situ growth. resulting in cross-contamination.
之后，可以通过选择性刻蚀，去除支撑层1019。Afterwards, the support layer 1019 can be removed by selective etching.
在加工通道，特别是器件区的加工通道中，可以形成栅堆叠。在此，要形成存储器件，可以通过栅堆叠来实现存储功能。例如，栅堆叠中可以包括存储结构，如电荷捕获材料或铁电材料等。In the processing channel, especially in the device area, a gate stack may be formed. Here, to form a memory device, the memory function can be implemented by gate stacking. For example, memory structures such as charge trapping materials or ferroelectric materials may be included in the gate stack.
如图6所示，可以例如通过淀积，依次形成存储功能层1025和栅导体层1027。存储功能层1025可以大致共形的方式形成，栅导体层1027可以填充加工通道T中形成存储功能层1025之后剩余的空隙。可以对形成的栅导体层1027和存储功能层1025进行平坦化处理如化学机械抛光(CMP，例如可以停止于硬掩模层1015)，从而栅导体层1027和存储功能层1025可以留于加工通道T中，形成栅堆叠。As shown in FIG. 6 , the memory function layer 1025 and the gate conductor layer 1027 may be formed sequentially, for example, by deposition. The memory function layer 1025 may be formed in a substantially conformal manner, and the gate conductor layer 1027 may fill the remaining voids in the processing channel T after the memory function layer 1025 is formed. The formed gate conductor layer 1027 and the storage function layer 1025 may be subjected to a planarization process such as chemical mechanical polishing (CMP, for example, may stop at the hard mask layer 1015), so that the gate conductor layer 1027 and the storage function layer 1025 may remain in the processing channel. In T, a gate stack is formed.
存储功能层1025可以基于介电电荷捕获、铁电材料效应或带隙工程电荷存储(SONOS)等。例如，存储功能层1025可以包括电介质隧穿层(例如厚度为约1nm-5nm的氧化物，可通过氧化或ALD形成)-能带偏移层(例如厚度为约2nm-10nm的氮化物，可通过CVD或ALD形成)-隔离层(例如厚度为约2nm-6nm的氧化物，可通过氧化、CVD或ALD形成)。这种三层结构可导致捕获电子或空穴的能带结构。或者，存储功能层1025可以包括铁电材料层，例如厚度为约2nm-20nm的HtZrO2。The storage function layer 1025 may be based on dielectric charge trapping, ferroelectric material effect or band gap engineered charge storage (SONOS), etc. For example, the memory function layer 1025 may include a dielectric tunneling layer (eg, an oxide with a thickness of about 1 nm-5 nm, which may be formed by oxidation or ALD) - an energy band offset layer (eg, a nitride with a thickness of about 2 nm-10 nm, which may be formed by oxidation or ALD) Formed by CVD or ALD) - isolation layer (eg, an oxide with a thickness of about 2 nm to 6 nm, which may be formed by oxidation, CVD or ALD). This three-layer structure can lead to an energy band structure that traps electrons or holes. Alternatively, the memory function layer 1025 may include a layer of ferroelectric material, such as HtZrO2 with a thickness of approximately 2 nm to 20 nm.
栅导体层1027可以包括例如(掺杂的，例如在n型器件的情况下p型掺杂)多晶硅或金属栅材料。The gate conductor layer 1027 may comprise, for example (doped, eg p-type doped in the case of n-type devices) polysilicon or metal gate material.
可以进行退火处理，以将固相掺杂剂源层中的掺杂剂驱入器件层中。对于器件层10051至10054中的每一个而言，其上下两端的隔离层中的掺杂剂分别从上下两端进入其中，从而可以在其上下两端形成高掺杂区10071、10091；10072、10092；10073、10093；10074、10094(例如，约1E19-1E21cm-3的n型掺杂)，从而限定源/漏区。在此，可以控制掺杂剂从隔离层向器件层中的扩散深度(例如，为约10nm-50nm)，使各器件层在竖直方向上的中部可以保持相对低掺杂，例如基本保持生长时原位掺杂导致的掺杂极性(例如，p型掺杂)和掺杂浓度(例如，1E17-1E19cm-3)，并可以限定沟道区。An annealing process may be performed to drive dopants from the solid phase dopant source layer into the device layers. For each of the device layers 10051 to 10054 , the dopants in the isolation layers at its upper and lower ends enter it respectively, so that highly doped regions 10071 and 1009 can be formed at its upper and lower ends.1 ; 10072 , 10092 ; 10073 , 10093 ; 10074 , 10094 (eg, n-type doping of about 1E19-1E21cm-3 ), thereby defining the source/drain regions. Here, the diffusion depth of dopants from the isolation layer into the device layer can be controlled (for example, about 10 nm-50 nm), so that the middle portion of each device layer in the vertical direction can remain relatively low-doped, such as substantially maintaining growth. The doping polarity (eg, p-type doping) and doping concentration (eg, 1E17-1E19cm-3 ) caused by in-situ doping can define the channel region.
原位掺杂所能实现的掺杂浓度一般低于1E20cm-3。根据本公开的实施例，通过从固相掺杂剂源层的扩散来进行源/漏掺杂，这可以实现高掺杂，例如最高掺杂浓度可以高于1E20cm-3，甚至高达约7E20-3E21cm-3。另外，由于扩散特性，源/漏区中可以具有在竖直方向上从靠近固相掺杂剂源层一侧向着靠近沟道区一侧下降的掺杂浓度梯度。The doping concentration that can be achieved by in-situ doping is generally lower than 1E20cm-3 . According to embodiments of the present disclosure, source/drain doping is performed by diffusion from the solid phase dopant source layer, which can achieve high doping, for example, the maximum doping concentration can be higher than 1E20cm-3 , or even as high as about 7E20- 3E21cm-3 . In addition, due to diffusion characteristics, the source/drain region may have a doping concentration gradient that decreases in the vertical direction from a side close to the solid-phase dopant source layer to a side close to the channel region.
这种扩散掺杂可以实现陡峭的掺杂浓度分布。例如，在源/漏区与沟道区之间，可以具有陡峭的掺杂浓度突变，例如小于约5nm/dec-20nm/dec(即，掺杂浓度至少一个数量级的下降在小于约5nm-20mm的范围内发生)。竖直方向上的这种突变区可以称为“界面层”。This diffusion doping can achieve a steep doping concentration profile. For example, between the source/drain region and the channel region, there may be a steep doping concentration change, such as less than about 5 nm/dec-20 nm/dec (i.e., at least an order of magnitude drop in doping concentration between less than about 5 nm/dec-20 nm/dec). occurs within the scope). This abrupt region in the vertical direction may be called an "interface layer".
由于从各隔离层以大致相同的扩散特性向器件层中扩散，每一源/漏区10071、10091；10072、10092；10073、10093；10074、10094可以在横向上可以实质上共面。类似地，每一沟道区可以在横向上实质上共面。另外，如上所述，沟道区可以具有竖直方向上的非均匀分布，在靠近一侧的源/漏区(漏区)处掺杂浓度相对较高，而在靠近另一侧的源/漏区(源区)处掺杂浓度相对较低。Due to diffusion from each isolation layer into the device layer with substantially the same diffusion characteristics, each source/drain region 10071 , 10091 ; 10072 , 10092 ; 10073 , 10093 ; 10074 , 10094 can be laterally Can be substantially coplanar. Similarly, each channel region may be substantially coplanar laterally. In addition, as mentioned above, the channel region may have a non-uniform distribution in the vertical direction, with a relatively high doping concentration near the source/drain region (drain region) on one side, and a relatively high doping concentration near the source/drain region (drain region) on the other side. The doping concentration at the drain region (source region) is relatively low.
如图6所示，具有存储功能层的栅堆叠(1025/1027)被器件层围绕。栅堆叠与器件层相配合，限定存储单元，如图6中的虚线圈所示。沟道区可以连接相对两侧的源/漏区，沟道区可以受栅堆叠的控制。单个存储单元中上下两端的源/漏区之一用作源区，可以电连接到源极线；另一个用作漏区，可以电连接到位线。对于每两个竖直相邻的存储单元，下方存储单元的上端的源/漏区和上方存储单元的下端的源/漏区可以用作源区，从而它们可以共用相同的源极线连接。As shown in Figure 6, the gate stack (1025/1027) with the memory functional layer is surrounded by device layers. The gate stack cooperates with the device layer to define the memory cell, as shown by the dotted circle in Figure 6. The channel region can connect the source/drain regions on opposite sides, and the channel region can be controlled by the gate stack. One of the source/drain regions at the upper and lower ends of a single memory cell is used as the source region and can be electrically connected to the source line; the other is used as the drain region and can be electrically connected to the bit line. For every two vertically adjacent memory cells, the source/drain region at the upper end of the lower memory cell and the source/drain region at the lower end of the upper memory cell can be used as source regions, so that they can share the same source line connection.
栅堆叠在竖直方向上呈柱状延伸，与多个器件层相交迭，从而可以限定在竖直方向上彼此叠置的多个存储单元。与单个栅堆叠柱相关联的存储单元可以形成存储单元串。与栅堆叠柱的布局(对应于上述加工通道T的布局，例如二维阵列)相对应，在衬底上布置有多个这样的存储单元串，从而形成存储单元的三维(3D)阵列。The gate stack extends in a columnar shape in the vertical direction and overlaps with a plurality of device layers, thereby defining a plurality of memory cells stacked on each other in the vertical direction. Memory cells associated with a single gate stack pillar may form a string of memory cells. Corresponding to the layout of the gate stack pillars (corresponding to the layout of the above-mentioned processing channel T, such as a two-dimensional array), a plurality of such memory cell strings are arranged on the substrate, thereby forming a three-dimensional (3D) array of memory cells.
这样，就完成了(器件区中)存储单元的制作。然后，可以(在接触区中)制作各种电接触部以实现所需的电连接。In this way, the fabrication of the memory cell (in the device area) is completed. Various electrical contacts can then be made (in the contact areas) to achieve the desired electrical connection.
为实现到各器件层的电连接，在接触区中可以形成阶梯结构。本领域存在多种方式来形成这样的阶梯结构。根据本公开的实施例，阶梯结构例如可以如下形成。To achieve electrical connection to the respective device layers, a step structure can be formed in the contact area. There are many ways in the art to form such a ladder structure. According to embodiments of the present disclosure, the stepped structure may be formed as follows, for example.
如图6所示，当前的栅堆叠在硬掩模层1015的表面处露出。为了以下在制作阶梯结构时保护(器件区中的)栅堆叠，可以在硬掩模层1015上先形成另一硬掩模层1029，如图7(a)、7(b)和7(c)所示。例如，硬掩模层1029可以包括氧化物。在硬掩模层1029上，可以形成光刻胶1031，并将其通过光刻构图为遮蔽器件区而露出接触区。可以光刻胶1031作为刻蚀掩模，通过选择性刻蚀如RIE，刻蚀硬掩模层1029、硬掩模层1015、隔离层10235和栅堆叠，以露出器件层。可以通过控制刻蚀深度，使得刻蚀后接触区中被光刻胶1031露出的表面大致平坦。例如，可以先刻蚀硬掩模层1029；然后刻蚀栅导体层1027，对栅导体层1027的刻蚀可以停止在器件层10054的顶面附近；然后，可以依次刻蚀硬掩模层1015和隔离层10235；如此刻蚀之后，存储功能层1025的顶端可以突出于器件层10054的顶面上方，并可以通过RIE去除。这样，在接触区与器件区之间形成了一个台阶。之后，可以去除光刻胶1031。As shown in FIG. 6 , the current gate stack is exposed at the surface of hard mask layer 1015 . In order to protect the gate stack (in the device area) when fabricating the ladder structure, another hard mask layer 1029 can be formed on the hard mask layer 1015 first, as shown in Figures 7(a), 7(b) and 7(c) ) shown. For example, hard mask layer 1029 may include oxide. On the hard mask layer 1029, a photoresist 1031 can be formed and patterned by photolithography to shield the device area and expose the contact area. The photoresist 1031 can be used as an etching mask, and the hard mask layer 1029, the hard mask layer 1015, the isolation layer10235 and the gate stack are etched through selective etching such as RIE to expose the device layer. The etching depth can be controlled so that the surface exposed by the photoresist 1031 in the contact area after etching is substantially flat. For example, the hard mask layer 1029 can be etched first; then the gate conductor layer 1027 can be etched, and the etching of the gate conductor layer 1027 can stop near the top surface of the device layer1005 ; then, the hard mask layer 1015 can be etched sequentially. and the isolation layer 10235 ; after such etching, the top of the storage function layer 1025 can protrude above the top surface of the device layer 10054 and can be removed by RIE. In this way, a step is formed between the contact area and the device area. Afterwards, the photoresist 1031 can be removed.
如图8(a)和8(b)所示，可以通过侧墙(spacer)形成工艺，在接触区与器件区之间的台阶处形成侧墙1033。例如，可以通过以大致共形的方式淀积一层电介质如氧化物，然后对淀积的电介质进行各向异性刻蚀如竖直方向上的RIE，以去除所淀积电介质的横向延伸部分，而留下其竖直延伸部分，从而形成侧墙1033。在此，考虑到硬掩模层1029也包括氧化物，可以控制RIE的刻蚀深度实质上等于或稍大于电介质的淀积厚度，以避免完全去除硬掩模层1029。侧墙1033的宽度(在图中水平方向上)可以基本等于电介质的淀积厚度。侧墙1033的宽度限定了随后到器件层10054中的源/漏区10094的接触部的着落垫(1anding pad)的大小。As shown in Figures 8(a) and 8(b), a spacer 1033 can be formed at the step between the contact area and the device area through a spacer formation process. For example, lateral extensions of the deposited dielectric can be removed by depositing a layer of dielectric, such as an oxide, in a generally conformal manner and then anisotropically etching the deposited dielectric, such as RIE in the vertical direction. The vertical extension portion is left, thereby forming the side wall 1033 . Here, considering that the hard mask layer 1029 also includes an oxide, the etching depth of the RIE can be controlled to be substantially equal to or slightly greater than the deposition thickness of the dielectric to avoid completely removing the hard mask layer 1029 . The width of the spacers 1033 (in the horizontal direction in the figure) may be substantially equal to the deposited thickness of the dielectric. The width of spacers 1033 defines the size of the landing pad for subsequent contacts to source/drain regions 10094 in device layer 10054 .
以如此形成的侧墙1033作为刻蚀掩模，可以通过选择性刻蚀如RIE，来刻蚀露出的器件层10054中的源/漏区10094以及栅堆叠，以露出器件层10054中的沟道区。可以通过控制刻蚀深度，使得刻蚀后接触区中被侧墙1033露出的表面大致平坦。例如，可以先刻蚀源/漏区10094和栅导体层1027(例如，分别为Si和多晶Si；如果栅导体层1027包括金属栅，则它们可以分别刻蚀)，对它们的刻蚀可以停止于器件层10054中的沟道区；如此刻蚀之后，存储功能层1025的顶端可以突出于器件层10054中的沟道区上方，并可以通过RIE去除。这样，在接触区中在器件层10054中的源/漏区10094与被侧墙1033露出的表面之间形成了又一台阶。Using the sidewalls 1033 thus formed as an etching mask, the source/drain regions 10094 and the gate stack in the exposed device layer 10054 can be etched through selective etching such as RIE to expose the device layer 10054 channel area. The etching depth can be controlled so that the surface exposed by the sidewalls 1033 in the contact area after etching is substantially flat. For example, the source/drain region10094 and the gate conductor layer 1027 can be etched first (for example, Si and polycrystalline Si respectively; if the gate conductor layer 1027 includes a metal gate, they can be etched separately), and their etching can Stopping at the channel area in the device layer 10054 ; after such etching, the top of the storage function layer 1025 can protrude above the channel area in the device layer 10054 , and can be removed by RIE. In this way, another step is formed in the contact region between the source/drain region 10094 in the device layer 10054 and the surface exposed by the spacer 1033 .
可以按照以上结合图8(a)和8(b)描述的工艺，通过形成侧墙，以侧墙为刻蚀掩模进行刻蚀，来在接触区中形成多个台阶，如图9(a)和9(b)所示。这些台阶形成这样的阶梯结构，使得对于各器件层中需要电连接的各源/漏区以及可选地沟道区，其相对于上方的区域，端部相对突出，以限定到该区域的接触部的着落焊盘。图9(a)和9(b)中的1035表示各次形成的侧墙在处理之后的留下部分。由于这些侧墙1035与隔离层均为氧化物，在此将它们示出为一体。Multiple steps can be formed in the contact area by forming sidewalls and etching using the sidewalls as etching masks according to the process described above in conjunction with Figures 8(a) and 8(b), as shown in Figure 9(a) ) and 9(b). These steps form a ladder structure such that for each source/drain region and optionally the channel region in each device layer that require electrical connection, its ends are relatively protruding relative to the region above to define a contact to this region landing pad. 1035 in Figures 9(a) and 9(b) represents the remaining portion of the sidewalls formed each time after processing. Since these sidewalls 1035 and the isolation layer are both made of oxide, they are shown as one body here.
之后，可以制作接触部。After that, the contacts can be made.
例如，如图10(a)和10(b)所示，可以通过淀积氧化物并平坦化如CMP，来形成层间电介质层1037。在此，由于均为氧化物，将之前的隔离层和侧墙1035均示出为与层间电介质层1037一体。然后，如图11(a)、11(b)和11(c)所示，可以在层间电介质层1037中形成接触部1039、1041。具体地，接触部1039形成在器件区中，电连接到栅堆叠中的栅导体层1027；接触部1041形成在接触区中，电连接到各源/漏区以及可选地沟道区。接触区中的接触部1041可以避开接触区中残留的栅堆叠。这些接触部可以通过在层间电介质层1037中刻蚀孔洞，并在其中填充导电材料如金属来形成。For example, as shown in Figures 10(a) and 10(b), interlayer dielectric layer 1037 may be formed by depositing oxide and planarizing such as CMP. Here, since they are both oxides, the previous isolation layer and spacer 1035 are shown as being integrated with the interlayer dielectric layer 1037 . Then, as shown in FIGS. 11(a), 11(b), and 11(c), contacts 1039, 1041 may be formed in the interlayer dielectric layer 1037. Specifically, a contact 1039 is formed in the device region and is electrically connected to the gate conductor layer 1027 in the gate stack; a contact 1041 is formed in the contact region and is electrically connected to each source/drain region and optionally the channel region. The contact portion 1041 in the contact area may avoid the remaining gate stack in the contact area. These contacts may be formed by etching holes in the interlayer dielectric layer 1037 and filling them with a conductive material such as a metal.
在此，接触部1039可以电连接到字线。通过字线，经由接触部1039，可以向栅导体层1027施加栅控制信号。对于竖直方向上每两个相邻的存储单元，位于中间的源/漏区，即第一器件层10051中的源/漏区10091和第二器件层10052中的源/漏区10072，或者第三器件层10053中的源/漏区10093和第四器件层10054中的源/漏区10074，可以经由公共的接触部1041而电连接到源极线，如图11(c)中的虚线圈所示；位于上下两端的源/漏区，即第一器件层10051中的源/漏区10071和第二器件层10052中的源/漏区10092，或者第三器件层10053中的源/漏区10073和第四器件层10054中的源/漏区10094，可以经由接触部1041而分别电连接到位线。这样，可以得到NOR型配置。在此，还形成了到沟道区的接触部。这种接触部可以称为体接触部，并可以接收体偏置，以调节器件阈值电压。Here, the contact 1039 may be electrically connected to the word line. Through the word lines, gate control signals may be applied to gate conductor layer 1027 via contacts 1039 . For every two adjacent memory cells in the vertical direction, the source/drain region located in the middle, that is, the source/drain region 10091 in the first device layer 10051 and the source/drain region in the second device layer 10052 10072 , or the source/drain region 10093 in the third device layer 10053 and the source/drain region 10074 in the fourth device layer 10054 , may be electrically connected to the source line via a common contact 1041, such as Shown by the dotted circle in Figure 11(c); the source/drain regions located at the upper and lower ends, that is, the source/drain region 10071 in the first device layer 10051 and the source/drain region 1009 in the second device layer 100522 , or the source/drain region 10073 in the third device layer 10053 and the source/drain region 10094 in the fourth device layer 10054 may be electrically connected to bit lines respectively via the contact portion 1041. In this way, a NOR type configuration can be obtained. Here, a contact to the channel region is also formed. Such contacts may be referred to as body contacts and may receive body bias to adjust the device threshold voltage.
在此，将竖直方向上相邻的两个存储单元设置为位于它们之间边界附近的源/漏区电连接到源极线。这可以减少布线数量。但是，本公开不限于此。例如，竖直方向上相邻的存储单元可以设置为源区-沟道区-漏区或者漏区-沟道区-源区的相同配置。Here, two vertically adjacent memory cells are arranged so that the source/drain regions located near the boundary between them are electrically connected to the source lines. This reduces the amount of wiring. However, the present disclosure is not limited thereto. For example, vertically adjacent memory cells may be arranged in the same configuration of source region-channel region-drain region or drain region-channel region-source region.
在该实施例中，含有掺杂剂的隔离层(用作固相掺杂剂源层)保留。但是，本公开不限于此。在扩散掺杂之后，可以利用其它材料来替换固相掺杂剂源层。例如，可以利用其它电介质材料特别是不有意包含掺杂剂的电介质材料来替换固相掺杂剂源层，以改进隔离性能。或者，以竖直方向上相邻的每两个器件层为一组，每一组的器件层之间的固相掺杂剂源层(例如，作为一组的器件层10051与10052之间的固相掺杂剂源层10232、作为一组的器件层10053与10054之间的固相掺杂剂源层10234)可以被导电材料如金属或掺杂半导体层替换，以降低(到源极线的)互连电阻；而各组上下侧的固相掺杂剂源层(例如，例如，器件层10051与10052的组下侧的固相掺杂剂源层10231、器件层10051与10052的组上侧也即器件层10053与10054的组下侧的固相掺杂剂源层10233、器件层10053与10054的组上侧的固相掺杂剂源层10235)可以被电介质材料替换，以实现位线之间的隔离。在替换固相掺杂剂源层的情况下，在源/漏区背对沟道区的一侧，也可以形成如上所述的掺杂浓度突变的“界面层”。In this embodiment, the dopant-containing spacer layer (serving as a solid phase dopant source layer) remains. However, the present disclosure is not limited thereto. After diffusion doping, the solid phase dopant source layer can be replaced with other materials. For example, the solid phase dopant source layer may be replaced with other dielectric materials, particularly dielectric materials that do not intentionally contain dopants, to improve isolation performance. Alternatively, every two device layers adjacent in the vertical direction are taken as a group, and the solid phase dopant source layer between the device layers of each group (for example, as a group of device layers 10051 and 10052The solid-phase dopant source layer 10232 between the device layers 10053 and 10054 ) as a set can be replaced by a conductive material such as a metal or a doped semiconductor layer to Lowering the interconnect resistance (to the source line); and solid phase dopant source layer 1023 below each set of device layers 10051 and 100521. The upper side of the set of device layers 10051 and 10052, that is, the solid phase dopant source layer 10233 on the lower side of the set of device layers 10053 and 10054. The solid phase dopant source layer 1023 3 on the upper side of the set of device layers 10053 and 10054 Phase dopant source layer 10235 ) may be replaced with a dielectric material to achieve isolation between bit lines. In the case of replacing the solid-phase dopant source layer, an "interface layer" with a sudden change in doping concentration as described above can also be formed on the side of the source/drain region facing away from the channel region.
图20示意性示出了根据本公开实施例的NOR型存储器件的等效电路图。FIG. 20 schematically shows an equivalent circuit diagram of a NOR type memory device according to an embodiment of the present disclosure.
在图20的示例中，示意性示出了三条字线WL1、WL2、WL3以及八条位线BL1、BL2、BL3、BL4、BL5、BL6、BL7、BL8。但是，位线和字线的具体数目不限于此。在位线与字线交叉之处，设置有存储单元MC。图20中还示出了四条源极线SL1、SL2、SL3、SL4。如上所述，每两个相邻的器件层可以共用相同的源极线连接。另外，各条源极线可以彼此连接，从而各存储单元MC可以连接到公共的源极线。另外，图20中还以虚线示意性示出了可选的到各存储单元的体连接。如下所述，各存储单元的体连接可以电连接到该存储单元的源极线连接。In the example of FIG. 20 , three word lines WL1, WL2, WL3 and eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8 are schematically shown. However, the specific numbers of bit lines and word lines are not limited to this. Memory cells MC are provided where bit lines and word lines intersect. Also shown in Figure 20 are four source lines SL1, SL2, SL3, SL4. As mentioned above, every two adjacent device layers can share the same source line connection. In addition, the respective source lines may be connected to each other, so that the respective memory cells MC may be connected to a common source line. In addition, optional body connections to each memory cell are schematically shown in dashed lines in Figure 20 . As discussed below, the body connection of each memory cell may be electrically connected to the source line connection of that memory cell.
在此，仅为图示方便起见，示出了存储单元MC的二维阵列。可以在与此二维阵列相交的方向上(例如，图中垂直于纸面的方向)，设置多个这样的二维阵列，从而得到三维阵列。Here, for the convenience of illustration only, a two-dimensional array of memory cells MC is shown. Multiple such two-dimensional arrays can be arranged in a direction that intersects this two-dimensional array (for example, the direction perpendicular to the paper surface in the figure), thereby obtaining a three-dimensional array.
图20中字线WL1至WL3的延伸方向可以对应于栅堆叠的延伸方向，即，前述实施例中相对于衬底的竖直方向。在该方向上，相邻的位线之间彼此隔离。The extension direction of the word lines WL1 to WL3 in FIG. 20 may correspond to the extension direction of the gate stack, that is, the vertical direction relative to the substrate in the previous embodiment. In this direction, adjacent bit lines are isolated from each other.
在上述实施例中，接触区中的接触部1041需要避开接触区中残留的栅堆叠。根据本公开的另一实施例，可以在接触区中残留的栅堆叠顶端形成隔离如电介质材料，从而无需刻意避开这些残留的栅堆叠。In the above embodiment, the contact portion 1041 in the contact area needs to avoid the remaining gate stack in the contact area. According to another embodiment of the present disclosure, isolation, such as a dielectric material, may be formed on top of the remaining gate stacks in the contact regions, thereby eliminating the need to deliberately avoid these remaining gate stacks.
例如，如图12(a)和12(b)所示，在如以上结合图7(a)至9(b)所述在接触区中形成阶梯结构之后，可以通过选择性刻蚀如RIE，去除隔离层和侧墙1035，以(在器件区以及接触区中)露出各栅堆叠的顶端。可以通过遮蔽层例如光刻胶，遮蔽器件区中的栅堆叠，而露出接触区中的栅堆叠。对接触区中露出的栅堆叠，可以通过选择性刻蚀如RIE，使得栅导体层凹进例如约50nm-150nm。之后，可以去除遮蔽层。在接触区中由于栅导体层的凹进而形成的空隙中，可以通过例如淀积然后回蚀，填充电介质材料如SiC，以形成隔离插塞1043。For example, as shown in Figures 12(a) and 12(b), after forming the step structure in the contact area as described above in conjunction with Figures 7(a) to 9(b), selective etching such as RIE can be performed, The isolation layer and spacers 1035 are removed to expose the tops of each gate stack (in device and contact areas). The gate stack in the device region may be shielded by a shielding layer such as photoresist, while the gate stack in the contact region may be exposed. For the gate stack exposed in the contact region, the gate conductor layer can be recessed by selective etching such as RIE, for example, about 50 nm to 150 nm. Afterwards, the masking layer can be removed. In the void formed by the recess in the gate conductor layer in the contact area, a dielectric material such as SiC may be filled, for example, by deposition and then etching back, to form an isolation plug 1043 .
然后，可以按照上述实施例形成层间电介质层并在其中形成接触部1039、1041′。在该示例中，接触区中的接触部1041′可以延伸到隔离插塞1043中。因此，接触部1041′可以不限于上述插塞的形式，而是可以形成为条形，以降低接触电阻。条形接触部1041′可以沿着相应层的着落垫(即，阶梯结构中的台阶)延伸。Then, the interlayer dielectric layer may be formed and the contacts 1039, 1041' may be formed therein according to the above-described embodiment. In this example, the contact portion 1041 ′ in the contact area may extend into the isolation plug 1043 . Therefore, the contact portion 1041' may not be limited to the above-mentioned plug form, but may be formed in a strip shape to reduce contact resistance. The strip contact portion 1041' may extend along the landing pad of the corresponding layer (ie, the step in the ladder structure).
在上述实施例中，由于沟道层轻掺杂或未有意掺杂，体接触部与沟道层之间的接触电阻可能相对较大。根据本公开的另一实施例，可以在沟道层与体接触部相接触之处形成(相对于沟道层中至少一部分的)高掺杂区，以降低接触电阻。例如，在如上所述形成层间电介质层并在层间电介质层中刻蚀出用于接触部的孔洞之后，可以形成光刻胶1045，并通过光刻将光刻胶1045构图为露出要形成体接触部的孔洞。可以经由这些孔洞，例如通过离子注入，在沟道层的着落垫中，形成高掺杂区1047。高掺杂区1047中的掺杂类型可以与沟道层的掺杂类型相同，但掺杂浓度相对较高。之后，可以去除光刻胶1045。然后，可以在层间电介质层的孔洞中形成接触部。In the above embodiments, since the channel layer is lightly doped or not intentionally doped, the contact resistance between the body contact and the channel layer may be relatively large. According to another embodiment of the present disclosure, a highly doped region (relative to at least a portion of the channel layer) may be formed where the channel layer contacts the body contact to reduce contact resistance. For example, after forming the interlayer dielectric layer and etching holes for contacts in the interlayer dielectric layer as described above, photoresist 1045 may be formed and patterned by photolithography to expose the layers to be formed. Holes in the body contact part. Highly doped regions 1047 can be formed in the landing pads of the channel layer via these holes, for example by ion implantation. The doping type in the highly doped region 1047 may be the same as that of the channel layer, but the doping concentration is relatively high. Afterwards, the photoresist 1045 can be removed. Contacts may then be formed in the holes of the interlayer dielectric layer.
在上述实施例中，单独提供体接触部。根据本公开的其他实施例，体接触部可以与源极线接触部一体，以节省面积。例如，如图14所示，接触部1041″可以与相邻两个器件层各自的沟道区以及沟道区之间的源/漏区相接触。与前述实施例中在每个相邻的区域之间形成台阶不同，在图14的实施例中，在相邻两个器件层各自的沟道区以及沟道区之间的源/漏区这四个区域中，可以仅在上方的三个区域与下方的一个区域之间形成一个台阶，以节省面积。In the above-described embodiment, the body contact portion is provided separately. According to other embodiments of the present disclosure, the body contact may be integrated with the source line contact to save area. For example, as shown in FIG. 14 , the contact portion 1041″ may be in contact with the channel region of each of two adjacent device layers and the source/drain region between the channel regions. In the previous embodiment, the contact portion 1041″ may be in contact with the channel region of each adjacent device layer and the source/drain region between the channel regions. The formation of steps between regions is different. In the embodiment of Figure 14, among the four regions of the channel region of each of the two adjacent device layers and the source/drain region between the channel regions, only the upper three regions can be formed. A step is formed between one area and the area below to save area.
在上述实施例中，接触部与相应的着落垫直接接触。根据本公开的其他实施例，可以在着落垫处形成硅化物，以降低接触电阻。更具体地，在接触区的各台阶处，台阶的横向表面用作着落垫，可以在其上形成硅化物。另一方面，在台阶的竖直表面上，可以不形成硅化物，以免使相邻台阶各自的着落垫之间短路。In the above embodiment, the contact portion is in direct contact with the corresponding landing pad. According to other embodiments of the present disclosure, silicide may be formed at the landing pad to reduce contact resistance. More specifically, at each step in the contact area, the lateral surface of the step serves as a landing pad on which silicide can be formed. On the other hand, silicide may not be formed on the vertical surfaces of the steps to avoid shorting between the respective landing pads of adjacent steps.
例如，如图15所示，在如以上结合图7(a)至9(b)所述在接触区中形成阶梯结构之后，可以通过选择性刻蚀如RIE，去除隔离层和侧墙1035，以在接触区中露出各台阶的表面。可以通过侧墙形成工艺，在各台阶的竖直表面上形成电介质侧墙1049，以将这些竖直表面遮蔽以免随后发生硅化反应。然后，可以对各台阶露出的横向表面进行硅化处理。例如，可以淀积金属如NiPt，并进行退火，使得淀积的金属与各台阶的横向表面处的半导体材料(例如，Si)发生硅化反应，从而生成导电的金属硅化物1051如NiPtSi。之后，可以去除未反应的金属。For example, as shown in Figure 15, after forming the step structure in the contact area as described above in conjunction with Figures 7(a) to 9(b), the isolation layer and spacers 1035 can be removed by selective etching such as RIE, to expose the surface of each step in the contact area. Dielectric spacers 1049 may be formed on the vertical surfaces of each step through a spacer forming process to shield these vertical surfaces from subsequent silicide reactions. The exposed lateral surfaces of each step can then be siliconized. For example, a metal such as NiPt may be deposited and annealed such that the deposited metal reacts with the semiconductor material (eg, Si) at the lateral surfaces of each step to undergo a silicide reaction to generate a conductive metal suicide 1051 such as NiPtSi. Afterwards, unreacted metal can be removed.
在所示出的示例中，栅导体层1027例如是多晶硅，因此其顶端也可以发生硅化反应从而被硅化物覆盖。在栅导体层1027是金属栅的情况下，可以先在器件区上形成保护层(例如，氮化物)以覆盖栅堆叠再进行硅化处理。于是，可以避免栅导体层1027在硅化处理工艺中去除金属时被刻蚀损坏。In the example shown, the gate conductor layer 1027 is, for example, polysilicon, so its top end may also undergo a silicide reaction and be covered by silicide. In the case where the gate conductor layer 1027 is a metal gate, a protective layer (eg, nitride) may be formed on the device area first to cover the gate stack and then the siliconization process is performed. Therefore, the gate conductor layer 1027 can be prevented from being damaged by etching when removing metal during the silicidation process.
之后，可以如上所述形成层间电介质层，并在其中形成接触部1039、1041。在刻蚀用于接触部的孔洞时，可以硅化物1051作为刻蚀停止层。因此，可以更好地控制孔洞的刻蚀深度。Thereafter, an interlayer dielectric layer may be formed as described above, and contacts 1039, 1041 may be formed therein. Silicide 1051 can be used as an etch stop layer when etching holes for contacts. Therefore, the etching depth of the holes can be better controlled.
在以上实施例中，有源区由器件层限定，如同体材料，且因此沟道区形成在体材料中。这种情况下，工艺较为简单。但是，本公开不限于此。In the above embodiments, the active region is defined by the device layer, such as the bulk material, and therefore the channel region is formed in the bulk material. In this case, the process is relatively simple. However, the present disclosure is not limited thereto.
在如以上结合图5所述形成隔离层10231至10235并去除支撑层1019之后，各器件层的侧壁在加工通道T中露出。可以在这些侧壁上例如通过外延生长，形成另外的半导体层，沟道区可以形成在如此形成的半导体层中(在此，各器件层可以称为“基体层”，且各基体层与其侧壁上的半导体层可以一起称为“器件层”，因为它们一起限定了器件层级)。半导体层可以沿加工通道T的侧壁形成，从而具有环状纳米片的形状。通过选择该半导体层的材料和/或厚度等特性，可以改进器件性能。After the isolation layers 10231 to 10235 are formed and the support layer 1019 is removed as described above in connection with FIG. 5 , the sidewalls of each device layer are exposed in the processing channel T. Additional semiconductor layers may be formed on these sidewalls, for example by epitaxial growth, and channel regions may be formed in the semiconductor layers thus formed (herein, each device layer may be referred to as a "base layer", and each base layer with its side The semiconductor layers on the walls may be collectively referred to as "device layers" because together they define the device level). The semiconductor layer may be formed along the sidewalls of the processing channel T to have the shape of a ring-like nanosheet. By selecting properties such as the material and/or thickness of the semiconductor layer, device performance can be improved.
为确保各器件层的侧壁上生长的半导体层之间的隔离，这些半导体层可以形成在隔离层之间。为此，如图16所示，可以通过选择性刻蚀，使各器件层10051至10054在横向上凹进一定程度。各器件层10051至10054在各横向方向上可以凹进实质上相同的深度，并因此可以导致在各对竖直方向上相邻的隔离层之间以加工通道T为中心的环形间隙。各器件层在刻蚀之后侧壁在竖直方向上仍然可以实质上共面。To ensure isolation between the semiconductor layers grown on the sidewalls of each device layer, these semiconductor layers may be formed between isolation layers. To this end, as shown in FIG. 16 , each device layer 10051 to 10054 can be recessed to a certain extent in the lateral direction through selective etching. Each device layer 10051 to 10054 may be recessed to substantially the same depth in each lateral direction, and thus may result in an annular gap centered on the processing channel T between each pair of vertically adjacent isolation layers. After etching, the sidewalls of each device layer can still be substantially coplanar in the vertical direction.
然后，如图17所示，可以通过例如选择性外延生长，在各器件层10051至10054的露出表面上分别形成另一半导体层1053。半导体层1053可以填充在上述环形间隙中，并可以包括各种合适的半导体材料如Si。可以选择半导体层1053的材料和/或厚度，以改进器件性能。例如，半导体层1053可以包括不同于器件层(在该示例中，均为Si)的材料，如Ge、IV-IV族化合物半导体如SiGe、III-V族化合物半导体等，以改进载流子迁移率或者降低漏电流。竖直方向上相邻的半导体层1053之间可以通过隔离层彼此隔离。Then, as shown in FIG. 17 , another semiconductor layer 1053 may be formed on the exposed surface of each device layer 10051 to 10054 by, for example, selective epitaxial growth. The semiconductor layer 1053 may be filled in the above-mentioned annular gap, and may include various suitable semiconductor materials such as Si. The material and/or thickness of semiconductor layer 1053 may be selected to improve device performance. For example, the semiconductor layer 1053 may include a different material than the device layer (both Si in this example), such as Ge, a group IV-IV compound semiconductor such as SiGe, a group III-V compound semiconductor, etc., to improve carrier migration rate or reduce leakage current. Adjacent semiconductor layers 1053 in the vertical direction may be isolated from each other by isolation layers.
之后，如图18所示，可以进行退火处理，以将隔离层10231至10235中的掺杂剂驱入到半导体层1053中，以在其上下两端形成源/漏掺杂。关于源/漏掺杂，可以参见以上结合图6的描述。Afterwards, as shown in FIG. 18 , an annealing process may be performed to drive the dopants in the isolation layers 10231 to 10235 into the semiconductor layer 1053 to form source/drain doping at its upper and lower ends. Regarding source/drain doping, please refer to the above description in conjunction with FIG. 6 .
根据另一实施例，还可以形成SSRW。例如，在退火处理时，各器件层10051至10054中的掺杂剂也可以横向扩散到与之相邻的半导体层1053中。如上所述，在竖直方向上，源自隔离层10231至10235的掺杂剂由于扩散深度的原因而实质上并未影响半导体层1053的中部，因此半导体层1053的中部的掺杂分布主要由源自各器件层10051至10054的横向扩散来决定，并可以限定沟道区。可以控制退火工艺的处理条件如退火时间等，使得在半导体层1053的中部，在横向上半导体层1053远离相应器件层一侧的侧壁(及其附近)处的掺杂浓度低于邻近相应器件层一侧的侧壁(及其附近)的掺杂浓度。于是，可以形成SSRW，并可以获得良好的短沟道效应控制。According to another embodiment, SSRW may also be formed. For example, during the annealing process, the dopants in each device layer 10051 to 10054 may also be laterally diffused into the adjacent semiconductor layer 1053 . As mentioned above, in the vertical direction, the dopants originating from the isolation layers 10231 to 10235 do not substantially affect the middle part of the semiconductor layer 1053 due to the diffusion depth, so the doping distribution of the middle part of the semiconductor layer 1053 It is primarily determined by lateral diffusion originating from each device layer 10051 to 10054 and may define the channel region. The processing conditions of the annealing process, such as the annealing time, etc., can be controlled so that in the middle of the semiconductor layer 1053, the doping concentration at the sidewall of the semiconductor layer 1053 away from the corresponding device layer (and its vicinity) in the lateral direction is lower than that of the adjacent corresponding device. The doping concentration of the sidewall (and its vicinity) on one side of the layer. Thus, SSRW can be formed, and good short channel effect control can be obtained.
之后，如图19所述，可以在加工通道中形成栅堆叠，并可以如上所述进行后继工艺。这里需要指出的是，在该示例中，示出了在形成栅堆叠之前进行退火处理。或者，如以上结合图6所述，可以在形成栅堆叠之后进行退火处理。Thereafter, as shown in Figure 19, the gate stack can be formed in the processing channel, and subsequent processes can be performed as described above. It should be noted here that in this example, an annealing process is shown before forming the gate stack. Alternatively, as described above in connection with FIG. 6 , an annealing process may be performed after forming the gate stack.
根据本公开实施例的存储器件可以应用于各种电子设备。例如，存储器件可以存储电子设备操作所需的各种程序、应用和数据。电子设备还可以包括与存储器件相配合的处理器。例如，处理器可以通过运行存储器件中存储的程序来操作电子设备。这种电子设备例如智能电话、个人计算机(PC)、平板电脑、人工智能设备、可穿戴设备或移动电源等。The memory device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, storage devices can store various programs, applications, and data required for the operation of electronic devices. The electronic device may also include a processor coupled with the storage device. For example, a processor may operate an electronic device by executing a program stored in a storage device. Such electronic devices include smart phones, personal computers (PCs), tablets, artificial intelligence devices, wearable devices, or mobile power supplies.
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。In the above description, there is no detailed explanation of the technical details such as patterning and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. in desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. In addition, although each embodiment is described separately above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.
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|---|---|---|---|
| CN202110252926.XACN112909010B (en) | 2021-03-08 | 2021-03-08 | NOR type memory device, method of manufacturing the same, and electronic apparatus including the same |
| CN202311286365.0ACN117295339A (en) | 2021-03-08 | 2021-03-08 | NOR type memory device, method of manufacturing the same, and electronic apparatus including the same |
| US18/042,754US20230337428A1 (en) | 2021-03-08 | 2022-02-22 | Nor-type memory device, method of manufacturing nor-type memory device, and electronic apparatus including memory device |
| EP22766147.7AEP4307376A4 (en) | 2021-03-08 | 2022-02-22 | Nor type memory device and manufacturing method therefor, and electronic apparatus comprising memory device |
| PCT/CN2022/077239WO2022188621A1 (en) | 2021-03-08 | 2022-02-22 | Nor type memory device and manufacturing method therefor, and electronic apparatus comprising memory device |
| Application Number | Priority Date | Filing Date | Title |
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| CN202110252926.XACN112909010B (en) | 2021-03-08 | 2021-03-08 | NOR type memory device, method of manufacturing the same, and electronic apparatus including the same |
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| CN202311286365.0ADivisionCN117295339A (en) | 2021-03-08 | 2021-03-08 | NOR type memory device, method of manufacturing the same, and electronic apparatus including the same |
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| CN112909010A CN112909010A (en) | 2021-06-04 |
| CN112909010Btrue CN112909010B (en) | 2023-12-15 |
| Application Number | Title | Priority Date | Filing Date |
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| CN202110252926.XAActiveCN112909010B (en) | 2021-03-08 | 2021-03-08 | NOR type memory device, method of manufacturing the same, and electronic apparatus including the same |
| CN202311286365.0APendingCN117295339A (en) | 2021-03-08 | 2021-03-08 | NOR type memory device, method of manufacturing the same, and electronic apparatus including the same |
| Application Number | Title | Priority Date | Filing Date |
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| CN202311286365.0APendingCN117295339A (en) | 2021-03-08 | 2021-03-08 | NOR type memory device, method of manufacturing the same, and electronic apparatus including the same |
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| EP (1) | EP4307376A4 (en) |
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