CN112865731B - Class D audio amplifier, mixed modulation method thereof and electronic equipment - Google Patents

Abstract

The application discloses D class audio amplifier and mixed modulation method, electronic equipment thereof, D class audio amplifier includes: the pulse width modulation module is used for performing pulse width modulation on the input signal and outputting a first pulse width modulation signal and a second pulse width modulation signal; the pulse width adjusting module is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal in an enabling state and outputting a corresponding first delay signal and a corresponding second delay signal to the driving module; the driving module comprises a differential logic unit and a driving output unit, wherein the differential logic unit is used for carrying out differential operation on input signals in an enabled state and outputting the input signals to the driving output unit; the driving output unit is used for amplifying the power of the output signal of the differential logic unit and outputting a first output signal and a second output signal; and the mode control module is used for outputting the mode control signal according to the input signal of the input signal. The D-class audio amplifier can improve the signal distortion problem.

Description

Class D audio amplifier, mixed modulation method thereof and electronic equipment

Technical Field

The application relates to the technical field of integrated circuits, in particular to a class-D audio amplifier, a mixed modulation method thereof and electronic equipment.

Background

Class D audio amplifiers are a commonly used high efficiency amplifier for amplifying audio signals, and in systems using class D amplifiers, an analog input signal is converted into a series of pulse modulated signals having different pulse widths to drive audio speakers.

The output of the class D audio amplifier is generally full-wave modulated, and usually has two output terminals connected to two ends of the load, respectively, and the two output terminal signals under the static output are both 50% duty ratio square wave signals. Considering that the power consumption is in positive correlation with the output duty ratio when the output voltage is applied to the LC load, the smaller the duty ratio is, the lower the power consumption is under the same condition, and therefore the 50% duty ratio output regulation mode is undoubtedly more power-consuming than the narrow pulse width output regulation mode. Because class D audio amplifier is widely used in electronic audio equipment such as cell-phone, smart audio amplifier, along with portable electronic audio equipment's popularization, also higher and higher to audio power amplifier's consumption requirement, consequently, the mode that reduces output pulse width is also more and more adopted in audio power amplifier.

The narrow pulse width is easy to disappear in the transmission process due to the deviation of the device process in the circuit, and especially under the condition of small signal input, the problems of bottom noise and distortion are easy to be caused when narrow pulse width modulation is adopted.

Therefore, how to keep the total harmonic distortion normal when performing narrow pulse width modulation is a problem to be solved urgently.

Disclosure of Invention

In view of this, the present application provides a class D audio amplifier, a hybrid modulation method thereof, and an electronic device, which ensure that total harmonic distortion is normal.

The technical scheme of the invention provides a D-type audio amplifier, which comprises: the pulse width modulation module is used for performing pulse width modulation on an input signal and outputting a first pulse width modulation signal and a second pulse width modulation signal, wherein the input signal comprises two paths of differential signals; the pulse width adjusting module is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the first output signal and the second output signal output to a load in an enabling state, and outputting the corresponding first delay signal and the second delay signal to the driving module; in a non-enabled state, maintaining the second pulse width modulation signal and the first pulse width modulation signal unchanged, and outputting the second pulse width modulation signal and the first pulse width modulation signal to a driving module; the driving module comprises a differential logic unit and a driving output unit, wherein the differential logic unit is used for carrying out differential operation on input signals in an enabled state, outputting two paths of differential operation signals to the driving output unit, and keeping the waveform of the input signals unchanged and outputting the input signals to the driving output unit in a non-enabled state; the driving output unit is used for performing power amplification on the output signal of the differential logic unit and outputting the first output signal and the second output signal; and the mode control module is used for outputting a mode control signal to the pulse width adjustment module and the driving module according to the input amplitude of the input signal so as to control the working states of the pulse width adjustment module and the differential logic unit.

Optionally, the mode control module is configured to output a corresponding mode control signal when the amplitudes of the two paths of signals in the input signal are both smaller than a first threshold, and control the differential logic unit and the pulse width adjustment module to be in an enabled state; and when the amplitude of at least one path of signal in the input signals is larger than or equal to a first threshold value, outputting a corresponding mode control signal, and controlling the differential logic unit and the pulse width adjusting module to be in a non-enabled state.

Optionally, the mode control module includes a reference generation unit and a comparison unit; the reference generating unit is used for generating a first reference voltage corresponding to the first threshold value; the comparison unit is used for comparing the input signal with the first reference voltage and outputting a corresponding mode control signal according to a comparison result.

Optionally, the comparing unit includes a first comparator, a second comparator, a first nor gate, a first not gate, and a third not gate; two negative input ends of the first comparator and the second comparator are simultaneously connected to a first reference voltage, two positive input ends of the first comparator and the second comparator are respectively connected to two differential signals in the input signals, output ends of the first comparator and the second comparator are respectively connected to the input end of the first NOR gate, and the output end of the first NOR gate is sequentially connected with the first NOR gate and the second NOR gate.

Optionally, the reference generating unit is further configured to generate a first offset reference voltage corresponding to the first threshold, where the first offset reference voltage is greater than the first reference voltage; the comparison unit is used for controlling the subsequent input signals to be compared with the first reference voltage when the amplitude of at least one path of signals in the input signals is gradually reduced from being larger than the first offset reference voltage, and controlling the subsequent input signals to be compared with the first offset reference voltage when the amplitude of at least one path of signals in the input signals is gradually increased from being smaller than the first reference voltage.

Optionally, the comparing unit further includes a first transmission gate and a second transmission gate; the input end of the first transmission gate is used for being connected with the first reference voltage, the control end of the first transmission gate is connected to the output end of the first not gate, and the inverted control end of the first transmission gate is connected to the output end of the first not gate; the input end of the second transmission gate is used for being connected to a first offset reference voltage, the control end of the second transmission gate is connected to the output end of the first NOR gate, and the inverted control end of the second transmission gate is connected to the output end of the first NOR gate; two negative input ends of the first comparator and the second comparator are connected to the output ends of the first transmission gate and the second transmission gate in common; wherein the first offset reference voltage corresponds to the first threshold and is greater than the first reference voltage.

Optionally, the mode control module is further configured to output a corresponding mode control signal when the amplitudes of the two paths of signals in the input signal are both greater than a second threshold, so as to control the differential logic unit and the pulse width adjustment module to be in an enable state; the second threshold is greater than the first threshold.

Optionally, the mode control module includes a reference generation unit and a comparison unit; the reference generating unit is used for generating a first reference voltage corresponding to the first threshold value and a second reference voltage corresponding to a second threshold value; the comparison unit is used for comparing the input signal with the first reference voltage and the second reference voltage and outputting a corresponding mode control signal according to a comparison result.

Optionally, the reference generating unit is further configured to generate a second offset reference voltage corresponding to a second threshold, where the second offset reference voltage is greater than the second reference voltage; the comparison unit is used for controlling the subsequent input signal to be compared with the second reference voltage when the amplitude of at least one path of signal in the input signals is gradually reduced from being larger than the second offset reference voltage, and controlling the subsequent input signal to be compared with the second offset reference voltage when the amplitude of at least one path of signal in the input signals is gradually increased from being smaller than the second reference voltage.

Optionally, the comparing unit further includes a first comparing path, a second comparing path, and an exclusive nor circuit; the first comparison path includes: the two negative input ends of the first comparator and the second comparator are simultaneously connected to a first reference voltage, the two positive input ends of the first comparator and the second comparator are respectively connected to two differential signals in the input signals, the output ends of the first comparator and the second comparator are connected to the input end of the first NOR gate, and the output end of the first NOR gate is sequentially connected with the first NOR gate and the third NOR gate; the second compare path includes: the two positive input ends of the third comparator and the fourth comparator are simultaneously connected to a second reference voltage, the two negative input ends of the third comparator and the fourth comparator are respectively connected to two differential signals in the input signals, the output ends of the third comparator and the fourth comparator are both connected to the input end of the second NOR gate, and the output end of the second NOR gate is connected to the input end of the second NOR gate; the output ends of the first NOT gate and the second NOT gate are connected to the input end of the XOR not circuit, and the output end of the XOR not circuit is used for outputting the mode control signal.

Optionally, the first comparison path of the comparison unit further includes a first transmission gate and a second transmission gate, an input end of the first transmission gate is used for connecting the first reference voltage, a control end is connected to an output end of the first not gate, and an inverted control end is connected to an output end of the first nor gate; the input end of the second transmission gate is used for being connected to a first offset reference voltage, the control end of the second transmission gate is connected to the output end of the first NOR gate, and the inverted control end of the second transmission gate is connected to the output end of the first NOR gate; two negative input ends of the first comparator and the second comparator are connected to the output ends of the first transmission gate and the second transmission gate in common; the second comparison path further comprises a third transmission gate and a fourth transmission gate, wherein the input end of the third transmission gate is used for being connected to the second reference voltage, the control end of the third transmission gate is connected to the output end of the second NOR gate, and the inverted control end of the third transmission gate is connected to the output end of the second NOR gate; the input end of the fourth transmission gate is used for being connected to a second offset reference voltage, the control end of the fourth transmission gate is connected to the output end of the second not gate, and the inverted control end of the fourth transmission gate is connected to the output end of the second not gate; wherein the first offset reference voltage corresponds to a first threshold and is greater than the first reference voltage; the second offset reference voltage corresponds to a second threshold, and the second offset reference voltage is greater than the second reference voltage.

Optionally, the pulse width adjusting module includes: the pulse width detection unit is used for detecting whether pulses exist in the first output signal and the second output signal or not and outputting corresponding pulse width control signals; and the delay control unit is controlled by the mode control signal to enter an enabling state or not, and is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the pulse width control signal in the enabling state and directly outputting the received second pulse width modulation signal to the driving module in the non-enabling state.

The invention also provides a mixed modulation method of the D-type audio amplifier, which comprises the following steps: performing pulse width modulation on an input signal to generate a first pulse width modulation signal and a second pulse width modulation signal; judging whether to adjust the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the amplitude of the input signal; if so, adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to a first output signal and a second output signal output to a load to form a corresponding first delay signal and a second delay signal; performing differential operation on the first delay signal and the second delay signal to generate two paths of differential operation signals, and then performing power amplification on the two paths of differential operation signals to generate a first output signal and a second output signal which are output to a load, wherein the pulse widths of the first output signal and the second output signal are changed along with the relative delay amount; if not, keeping the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal unchanged, carrying out power amplification on the first pulse width modulation signal and the second pulse width modulation signal, and generating a first output signal and a second output signal which are output to a load.

Optionally, if the amplitudes of the two paths of signals in the input signal are both smaller than a first threshold, adjusting a relative delay amount between the second pwm signal and the first pwm signal; and if the amplitude of at least one path of signals in the input signals is larger than the first threshold value, keeping the relative delay amount unchanged.

Optionally, the method for determining whether to adjust the relative delay amount between the second pwm signal and the first pwm signal further includes: providing a first reference voltage corresponding to the first threshold, comparing the input signal with the first reference voltage; when the amplitudes of two paths of signals in the input signals are smaller than the first reference voltage, adjusting the relative delay amount; and when the amplitude of at least one path of signals in the input signals is greater than or equal to the first reference voltage, keeping the relative delay constant.

Optionally, the method for determining whether to adjust the relative delay amount between the second pwm signal and the first pwm signal further includes: providing a first offset reference voltage corresponding to the first threshold, the first offset reference voltage being greater than the first reference voltage; when the amplitude of at least one of the input signals is gradually reduced from being larger than the first offset reference voltage, the subsequent input signal is controlled to be compared with the first reference voltage, and when the amplitude of at least one of the input signals is gradually increased from being smaller than the first reference voltage, the subsequent input signal is controlled to be compared with the first offset reference voltage.

Optionally, the method for determining whether to adjust the relative delay amount further includes: and when the amplitudes of the two paths of signals in the input signals are larger than the second threshold value, adjusting the relative delay amount.

Optionally, the method for determining whether to adjust the relative delay amount includes: providing a first reference voltage corresponding to the first threshold value and a second reference voltage corresponding to a second threshold value; comparing the input signal to the first and second reference voltages; when the amplitudes of two paths of signals in the input signals are smaller than the first reference voltage, adjusting the relative delay amount; when the amplitude of at least one path of signals in the input signals is greater than or equal to the first reference voltage and smaller than the second reference voltage, keeping the relative delay amount unchanged; and when the amplitudes of the two paths of signals in the input signals are both larger than or equal to the second reference voltage, adjusting the relative delay amount.

Optionally, the method further includes: providing a first offset reference voltage corresponding to the first threshold, a second offset reference voltage corresponding to the second threshold, the first offset reference voltage being greater than the first reference voltage, the second offset reference voltage being greater than the second reference voltage; when the amplitude of at least one path of signals in the input signals is gradually reduced from being larger than the first offset reference voltage, controlling the subsequent input signals to be compared with the first reference voltage; when the amplitude of at least one path of signals in the input signals is gradually increased from being smaller than the first reference voltage, controlling the comparison between the subsequent input signals and the first offset reference voltage; and when the amplitude of at least one of the input signals is gradually increased from being smaller than the second reference voltage, the subsequent input signal is controlled to be compared with the second offset reference voltage.

Optionally, the method for adjusting the relative delay amount between the second pwm signal and the first pwm signal according to the first output signal and the second output signal output to the load includes: performing level conversion on the first output signal and the second output signal to form a first conversion signal and a second conversion signal; detecting whether the first conversion signal and the second conversion signal have pulses or not and outputting corresponding pulse width control signals; and adjusting the relative delay amount according to the pulse width control signal.

Optionally, the method for adjusting the relative delay amount further includes: and delaying the first pulse width modulation signal by a fixed amount to form the first delayed signal.

The technical solution of the present invention also provides an electronic device, including: a class D audio amplifier as claimed in any preceding claim.

The class D audio amplifier switches the pulse width modulation mode according to the amplitude of the input signal, performs narrow pulse width modulation within a proper amplitude range of the input signal, and improves the signal distortion problem.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a class D audio amplifier according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a differential logic unit of a class D audio amplifier according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a pulse width detection unit of a class D audio amplifier according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a delay control unit of a class D audio amplifier according to an embodiment of the present application;

FIG. 5a is a schematic structural diagram of a mode control module according to an embodiment of the present application;

FIG. 5b is a schematic diagram of a comparing unit of a mode control module according to an embodiment of the present application;

FIG. 6a is a schematic structural diagram of a mode control module according to an embodiment of the present application;

FIG. 6b is a schematic diagram of a comparing unit of a mode control module according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a comparing unit of a mode control module according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a comparing unit of a mode control module according to an embodiment of the present application;

FIGS. 9a and 9b are schematic signal waveforms of the output signal of the class D audio amplifier in the static state according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a class D audio amplifier according to an embodiment of the present application;

FIG. 11 is a signal waveform diagram illustrating the output signal of the class D audio amplifier in the static condition according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a fixed delay unit of a class D audio amplifier according to an embodiment of the present application;

fig. 13 is a flowchart illustrating an adaptive pulse width adjusting method according to an embodiment of the present application.

Detailed Description

As described in the prior art, the prior art reduces power consumption by simply reducing the pulse width during the static operation, which causes problems of noise reduction and distortion, and particularly, in the case of a small signal input, the pulse width is inherently small and is easily distorted, and if narrow pulse width modulation is performed, further reduction of the pulse width causes greater signal distortion. Therefore, the inventor provides a new class D audio amplifier and a pulse width adjusting method thereof, which can perform adaptive narrow pulse width modulation in a proper power range according to the amplitude of an output signal output to a load, reduce the pulse width of the output signal as much as possible, and avoid introducing additional problems of noise floor, distortion and the like.

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.

Fig. 1 is a schematic structural diagram of a class D audio amplifier according to an embodiment of the present invention.

In this embodiment, the class D audio amplifier includes: a pulsewidth modulation module 110, adriving module 120, a pulsewidth adjustment module 130, and amode control module 140.

The pulsewidth modulation module 110 is configured to perform pulse width modulation on an input signal and output a first pulse width modulation signal and a second pulse width modulation signal. The input signal includes two analog differential signals VOP0 and VON0.

The pulsewidth modulation module 110 comprises an operational amplifier AMP and a capacitor C₁ ～C₆ Resistance R₁ ～R₈ And the comparators comp1 and comp2 are coupled to form an integrator. The operational amplifier AMP is used for amplifying the signal via a resistor R₁ And a resistance R₂ A pair of differential signals VOP0 and VON0 coupled to the two input terminals respectively perform an integration operation, and output two amplified signals. A T-type differential circuit is connected between the positive input end and the positive output end of the operational amplifier AMP, and comprises a capacitor C₁ 、C₃ And a resistance R₃ ，C₁ And C₃ A resistor R connected in series between the positive input end and the positive output end of the operational amplifier AMP₃ Is connected to C₁ And C₃ Between the connection point of (a) and the ground. A T-shaped differential circuit is also connected between the negative input end and the negative output end of the operational amplifier AMP, and comprises a capacitor C₂ 、C₄ And a resistance R₄ ，C₂ And C₄ A resistor R connected in series between the positive input end and the positive output end of the operational amplifier AMP₄ Is connected to C₂ And C₄ Between the connection point of (a) and the ground. A feedback loop structure is respectively formed between the two input ends of the operational amplifier AMP and the two output ends of the class D audio amplifier, and the feedback loop structures are respectively connected with feedback resistors R5-R8 and a feedback capacitor C₅ And C₆ Feedback resistance R₅ 、R₆ And a feedback capacitor C₅ Forming a T-shaped feedback circuit, a feedback resistor R₇ 、R₈ And a feedback capacitor C₆ And the T-shaped feedback circuit has a filtering function and is used for inhibiting the influence on the input end when the modulated high-frequency square wave signal is fed back to the operational amplifier AMP through the feedback loop. The feedback loop structure may improve the quality of the output signal, but is not a necessary structure.

Thepwm module 110 may further include a preceding stage amplifying module, which includes an amplifier, and is configured to differentially amplify an input preceding stage audio analog signal, such as a differential signal, and output the analog differential signals VOP0 and VON0, and then perform an integration operation through an operational amplifier AMP.

The comparator comp1 and the comparator comp2 are respectively configured to modulate two amplified signals output by the operational amplifier AMP, compare the two amplified signals with the modulation signal generated by themodulation signal generator 111, and output a first pulse width modulation signal VO1 and a second pulse width modulation signal VO2. The modulation signal is typically a triangular wave, and a triangular wave of a specific frequency and level value may be generated as the modulation signal by themodulation signal generator 111. When the level of the amplified signal exceeds the signal level of the triangular wave, the comparator outputs a high level; when the level of the amplified signal is lower than the signal level of the triangular wave, the comparator outputs a low level, so that the first pulse width modulation signal VO1 and the second pulse width modulation signal VO2 which are output are both modulated square wave signals with a certain duty ratio. In other embodiments, the modulation signal may also be a waveform signal with a periodic rising and falling slope, such as a sawtooth wave or a sinusoidal half wave. The frequency of the modulation signal is usually 400KHz to 800KHz, which is much higher than the frequency of the signal to be modulated.

The pulsewidth adjusting module 130 is configured to control a relative delay amount between the second pulse width modulation signal VO2 and the first pulse width modulation signal VO1 according to a first output signal VOP and a second output signal VON output to a load in an enable state, so as to form a second delay signal VO3. In this embodiment, the pulsewidth adjustment module 130 only delays the second pulse width modulation signal VO2 by a delay amount T to form a second delayed signal VO3; if the delay amount of the first pwm signal VO1 is 0, the relative delay amount between VO3 and VO1 is the delay amount T. In the non-enabled state, the pulsewidth adjustment module 130 directly outputs the second pulse width modulation signal VO2 to thedriving module 120 without adjusting the relative delay amount.

Thedriving module 120 is coupled to the output terminals of the comparators comp1 and comp2, and is at least used for performing power amplification on the first pulse width modulation signal VO1 and the second delay signal VO3 to generate a first output signal VOP and a second output signal VON for applying to a load to drive the load. The pulse widths of the first output signal VOP and the second output signal VON vary with the relative delay amount between the second delayed signal VO3 and the first pulse width modulatedsignal VO 1.

In this embodiment, thedriving module 120 includes adifferential logic unit 121 and drivingoutput units 122a and 122b; thedifferential logic unit 121 is configured to perform a differential operation, such as a NAND operation, on the first pulse-width modulation signal VO1 and the second delay signal VO3 in an enabled state, and output two differential operation signals GTA and GTB; the differential operation signal GTA outputs the first output signal VOP through the drivingoutput unit 122a, and the differential operation signal GTB outputs the second output signal VON through the drivingoutput unit 122b. Thedifferential logic unit 121 is configured to directly output the first pulse width modulation signal VO1 and the second delay signal VO3 to the drivingoutput units 122a and 122b in an disabled state, and perform power amplification and then output the signals.

The pulsewidth adjusting module 130 is configured to delay the second pulse modulation signal VO2 to form a second delayed signal VO3 in an enabled state, so as to adjust pulse widths of the first output signal VOP and the second output signal VON by adjusting a delay amount. If the pulsewidth adjustment module 130 detects that neither the first output signal VOP nor the second output signal VON has pulses, that is, both signals are at low level, the pulsewidth adjustment module 130 is configured to increase the delay amount of the second delayed signal VO3 to increase the pulse widths of the first output signal VOP and the second output signal VON until one of the signals has pulses; if at least one of the two signals is detected to be high level, that is, any one signal has a pulse, reducing the delay amount of the second delay signal VO3, and reducing the pulse width of the first output signal VOP and the second output signal VON; therefore, the pulse widths of the first output signal VOP and the second output signal VON are always limited to be close to the minimum pulse width controlled by the minimum delay amount, so that the first output signal VOP and the second output signal VON are always ensured to have pulse output, the problems of bottom noise and distortion are reduced, the pulse width can be reduced as much as possible, and the power consumption is reduced.

In addition, in this embodiment, the pulsewidth adjusting module 130 detects the first output signal VOP and the second output signal VON which are finally output to the load end by the class D audio amplifier to perform pulse width modulation, and the finally modulated output signals are not lost or eliminated by the dead zone of the output driving module before being applied to the load, so that the output pulse widths of the first output signal VOP and the second output signal VON can be reduced as much as possible without worrying about the occurrence of no output phenomenon due to the small pulse width.

In this embodiment, the pulsewidth adjusting module 130 specifically includes alevel converting unit 133, a pulsewidth detecting unit 131, and adelay control unit 132.

Thelevel shifting unit 133 is coupled between the pulsewidth detecting unit 131 and the output terminal of thedriving module 120, and is configured to perform level shifting on the first output signal VOP and the second output signal VON. Since the first output signal VOP and the second output signal VON are directly supplied to the load, a typical level range is in a high voltage domain range, for example, 6.5V to 12.5V; the pulsewidth detection unit 131 adopts a logic circuit, and generally operates in a low voltage range, for example, 2.8V to 5.5V. Thelevel conversion unit 133 converts the first output signal VOP and the second output signal VON from a high-voltage domain (PVDD) to a low-voltage domain (VDD) to form a first converted signal and a second converted signal. Thelevel shift unit 133 may input the PVDD domain voltage to the drain terminal of the isolation tube through the ESD resistor through the high voltage isolation tube, and clamp the voltage to the VDD domain to implement level shift. Those skilled in the art can select an appropriate level shift circuit to implement voltage shifting in a specific level range according to the requirement. The first converted signal corresponds to the first output signal VOP and the second converted signal corresponds to the second output signal VON.

The pulsewidth detection unit 131 is configured to detect whether the level-converted first converted signal and the level-converted second converted signal have pulses, and output a corresponding control signal according to a detection result.

Thedelay control unit 132 is coupled to the pulsewidth detection unit 131, and is configured to adjust a delay amount of the second delay signal VO3 according to the control signal. Thedelay control unit 132 includes a charging structure, controls a charging and discharging process of the charging structure through a second pwm signal VO2, and outputs a delayed second delay signal VO3 after the charging and discharging are completed. The control signal may control the charging time within the charging structure, thereby controlling the delay amount of the second delay signal VO3, the faster the charging, the smaller the delay amount. The charging structure at least comprises a charging capacitor structure and a charging current source, the charging time can be adjusted by controlling the size of the charging current or controlling the size of the charging capacitor, and then the delay amount is adjusted, specifically, the negative correlation between the delay amount and the size of the charging current is positive correlation with the size of the charging capacitor.

In another embodiment of the present invention, the drivingoutput units 122a and 122b respectively include one or more stages of power buffers, and the pulsewidth adjustment module 130 may also determine whether the first output signal VOP and the second output signal VON have pulses by detecting a signal output from any stage of buffer in the drivingoutput units 122a and 122b. Since the drivingoutput unit 122a and the drivingoutput unit 122b mainly amplify the power of the signal without changing the waveform of the signal, the signals output by each stage of buffers in the drivingoutput unit 122a and the drivingoutput unit 122b can also accurately reflect the pulse waveforms of the first output signal VOP and the second output signal VON, and the level ranges of the drivingoutput unit 122a and the drivingoutput unit 122b are low, so that the level conversion by thelevel conversion unit 133 is not required for direct detection, and the circuit structure of the pulsewidth adjustment module 130 can be simplified.

Themode control module 140 is connected to the pulsewidth adjustment module 130 and thedriving module 120, and the input ends of the two differential signals VOP0 and VOPN of the input signal, and is configured to output a mode control signal EN-HWM to the pulsewidth adjustment module 130 and thedriving module 120 according to the magnitude of the input signal. Themode control module 140 detects the input power by detecting the signal amplitude of the input signal, and the larger the input signal amplitude is, the larger the input power is. The signal amplitude is the signal voltage value.

Specifically, the pulsewidth adjusting module 130 is connected to thedifferential logic unit 121 of thedriving module 120, and is configured to control an enabling state of thedifferential logic unit 121. When the mode control signal EN-HWM controls thedifferential logic unit 121 to enter the enabled state, thedifferential logic unit 121 performs differential operation on the input signal and outputs the differential signal to the drivingoutput units 122a and 122b; when the mode control signal EN-HWM controls thedifferential logic unit 121 to enter the disabled state, thedifferential logic unit 121 does not perform differential operation any more, and directly outputs the received signal to the drivingoutput units 122a and 122b.

Themode control module 140 is connected to thedelay control unit 132 of the pulsewidth adjustment module 130, and is configured to output a mode control signal EN-HWM to control an enable state of thedelay control unit 132. When the mode control signal EN-HWM controls thedelay control unit 132 to enter an enabled state, thedelay control unit 132 delays the input second pwm signal VO2 and outputs the delayed second pwm signal VO2 to thedriving module 120; when the mode control signal EN-HWM controls thedelay control unit 132 to enter the inactive state, thedelay control unit 132 does not perform delay control on the second pwm signal VO2 any more, keeps the timing unchanged, and outputs the timing unchanged to thedriving module 120.

In this embodiment, when the mode control signal EN-HWM is at a high level, it corresponds to thedifferential logic unit 121 and thedelay control unit 132 entering an enabled state; when the mode control signal EN-HWM is low, it corresponds to thedifferential logic unit 121 and thedelay control unit 132 entering a disable state. In other embodiments, the control logic may also be adjusted according to circuit requirements, for example, when the mode control signal EN-HWM is low, corresponding to an enabled state; the mode control signal EN-HWM is high, corresponding to a non-enabled state.

Themode control module 140 outputs a corresponding mode control signal EN-HWM according to the magnitude of the input signal, so as to switch the switching mode. Specifically, when the amplitudes of the two paths of signals in the input signal are both smaller than the first threshold, themode control module 140 outputs a high-level mode control signal EN-HWM to control thedifferential logic unit 121 and thedelay control unit 132 to enter an enable state, and performs narrow pulse width modulation, so that the pulse widths of the output first output signal VOP and the output second output signal VON are smaller. Generally, the amplitudes of two paths of signals in the input signals are smaller than a first threshold value, the input signals are equal to or close to 0 correspondingly, the input signals are in a static working state, the pulse width of the output signals can be reduced as much as possible through narrow pulse width modulation, and power consumption is reduced.

When the amplitude of at least one path of input signals is greater than or equal to the first threshold, themode control module 140 outputs a low-level mode control signal EN-HWM to control thedifferential logic unit 121 and thedelay control unit 132 to enter an disable state, the pulse widths of the first pulse width modulation signal VO1 and the second pulse width modulation signal VO2 are not adjusted, and the pulse widths of the first output signal VOP and the second output signal VON are increased relative to the narrow pulse width modulation mode to avoid signal distortion.

In some embodiments, themode control module 140 may further control thedifferential logic unit 121 and thedelay control unit 132 to enter an enable state and switch to a narrow pulse width modulation mode when the input signal is greater than the second threshold. When the input signal is larger than the second threshold, the input signal belongs to large signal input, the pulse width of the output signal is reduced, signal distortion is not generated generally, and power consumption in large signal input can be further reduced.

Themode control module 140 outputs a corresponding mode control signal EN-HWM according to the amplitude of the input signal, and can dynamically switch into or out of the narrow pulse width modulation mode in real time according to the continuous change of the input signal, so that the whole circuit can perform narrow pulse width modulation as required, reduce power consumption, and improve the signal distortion problem.

Fig. 2 is a schematic structural diagram of adifferential logic unit 121 according to an embodiment of the present invention.

Thedifferential logic unit 121 is composed of NAND gates NAND21 AND NAND gates NAND22, AND gates AND21 AND 22. Specifically, one input end of the NAND gate NAND21 is used for inputting the first pulse width modulation signal VO1, and the other input end is used for inputting the mode control signal EN-HWM; one input end of the NAND gate NAND22 is used for inputting the second pulse width modulation signal VO2, and the other input end is used for inputting the mode control signal EN-HWM; one input end of the AND gate AND21 is used for inputting a first pulse width modulation signal VO1, the other end of the AND gate AND21 is connected to the output end of the NAND gate NAND22, AND the output end of the AND gate AND21 is used for outputting a differential operation signal GTA; one input end of the AND gate AND22 is used for inputting the second pulse width modulation signal VO2, the other end of the AND gate AND22 is connected to the output end of the NAND gate NAND21, AND the output end of the AND gate AND22 is used for outputting the differential operation signal GTB.

When the mode control signal EN-HWM is at a low level, thedifferential logic unit 121 enters a non-enabled state, the NAND gate NAND21 AND the NAND gate NAND22 both output a high level, the pulse width AND timing of the output signal GTA of the AND gate AND21 are consistent with those of VO1, AND the pulse width AND timing of the output signal GTB of the AND gate AND22 are consistent with those of VO3.

When the mode control signal EN-HWM is at a high level, thedifferential logic unit 121 enters an enabled state, performs differential operation on VO1 and VO3, and outputs differential operation signals GTA and GTB after narrow pulse width modulation.

Fig. 3 is a schematic structural diagram of a pulse width adjusting module according to an embodiment of the invention.

In this embodiment, the pulsewidth detection unit 131 implemented in the pulse width adjustment module includes:operational circuit 1311, addsignal path 1312, and subtractsignal path 1313.

Theoperation circuit 1311 is configured to perform an and operation after performing a non-operation on the first output signal VOP and the second output signal VON respectively. Specifically, thenon-operation circuit 1311 includes an inverter INV2 AND an inverse INV3 respectively connected to two output terminals of thelevel shift unit 133, AND an AND gate AND connected to the inverter INV2 AND the inverter INV 3.

The control signal output by the pulsewidth detection unit 131 includes the subtraction signal and the addition signal.

Theadd signal path 1312 is for outputting an add signal and includes a first D flip-flop DFF₁ And a second D flip-flop DFF₂ SaidFirst D flip-flop DFF₁ And a second D flip-flop DFF₂ The clock signal terminal of (2) receives the clock signal CKL1.

The subtractsignal path 1313 is for outputting a subtract signal, and includes a third D flip-flop DFF₃ And a fourth D flip-flop DFF₄ Said third D flip-flop DFF₃ And a fourth D flip-flop DFF₄ The clock signal terminal of (2) inputs the clock signal CKL2.

The add signal output terminal is coupled to the third D flip-flop DFF through an inverter INV1₃ And said fourth D flip-flop DFF₄ Reset terminal (Reset), third D flip-flop DFF₃ Is connected to the fourth D flip-flop DFF₄ The fourth D flip-flop DFF₄ And the Q terminal of (a) is used as a subtraction signal output terminal.

When at least one of the VOP AND VON outputs a high level, the AND gate AND is connected to the first D flip-flop DFF₁ And a second D flip-flop DFF₂ Outputting a low-level reset signal to enable DFF₁ And DFF₂ Is forced to reset to a low level. AND the AND gate AND outputs a high level when both VOP AND VON are low level, AND the addition signal becomes high level when there is no pulse at both VON AND VOP in two periods ofCLK 1.

Inverter INV1 inverts the added signal and provides it to DFF₃ And DFF₄ When the add signal is high level, i.e. both VON and VOP are low level, the DFF₃ And DFF₄ The reset end is at low level, and the reduction signal is at low level; when at least one of VOP and VON is high level, the added signal is low level and is supplied to DFF via inverter INV1₃ And DFF₄ The reset terminal of (2) provides a high level reset signal, and the down signal goes high when both the up signal and the down signal are low in both periods ofCLK 2.

Clock signal CLK1 is the clock that controls theadd signal path 1312 to output the add signal and clock signal CLK2 is the clock that controls the subtractsignal path 1313 to output the subtract signal. The frequency of CLK1 may be greater than the frequency ofCLK 2.

The frequency of the CKL1 is high, and a high-level adding signal needs to be output in time after the disappearance of the pulse is detected, so that the pulse width is increased in time, the state of disappearance of the pulse for a long time is avoided, and meanwhile, the CKL1 still needs to be out of an audio frequency range, so that the output signal of the pulse adjustment process is prevented from falling into the audio frequency range to generate noise. Since the audio frequency range is 20Hz to 20KHz, the frequency of CLK1 may be set to be greater than 20KHz. Further, to ensure that the large periodic envelope formed by the output does not enter the audio range, CLK1 may be greater than 100kHz.

Since the pulse width does not need to be immediately reduced when a pulse is detected, frequent switching of the addition signal and the subtraction signal can be avoided. While the frequency of CLK2 is also guaranteed to be outside the audio frequency range, the CLK2 frequency may even be less than 20Hz.

Preferably, the frequency of CLK1 is 400kHz and the frequency of CLK2 is 10Hz.

Fig. 4 is a schematic structural diagram of adelay control unit 132 according to an embodiment of the invention.

In this embodiment, thedelay control unit 132 includes: acounting unit 1321, acontrol circuit 1322, and a first selection switch X1.

The input terminal of the first selection switch X1 is used for inputting a second pulse width modulation signal VO2, one output terminal is directly connected to the output terminal of thedelay control unit 132, and the other output terminal is connected to thecontrol circuit 1322. The first selection switch X1 is switched to a conduction path by the mode control signal EN-HWM. In this embodiment, when the mode control signal EN-HWM is at high level, thedelay control unit 132 is in the enabled state, VO2 is input to thecontrol circuit 1322; when the mode control signal EN-HWM is low, thedelay control unit 132 is disabled, and VO2 is directly output to the VO3 output terminal.

Thecounting unit 1321 is configured to count according to a clock signal, and count once every clock rising edge occurs. In this embodiment, thecounting unit 1321 includes a counter and related electronic devices and circuit structures, and the counter is a binary up-down counter, which can perform both up-down counting and down-down counting. Thecounting unit 1321 is configured to output an n-bit (bit) signal. In one embodiment, thecounting unit 1321 is configured to outputA 3-bit binary coded signal, comprising 000 to 111, can achieve a count from 0 to 8. In other embodiments, thecounting unit 1321 is configured to output n-bit signals, which are implemented from 0 to 2ⁿ Is counted.

Thecounting unit 1321 is configured to change a count value of thecounting unit 1321 according to the control signal, i.e., the add signal and the subtract signal, output by the pulsewidth detection unit 131, and thecontrol circuit 1322 is configured to adjust the delay amount according to the count value. In the control signal, the addition signal is used for increasing the counting value when being in high level, and the subtraction signal is used for reducing the counting value when being in high level.

In this embodiment, thecontrol circuit 1322 includes a chargingcurrent source structure 1322a and a chargingcapacitor structure 1322b. The chargingcurrent source structure 1322a is composed of a current source Ib and a PMOS transistor MP₁ ～MP₄ NMOS transistor MN₁ ～MN₃ And (4) forming. When the mode control signal EN-HWM controls thedelay control unit 132 to be enabled, the second pwm signal VO2 passes through MP₄ And MN₁ An inverter configured to couple to thecharge capacitor structure 1322b; when MP₄ And MN₁ When the inverter outputs high level, the chargingcapacitor structure 1322b is charged; when the inverter outputs a low level, the chargingcapacitor structure 1322b is discharged. The chargingcurrent source structure 1322a charges the chargingcapacitor structure 1322b to form a signal delayed from VO2 and inverted from VO2, and then outputs a second delayed signal VO3 after pulse delay to VO2 through the inverter INV 4.

The current source Ib passes through MP₁ And MP₂ Composed current mirror, and MN₂ And MN₃ The current mirror is provided to the MP₄ And MN₁ An inverter configured to provide a charging current to the chargingcapacitor structure 1322b. The larger the charging current is, the shorter the charging time is, the smaller the delay amount of VO3 relative to VO2 is, and the smaller the pulse widths of VOP and VON are; the smaller the charging current is, the longer the charging time is, the larger the delay amount of VO3 with respect to VO2 is, and the larger the pulse widths of VOP and VON are outputted. In this embodiment, the current source Ib is a fixed biasAnd (4) streaming.

Since the charging time of the capacitor is proportional to the capacitance value and inversely proportional to the charging current, the larger the capacitance value of the chargingcapacitor structure 1322b is, the longer the charging time is, the larger the delay amount of VO3 relative to VO2 is, and the larger the pulse widths of the output VOP and VON are; the smaller the capacitance value is, the shorter the charging time is, the smaller the delay amount of VO3 with respect to VO2 is, and the smaller the pulse widths of the first output signal VOP and the second output signal VON that are finally output to the load are.

In this embodiment, the current source Ib is a constant current. The chargingcapacitor structure 1322b comprises n charging capacitors C connected in parallel₁ ～C_n Respectively through a switch SW₁ ～SW_n Grounded, and the other ends are connected to the PMOS tubes MP₄ And NMOS transistor MN₁ The output terminals of the inverters, i.e., the drains of MP4 and MN1, are formed. The chargingcapacitor structure 1322b further includes an initial capacitor C₀ The initial capacitance C₀ One end is grounded and the other end is connected to the MP₄ And MN₁ Of the substrate. N is an integer of 2 or more.

The capacitance of theentire charging capacitor 1322b includes an adjustable capacitance and a minimum capacitance, and the adjustable capacitance is determined by the charging capacitor C₁ ～C_n Provided is a method. The switch SW₁ ～SW_n Each bit signal of the n-bit signals output by thecounting unit 1321 is controlled. In this embodiment, when the ith bit signal is 0 (low level), the switch SW_i Disconnecting; when the ith bit signal is 1 (high level), the switch SW_i And conducting. Therefore, when the counting unit outputs a signal in which n bits (bit) are all 0, the switch SW₁ ～SW_n All are disconnected, the capacitance value of the chargingcapacitor structure 1322b is the smallest, and is the initial capacitor C₀ The capacity value of (c); when the counting unit outputs a signal with n bits being 1, each switch is turned on, and the capacitance value of the chargingcapacitor structure 1322b is the largest and is C₀ ～C_n Parallel capacitance value of (i.e. C)₀ +C₁ ……+C_n The relative delay amount is maximum; in other embodiments, the corresponding relationship between the signal on each bit and the on/off of the switch may be adjusted, for example, when the ith bit signal is 1,the switch SWi is turned off, and when the ith bit signal is 0, the switch SW_i And conducting.

Can be set by setting C₁ ～C_n The capacitance value of the chargingcapacitor structure 1322b is made larger as the count value of thecounting unit 1321 is gradually increased. In one embodiment, the capacitor C may be caused to charge₁ To C_n In, C_i Its capacitance value is greater than C1+ \8230 \ 8230 ++ C_i-1 And i is an integer of 1 or more.

Initial capacitance C₀ The minimum relative delay amount of the second delayed signal VO3 with respect to the first pulse width modulation signal VO1 is determined. In other embodiments, the initial capacitance C₀ The capacitance value of the capacitor is adjustable, so that the minimum capacitance value is adjusted in a larger range, and the control of the minimum pulse width is realized.

In another embodiment, the chargingcapacitor structure 1322b of thecontrol circuit 1322 may further have a fixed charging capacitance, and the current source Ib in the chargingcurrent source structure 1322a may be a variable current source, and the delay amount is adjusted by adjusting the charging current outputted by the current source Ib. In one embodiment, the current source Ib may include n charging current sources Ib1 to Ibn connected in parallel, and an initial charging current Ib0, where the initial charging current Ib0 is directly grounded, and Ib1 to Ibn are grounded through switches K1 to Kn, respectively, and coupled to the chargingcapacitor structure 1322b, and an n-bit signal output by thecounting unit 1321 controls on and off of each switch Ki, so as to control a magnitude of the charging current output by the chargingcurrent source structure 1322a, and a maximum charging current Imax of the entire charging current structure may be 0+ \8230; ib + Ibn. In one embodiment, ki is turned on when the ith bit signal is 0; when the ith bit signal is 1, ki is turned off. Under the condition that the mode control signal is fixed, when n-bit signals of the counting value are all 0, K1-Kn are conducted, the charging current is maximum, the charging time is minimum, and the delay amount is minimum; when the n-bit signals are all 1, K1-Kn are disconnected, the charging current is minimum, the charging time is longest, and the delay amount is maximum.

In other embodiments, the variable current source Ib and the charging capacitor structure with a variable capacitance value may be simultaneously provided, and the adjustment of the charging time and thus the adjustment of the relative delay amount may be realized by adjusting the charging current and the size of the charging capacitor.

Fig. 5a is a schematic structural diagram of themode control module 140 according to an embodiment of the invention.

In this embodiment, themode control module 140 includes areference generating unit 141 and a comparingunit 142, thereference generating unit 141 generating a first reference voltage Vref1 corresponding to a first threshold value of the magnitude of the amplitude of the input signal; the comparingunit 142 is configured to compare the input signal with the first reference voltage Vref1, and output a corresponding mode control signal EN-HWM according to a comparison result. Thereference generating unit 141 may include a reference generating circuit.

Referring to fig. 5b, a schematic structural diagram of the comparingunit 142 according to an embodiment of the invention is shown.

In this embodiment, the comparingunit 142 includes a first comparing path, and the first comparing path includes: a first comparator CMP41, a second comparator CMP42, and a nor operation circuit.

In this embodiment, the or operation circuit includes a first NOR gate NOR41, and first and third not gates INV41 and INV43. In other embodiments, the nor operation circuit may be implemented by other circuit structures as long as the function of or operation can be satisfied.

The negative input ends of the first comparator CMP41 and the second comparator CMP42 are both connected to a first reference voltage Vref1; a positive input terminal of the first comparator CMP41 is used for connecting a differential signal VOP0 in the input signal, and comparing VOP0 with Vref1; the positive input terminal of the second comparator CMP42 is used for connecting the differential signal VON0 in the input signal, and comparing VON0 with Vref1. The output signals of the first and second comparators CMP41 and CMP42 are NOR-operated by the first NOR gate NOR41, and then sequentially pass through the first and third NOR gates INV41 and INV43, and then the mode control signal EN-HWM is output.

When the amplitudes of both signals in VOP0 and VON0 are smaller than the first reference voltage Vref1, the first comparator CMP41 and the second comparator CMP42 both output a low level, the NOR41 outputs a high level, and EN-HWM is output as a high level through INV4 and INV43, so that thedelay control unit 132 and thedifferential logic unit 121 are controlled to be enabled, and narrow pulse width modulation is performed.

When the amplitude of any one of VOP0 and VON0 is greater than the first reference voltage Vref1, at least one of the output signals of the comparator CMP41 and the comparator CMP42 is at a high level, the NOR41 outputs a low level, and the INV43 outputs an EN-HWM at a low level, so as to control thedelay control unit 132 and thedifferential logic unit 121 to enter an disable state, and no longer perform narrow pulse width modulation.

Referring to fig. 6a, a schematic structural diagram of themode control module 140 according to another embodiment of the present invention is shown.

In this embodiment, themode control module 140 includes areference generation unit 141a and acomparison unit 142a. Thereference generating unit 141a is configured to generate a first reference voltage Vref1 corresponding to a first threshold, and a second reference voltage Vref2 corresponding to a second threshold.

The comparingunit 142a compares the differential signals VON0 and VOP0 in the output signal with the first reference voltage Vref1 and the second reference voltage Vref2, and outputs a corresponding mode control signal EN-HWM according to a comparison result. The first threshold is smaller than the second threshold, and the corresponding first reference voltage Vref1 is smaller than the second reference voltage Vref2.

Referring to fig. 6b, a specific circuit structure diagram of the comparingunit 142a in fig. 6a is shown.

In this embodiment, on the basis of the first comparison path compared with the first reference voltage Vref1 shown in fig. 5b, a second comparison path compared with the second reference voltage Vref2 is further included, and specifically, the second comparison path includes: a third comparator CMP43, a fourth comparator CMP44, and a nor operation circuit. The NOR operation circuit comprises a second NOR gate NOR42 and a second NOR gate INV42 which are connected in sequence. In other embodiments, the nor operation circuit may have other circuit configurations as long as the nor operation function is satisfied.

The positive input terminals of the third comparator CMP43 and the fourth comparator CMP44 are both connected to a second reference voltage Vref2; the negative input terminal of the third comparator CMP43 is used for connecting the differential signal VOP0 in the input signal, and comparing VOP0 with Vref2; the negative input of the fourth comparator CMP44 is used to connect the differential signal VON0 in the input signal for comparing VON0 with Vref2. The output signals of the third comparator CMP43 and the fourth comparator CMP44 are NOR-operated by the second NOR gate NOR42, and then output the comparison result of the second comparison path by the second NOR gate INV42.

The comparingunit 142a further includes an exclusive or circuit including an exclusive or gate XOR41 and a fourth not gate INV44, for performing an exclusive or operation on the signals output by the third not gate INV43 and the second not gate INV42. The output signals of the third and second not gates INV43 and INV42 sequentially pass through the exclusive or gate XOR43 and the fourth not gate INV44, and output the mode control signal EN-HWM.

When VON0 and VOP0 are both less than Vref1, the first comparator CMP41 and the second comparator CMP42 both output a low level, NOR41 outputs a high level, and INV43 outputs a high level; the third comparator CMP43 and the fourth comparator CMP43 both output a high level, the NOR42 outputs a low level, and the INV42 outputs a high level; therefore, the XOR gate XOR41 outputs a low level, and the mode control signal EN-HWM output by the fourth not gate INV44 is a high level, controlling thedelay control unit 132 and thedifferential logic unit 121 to be enabled.

When at least one of the signals VON0 and VOP0 is greater than Vref1 and at least one of the signals is less than Vref2, at least one of the first comparator CMP41 and the second comparator CMP42 outputs a high level, the NOR41 outputs a low level, and the INV43 outputs a low level; at least one of the third comparator CMP43 and the fourth comparator CMP43 outputs a high level, the NOR42 outputs a low level, and the INV42 outputs a high level; therefore, the XOR gate XOR41 outputs a high level, and the mode control signal EN-HWM output by the fourth not gate INV44 is a low level, controlling thedelay control unit 132 and thedifferential logic unit 121 to be disabled.

When both of VON0 and VOP0 are greater than Vref2, the first comparator CMP41 and the second comparator CMP42 both output a high level, the NOR41 outputs a low level, and the INV43 outputs a low level; the third comparator CMP43 and the fourth comparator CMP43 each output a low level, the NOR42 outputs a high level, and the INV42 outputs a low level; therefore, the XOR gate XOR41 outputs a low level, and the mode control signal EN-HWM output by the fourth not gate INV44 is a high level, controlling thedelay control unit 132 and thedifferential logic unit 121 to be enabled.

Because the amplitude of the input signal swings on both sides of the first reference voltage and the second reference voltage, the output lowest-delay control signal EN-HWM is easy to switch high and low levels frequently, so that the circuit state is switched too frequently, and the stability is reduced. To solve this problem, embodiments of the present invention further provide another comparison unit capable of avoiding frequent switching of the minimum relative delay amount.

Fig. 7 is a schematic structural diagram of a comparingunit 142b in the mode control module according to an embodiment of the invention.

In this embodiment, the reference generating unit of themode control module 140 generates the first offset reference voltage Vref1_ hys and the first reference voltage Vref1 corresponding to the first threshold at the same time, and Vref1_ hys > Vref1.

On the basis of the embodiment shown in fig. 5b, in this embodiment, the first comparison path in thecomparison unit 142c further includes: a first transmission gate TG1 and a second transmission gate TG2. The input end of the first transmission gate TG1 is used for connecting a first reference voltage Vref1, the control end is connected to the output end of the first not gate INV41, and the inverted control end is connected to the output end of the first not gate NOR 41; an input end of the second transmission gate TG2 is configured to be connected to a first offset reference voltage Vref1_ hys, a control end of the second transmission gate TG2 is connected to an output end of the first NOR gate NOR41, and an inverted control end of the second transmission gate TG2 is connected to an output end of the first NOR gate INV 41; a positive input terminal of the first comparator CMP41 is connected to the differential signal VOP0 in the input signal, positive input terminals of the second comparator CMP42 are respectively connected to the differential signal VON0 in the input signal, and two negative input terminals are commonly connected to output terminals of the first transmission gate TG1 and the second transmission gate TG2.

When the differential amplifier operates in a static state, for example, when the input signal is 0, both CMP41 and CMP42 output a low level, the NOR41 output signal PO1N is a high level, the INV41 output signal PO1 is a low level, and the INV43 output mode control signal EN-HWM is a high level, and controls thedifferential logic unit 121 and thedelay control unit 132 to be enabled, while the second transmission gate TG2 is turned on; as the input signal gradually increases, until at least one of VOP0 or VON0 is greater than Vref1_ hys, the NOR41 output signal PO1N becomes low, the INV41 output signal PO1 becomes high, the INV43 output EN-HWM becomes low, thedifferential logic unit 121 and thedelay control unit 132 are controlled to be disabled, the first transmission gate TG1 is turned on, the second transmission gate TG2 is kept off, the negative input terminals of CMP41 and CMP42 are connected to the first reference voltage Vref1, and the amplitude of the subsequent input signal is compared with the first reference voltage Vref1.

When the input signal is gradually reduced from being larger than Vref1-hys, the reference voltages of the CMP41 and the CMP42 are both Vref1 due to the conduction of the second transmission gate TG2 until the amplitude of the input signal is reduced to be smaller than Vref1, the outputs of the CMP41 and the CMP42 are both changed into low level, PO1N is changed into high level, PO1 is changed into low level, and EN-HWM is changed into high level; at this time, the second transmission gate TG2 is opened, the first transmission gate TG1 is closed, and the subsequent signal is compared with the first offset reference voltage Vref 1-hys.

From the above analysis, when at least one of the input signals is gradually decreased from being greater than the first offset reference voltage, the subsequent input signals are compared with the smaller Vref1; when at least one path of signals in the input signals is gradually increased from being smaller than Vref1, comparing the input signals with Vref1-hys with larger value; through setting different reference voltages for comparison in two processes of signal increase and signal decrease respectively, after the EN-HWM is switched, if the reverse change amplitude of the input signal is within the offset, the EN-HWM is not switched any more, thereby avoiding frequent switching of the EN-HWM.

Fig. 8 is a schematic structural diagram of a comparingunit 142c in a mode control module according to another embodiment.

The reference generation unit of the mode control module simultaneously generates a first offset reference voltage Vref1_ hys and a first reference voltage Vref1 corresponding to a first threshold value, and a second reference voltage Vref2 and a second offset reference voltage Vref2_ hys corresponding to the second threshold value, wherein Vref1_ hys > Vref1, and Vref2_ hys > Vref2.

On the basis of the embodiment of fig. 7, the comparingunit 142c further comprises a second comparing path for comparing the input signal with a second threshold value. The second comparison path further includes a third transmission gate TG3 and a fourth transmission gate TG4. The input end of the third transmission gate TG3 is used for connecting a second reference voltage Vref2, the control end is connected to the output end of the second NOR gate NOR42, and the inverted control end is connected to the output end of the second NOR gate INV 42; an input end of the fourth transmission gate TG4 is configured to be connected to a second offset reference voltage Vref2_ hys, a control end of the fourth transmission gate TG4 is connected to an output end of the second not gate INV42, and an inverted control end of the fourth transmission gate TG4 is connected to an output end of the second not gate NOR 42; a negative input terminal of the third comparator CMP43 is connected to the differential signal VOP0 in the input signal, a negative input terminal of the fourth comparator CMP44 is connected to the differential signal VON0 in the input signal, and two positive input terminals are commonly connected to output terminals of the third transmission gate TG3 and the fourth transmission gate TG4.

In this embodiment, when the mobile terminal operates in a static state, for example, when the input signal is 0, the input signal is smaller than the first threshold, both the CMP41 and the CMP42 output a low level, PO1N is a high level, PO1 is a low level, the second transmission gate TG2 is controlled to be turned on, the INV43 outputs a high level, and the negative input terminals of the CMP41 and the CMP42 are connected to Vref1-hys; the CMP43 and the CMP44 both output a high level, PO2 is a low level, PO2N is a high level, the fourth transmission gate TG4 is controlled to be turned on, and the positive input terminals of the CMP43 and the CMP44 are connected to Vref2-hys; at this time, EN-HWM output by the INV44 is high.

When the input signal is gradually increased until at least one of VOP0 or VON0 is greater than Vref1_ hys and at least one of VOP0 and VON0 is less than Vref2-hys, PO1 is changed to low level and PO1 is changed to high level, the first transmission devices TG1 are controlled to be conducted, and the negative input ends of CMP41 and CMP42 are connected to Vref1; the outputs of both CMP43 and CMP44 are still at high level, PO2 is at low level, PO2N is at high level, and the fourth transmission gate TG4 is still turned on; at this time, the EN-HWM signal output by the INV44 flips to the LOW level.

When the input signals are increased to be larger than Vref2-hys, PO1N is still at a low level, PO1 is still at a high level, and the first transmission gate TG1 is controlled to be conducted; the CMP3 and CMP4 output a low level, PO2 becomes a high level, PO2N is a low level, the third transmission gate TG3 is controlled to be turned on, and the positive input terminals of the CMP43 and CMP44 are connected to Vref2; at this time, the EN-HWM signal outputted from the INV44S is inverted to a high level, and is switched to the narrow pulse width modulation mode.

Similarly, when the input signal is reduced from being larger than Vref2-hys to at least one path which is smaller than Vref2 and larger than Vref1, the EN-HWM signal is inverted to be low level; when the input signal continues to fall below Vref1, the EN-HWM signal is inverted high again.

From the above analysis, when at least one path of the input signals is gradually increased, the input signals are compared with Vref1-hys and Vref2-hys; the input signal is compared to Vref1 and Vref2 when at least one of the input signals is tapered.

Please refer to fig. 9a and 9b, which are schematic waveforms of signals in a static operating state.

In the static initial state (please refer to fig. 9 a), the input signal is smaller than the first threshold. In the initial state, the input signal is 0, and VO1 and VO2 are square wave signals with 50% duty ratio in the same time sequence. In the initial state, the add signal and the subtract signal are both low, and the counting unit 1321 (see fig. 3) with n bits outputs the counting value of 11 \8230, 82301 (n bits), the charging capacitance is the largest, the VO3 delay is the largest, and the pulse width of the output signal is the largest.

Referring to fig. 5b, when the second rising edge of CLK2 (the clock frequency of the D flip-flop controlling the decrement signal) comes, the decrement signal is turned to high level, and thedelay control unit 132 starts to adjust the delay amount of VO3, when the output value of thecounting unit 1321 gradually decreases to 00 \ 8230; \82300 (n bit), the switches SW1 to SWn are all turned off, and the capacitance value of the chargingcapacitor structure 1322b is the smallest and is C0; accordingly, the pulse widths of GTA and GTB (corresponding to VOP and VON) are from t₀ Decreasing to a minimum value tn defined by the charging capacitance C0; thecounter unit 1321 then outputs 000 \ 8230; \82300 remains unchanged, so the pulse widths of VOP and VON are always at a minimum. In other embodiments, the output value of thecounting unit 1321 is gradually decreased to 000 \ 8230; \8230; 0In the process, when the dead time of the drivingoutput units 122a and 122b is greater than or equal to the pulse width of a certain gear, the output pulse width is decreased to 0, and in two cycles of the CLK1 clock, the pulsewidth detection unit 131 does not detect a pulse, the add signal is changed to a high level, the subtract signal is changed to a low level, thecounting unit 1321 controls the switch circuit to increase the charging capacitance value, the delay is increased, so that the pulse width of the output signal reappears, and then the pulse width is controlled to decrease to the minimum value.

And when the input signal is greater than 0, entering a dynamic working state, including a small signal input state and a large signal input state. When the input signal is in the small signal input state, that is, the input signal is greater than the first threshold and smaller than the second threshold, the mode control signal EN-HWM control circuit output by themode control module 140 does not adjust the pulse width, so that the pulse width at the time of inputting the small signal is greater than the minimum pulse width at the time of static operation, and at this time, even if the dead zone of the drivingoutput units 122a and 122b exists, it can be ensured that the pulses exist at all times in the VON and VOP, thereby reducing the distortion of the small signal; and in a large signal input state, the input signal is greater than the second threshold value, the EN-HWM is output again through the mode control module, thedelay control unit 132 and thedifferential logic unit 121 are controlled to perform narrow pulse width modulation on the pulse width, and the pulse widths of VON and VOP are reduced, so that the power consumption is further reduced.

Fig. 10 is a schematic structural diagram of a class D audio amplifier according to another embodiment of the present invention.

In this embodiment, the pulsewidth adjusting module 130 further includes: a fixeddelay unit 134, configured to delay the first pulse width modulation signal VO1 by a fixed amount to form a first delayed signal VO4. Thedelay control unit 132 is configured to delay the second pulse width modulation signal VO1 by a variable amount, so as to achieve variable adjustment of a relative delay amount between the first delayed signal VO4 and the second delayed signal VO3.

By delaying VO1 and VO2 by the fixeddelay unit 134 and thedelay control unit 132, respectively, it is possible to make the two branches as symmetrical as possible, and reduce signal distortion caused by mismatch factors introduced by delayingonly VO 1. By adjusting the delay amount of the signal VO1 by thedelay control unit 132, the delay amount between the signal VO3 and the signal VO4 is adjusted.

The fixed delay unit 124 is also connected to themode control module 140, and the enable state of the fixeddelay unit 134 is controlled by the mode control signal EN-HWM output by themode control module 140 to control whether the fixed delay unit 124 delays the signal.

Please refer to fig. 11, which is a schematic diagram of waveforms of signals of the class D audio amplifier with the structure shown in fig. 10 in a static operating state.

In the static operating state, both thedifferential logic unit 121 and thedelay control unit 132 are enabled. In this example, VO4 has a fixed retardation with respect toVO 1; and the delay amount of VO3 with respect to VO2 is gradually decreased such that the relative delay amount between VO3 and VO4 is gradually decreased to T1. After performing differential operation on the signals VO4 and VO3, signals GTA and GTB are obtained, and the pulse widths of both signals are gradually reduced to a minimum pulse width tn determined by a minimum value T1 of the relative delay amount.

Fig. 12 is a schematic structural diagram of a fixed delay unit according to an embodiment of the invention.

In this embodiment, the fixeddelay unit 134 includes: a second selection switch X2, and a fixed control circuit, the fixed control circuit comprising: current source Ib₀ And a PMOS transistor MP₁₀ ～MP₄₀ NMOS transistor MN₁₀ ～MN₃₀ 。

The input terminal of the second selection switch X2 is connected to the first pwm signal VO1, one output terminal is directly connected to the output terminal of thedelay control unit 134, and the other output terminal is connected to the fixed control circuit. The second selection switch X2 is switched to a conduction path by the mode control signal EN-HWM. In this embodiment, when the mode control signal EN-HWM is at a high level, the fixeddelay control unit 134 is in an enabled state, and VO1 is input to the fixed control circuit; when the mode control signal EN-HWM is at a low level, thedelay control unit 134 is in a non-enabled state, and VO1 is directly output to the VO4 output terminal.

When EN-HWM is high, the firstPulse width modulation signal VO1 passes through MP₄₀ And MN₁₀ The formed inverter is coupled to the fixed capacitor Cm, and when the inverter outputs a high level, the fixed capacitor Cm is charged; and when the inverter outputs a low level, discharging the fixed capacitor Cm. The fixed capacitor Cm is charged to form a signal which is delayed to VO1 and is in an inverted phase with VO1, and then a fixed delay signal VO4 which delays the pulse of VO1 is output after passing through an inverter INV 5.

The current source Ib₀ By MP₁₀ And MP₂₀ Composed current mirror, and MN₂₀ And MN₃₀ A current mirror configured to provide power to the MP₄₀ And MN₁₀ An inverter configured to supply a charging current to the fixed capacitor Cm. The larger the charging current, the shorter the charging time, and the smaller the delay amount of VO4 with respect toVO 1. In this embodiment, the current source Ib₀ And the fixed capacitance Cm are both held fixed so that there is a fixed amount of delay between VO4 andVO 1.

The embodiment of the present invention further provides an electronic device having the above class D audio amplifier, where the class D audio amplifier can adaptively adjust a pulse width according to an output signal, so as to ensure that the output signal has a pulse output all the time, thereby reducing the problems of noise and distortion, and also reducing the pulse width as much as possible, thereby reducing power consumption of the electronic device under certain application conditions.

The embodiment of the invention also provides a self-adaptive pulse width adjusting method.

Fig. 13 is a flowchart illustrating an adaptive pulse width adjusting method according to an embodiment of the invention.

The self-adaptive pulse width adjusting method comprises the following steps:

in step S1301, the input signal is pulse width modulated to generate a first pulse width modulated signal and a second pulse width modulated signal.

The input signal may be a pair of differential signals, such as analog audio signals. The pulse width modulation includes: performing integral operation on the pair of differential signals and outputting two amplified signals; the two amplified signals are respectively compared with the modulation signal through a comparator to generate a first pulse width modulation signal and a second pulse width modulation signal.

The modulation signal is typically a triangular wave having a particular frequency and level value. When the level of the amplified signal exceeds the signal level of the triangular wave, the comparator outputs a high level; when the level of the amplified signal is lower than the signal level of the triangular wave, the comparator outputs a low level; therefore, the output first pulse width modulation signal and the second pulse width modulation signal are both modulated square wave signals with certain duty ratio. In other embodiments, the modulation signal may also be a waveform signal with a periodic rising and falling slope, such as a sawtooth wave or a sinusoidal half wave. The frequency of the modulation signal is usually 400KHz to 800KHz, which is much higher than the frequency of the signal to be modulated.

Step S1302: and judging whether to adjust the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the amplitude of the input signal.

If the input signal is smaller than a first threshold value, adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal; and if the input signal is greater than or equal to the first threshold value, keeping the relative delay amount unchanged.

Since the input signal power is related to the input signal amplitude, the detection of the input signal amplitude can be used to determine whether the input signal exceeds the first threshold. In one embodiment, a first reference voltage corresponding to the first threshold is provided, and the input signal is compared to the first reference voltage; when the input signal is smaller than the first reference voltage, adjusting the relative delay amount; when the input signal is greater than or equal to the first reference voltage, the relative delay amount is kept unchanged. In other embodiments, a first offset reference voltage corresponding to the first threshold is provided, the first offset reference voltage being greater than the first reference voltage; the input signal is compared with the first offset reference voltage when the input signal gradually increases, and compared with the first reference voltage when the input signal gradually decreases.

In another embodiment, the method of controlling the minimum value of the relative delay amount further comprises adjusting the relative delay amount when the input signal is greater than the second threshold. Specifically, a first reference voltage corresponding to the first threshold value and a second reference voltage corresponding to the second threshold value are provided; comparing the input signal to the first and second reference voltages; when the input signal is smaller than the first reference voltage, the relative delay amount needs to be adjusted; when the input signal is greater than or equal to the first reference voltage and smaller than the second reference voltage, the relative delay amount does not need to be adjusted; when the input signal is greater than or equal to the second reference voltage, the relative delay amount needs to be adjusted.

In order to avoid frequent switching of the adjustment mode for the above relative delay amount, in some embodiments, a first offset reference voltage corresponding to the first threshold and a second offset reference voltage corresponding to the second threshold are further provided, the first offset reference voltage is greater than the first reference voltage, and the second offset reference voltage is greater than the second reference voltage; the input signal is compared with the first offset reference voltage and the second offset reference voltage when the input signal is gradually increased, and compared with the first reference voltage and the second reference voltage when the input signal is gradually decreased.

If the determination in step S1302 is yes, step S1303 is executed to adjust a relative delay amount between the second pwm signal and the first pwm signal according to the first output signal and the second output signal output to the load, so as to form a corresponding first delay signal and a second delay signal.

In step S1303, the method for controlling the relative delay amount includes: performing level conversion on the first output signal and the second output signal to form a first conversion signal and a second conversion signal; detecting whether the first conversion signal and the second conversion signal have pulses or not, and outputting corresponding control signals; and adjusting the relative delay amount according to the control signal. If no pulse is detected in the first output signal and the second output signal, increasing the delay amount and increasing the pulse width of the first output signal and the second output signal; if the pulse is detected, reducing the delay amount and reducing the pulse width of the first output signal and the second output signal; therefore, the pulse of the first output signal and the pulse of the second output signal are always limited to be close to the minimum pulse width, so that the first output signal and the second output signal are ensured to have pulse output, the problems of noise and distortion are reduced, the width of the pulse can be reduced as much as possible, and the power consumption is reduced.

And, the first output signal and the second output signal that are finally output to the load end by the D-type audio amplifier are detected to judge whether pulses exist, and the final output signal is not lost or eliminated by the dead zone of the output driving module before being applied to the load, so that the output pulse width of the first output signal and the second output signal can be reduced as much as possible without worrying about the phenomenon of no output due to the small pulse width.

In some embodiments, the second pwm signal is adjusted by a control circuit, the control circuit includes a charge/discharge structure, and the second pwm signal is delayed by charging or discharging the charge/discharge structure to output a second delayed signal. The delay amount is adjusted by controlling the charging time, and the longer the charging time is, the larger the delay amount is. In step S1304, the minimum value of the relative delay amount may be controlled by controlling the minimum value of the charging time, and specifically, the minimum value of the relative delay amount may be controlled by controlling the minimum charging capacitance value and/or the maximum charging current value.

In some embodiments, the charging time may be adjusted by a count value of a counter. Specifically, the delay amount may be adjusted by increasing or decreasing the count value of the counter according to the detection result and changing the count value. Specifically, when there is no pulse, the count value is increased to gradually increase the delay amount and increase the pulse width; in the presence of pulses, decreaseA count value to gradually decrease the delay amount to decrease the pulse width. The delay amount may be adjusted by adjusting a charging capacitance value and/or a charging current between the second pwm signal output terminal and a ground terminal by the count value. The larger the charging capacitance value is, the longer the charging time is, the larger the delay amount is, and the output pulse width is increased; the smaller the charging capacitance value is, the shorter the charging time is, the smaller the delay amount is, and the output pulse width is reduced. The larger the charging current is, the shorter the charging time is, the smaller the delay amount is, and the output pulse width is reduced; the smaller the charging current is, the longer the charging time is, the larger the delay amount is, and the larger the output pulse width is. The count value may be an n-bit binary signal, thereby implementing 2ⁿ A control quantity can be generated as 2ⁿ Charging current, or 2ⁿ A charging capacitance value. The adjustment of the charging current can be realized by a plurality of current sources which can be selectively connected in parallel, and the adjustment of the charging current is realized by selecting one or more current sources suitable for being connected into the circuit through the counting value. The adjustment of the charging capacitor can be realized by a plurality of capacitors which can be selectively connected in parallel, and the adjustment of the charging capacitor is realized by selecting one or more proper capacitors to be connected into the circuit through the counting value.

In other embodiments, a fixed amount of delay may be further applied to the first pulse width modulated signal.

And after the step S1303, continuing to execute a step S1304 of performing differential operation on the first delay signal and the second delay signal to generate two paths of differential operation signals, and performing power amplification on the two paths of differential operation signals to generate a first output signal and a second output signal which are output to a load, wherein pulse widths of the first output signal and the second output signal are changed along with the relative delay amount.

If not, in step S1302, a step S1305 is executed to maintain the relative delay amount between the second pwm signal and the first pwm signal unchanged, and perform power amplification to generate a first output signal and a second output signal for output to a load.

The hybrid modulation method switches the pulse width modulation mode of the audio signal according to the amplitude of the input signal, realizes dynamic adjustment of the pulse width of the input signal, ensures that the output signal has pulse output all the time, thereby reducing the problems of bottom noise and distortion, and can reduce the pulse width as much as possible, thereby reducing the power consumption of electronic equipment.

The above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent processes, such as combinations of technical features between various embodiments, or direct or indirect applications in other related technical fields, which are made by using the contents of the present specification and the accompanying drawings, are all included in the scope of the present application.

Claims (22)

1. A class D audio amplifier, comprising:

the pulse width modulation module is used for performing pulse width modulation on an input signal and outputting a first pulse width modulation signal and a second pulse width modulation signal, wherein the input signal comprises two paths of differential signals;

the pulse width adjusting module is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the first output signal and the second output signal output to a load in an enabling state, and outputting the corresponding first delay signal and the second delay signal to the driving module; in a non-enabled state, maintaining the second pulse width modulation signal and the first pulse width modulation signal unchanged, and outputting the second pulse width modulation signal and the first pulse width modulation signal to a driving module;

the driving module comprises a differential logic unit and a driving output unit, wherein the differential logic unit is used for carrying out differential operation on signals input to the driving module in an enabling state and outputting two paths of differential operation signals to the driving output unit; keeping the waveform of the signal input to the driving module unchanged in a non-enabled state and outputting the signal to the driving output unit; the driving output unit is used for performing power amplification on the output signal of the differential logic unit and outputting the first output signal and the second output signal;

and the mode control module is used for outputting a mode control signal to the pulse width adjusting module and the driving module according to the amplitude of the input signal so as to control the working states of the pulse width adjusting module and the differential logic unit.

2. The class-D audio amplifier according to claim 1, wherein the mode control module is configured to output a corresponding mode control signal when the amplitudes of the two signals in the input signal are both smaller than a first threshold, and control the differential logic unit and the pulse width adjustment module to be in an enabled state; and when the amplitude of at least one path of signal in the input signals is larger than or equal to a first threshold value, outputting a corresponding mode control signal, and controlling the differential logic unit and the pulse width adjusting module to be in a non-enabled state.

3. The class D audio amplifier according to claim 2, wherein the mode control module comprises a reference generation unit and a comparison unit; the reference generating unit is used for generating a first reference voltage corresponding to the first threshold value; the comparison unit is used for comparing the input signal with the first reference voltage and outputting a corresponding mode control signal according to a comparison result.

4. The class D audio amplifier according to claim 3, wherein the comparing unit comprises a first comparator, a second comparator, a first nor gate, a first not gate and a third not gate; two negative input ends of the first comparator and the second comparator are simultaneously connected to a first reference voltage, two positive input ends of the first comparator and the second comparator are respectively connected to two differential signals in the input signals, output ends of the first comparator and the second comparator are respectively connected to the input end of the first NOR gate, and the output end of the first NOR gate is sequentially connected with the first NOR gate and the third NOR gate.

5. The class D audio amplifier of claim 3 or4, wherein the reference generating unit is further configured to generate a first offset reference voltage corresponding to the first threshold, the first offset reference voltage being greater than the first reference voltage; the comparison unit is used for controlling the subsequent input signals to be compared with the first reference voltage when the amplitude of at least one path of signals in the input signals is gradually reduced from being larger than the first offset reference voltage, and controlling the subsequent input signals to be compared with the first offset reference voltage when the amplitude of at least one path of signals in the input signals is gradually increased from being smaller than the first reference voltage.

6. The class D audio amplifier of claim 4, wherein the comparison unit further comprises a first transmission gate, a second transmission gate; the input end of the first transmission gate is used for being connected with the first reference voltage, the control end of the first transmission gate is connected to the output end of the first not gate, and the inverted control end of the first transmission gate is connected to the output end of the first not gate; the input end of the second transmission gate is used for being connected to a first offset reference voltage, the control end of the second transmission gate is connected to the output end of the first NOR gate, and the inverted control end of the second transmission gate is connected to the output end of the first NOR gate; two negative input ends of the first comparator and the second comparator are connected to the output ends of the first transmission gate and the second transmission gate in common; wherein the first offset reference voltage corresponds to the first threshold and is greater than the first reference voltage.

7. The class-D audio amplifier according to claim 2, wherein the mode control module is further configured to output a corresponding mode control signal when the amplitudes of the two paths of signals in the input signal are both greater than a second threshold value, so as to control both the differential logic unit and the pulse width adjustment module to be in an enable state; the second threshold is greater than the first threshold.

8. The class D audio amplifier according to claim 7, wherein the mode control module comprises a reference generation unit and a comparison unit; the reference generating unit is used for generating a first reference voltage corresponding to the first threshold value and a second reference voltage corresponding to a second threshold value; the comparison unit is used for comparing the input signal with the first reference voltage and the second reference voltage and outputting a corresponding mode control signal according to a comparison result.

9. The class D audio amplifier of claim 8, wherein the reference generating unit is further configured to generate a second offset reference voltage corresponding to a second threshold, the second offset reference voltage being greater than the second reference voltage; the comparison unit is used for controlling the subsequent input signal to be compared with the second reference voltage when the amplitude of at least one path of signal in the input signals is gradually reduced from being larger than the second offset reference voltage, and controlling the subsequent input signal to be compared with the second offset reference voltage when the amplitude of at least one path of signal in the input signals is gradually increased from being smaller than the second reference voltage.

10. The class D audio amplifier of claim 8, wherein the comparing unit further comprises a first comparing path, a second comparing path, and an exclusive nor circuit; the first comparison path includes: the two negative input ends of the first comparator and the second comparator are simultaneously connected to a first reference voltage, the two positive input ends of the first comparator and the second comparator are respectively connected to two differential signals in the input signals, the output ends of the first comparator and the second comparator are connected to the input end of the first NOR gate, and the output end of the first NOR gate is sequentially connected with the first NOR gate and the third NOR gate; the second compare path includes: the two positive input ends of the third comparator and the fourth comparator are simultaneously connected to a second reference voltage, the two negative input ends of the third comparator and the fourth comparator are respectively connected to two differential signals in the input signals, the output ends of the third comparator and the fourth comparator are both connected to the input end of the second NOR gate, and the output end of the second NOR gate is connected to the input end of the second NOR gate; and the output ends of the third NOT gate and the second NOT gate are connected to the input end of the XOR not circuit, and the output end of the XOR not circuit is used for outputting the mode control signal.

11. The class D audio amplifier of claim 10, wherein the first comparison path of the comparison unit further comprises a first transmission gate and a second transmission gate, the input terminal of the first transmission gate is connected to the first reference voltage, the control terminal is connected to the output terminal of the first not gate, and the inverted control terminal is connected to the output terminal of the first nor gate; the input end of the second transmission gate is used for being connected to a first offset reference voltage, the control end of the second transmission gate is connected to the output end of the first NOR gate, and the inverted control end of the second transmission gate is connected to the output end of the first NOR gate; two negative input ends of the first comparator and the second comparator are connected to the output ends of the first transmission gate and the second transmission gate in common; the second comparison path further comprises a third transmission gate and a fourth transmission gate, wherein an input end of the third transmission gate is used for being connected to the second reference voltage, a control end of the third transmission gate is connected to an output end of the second NOR gate, and an inverted control end of the third transmission gate is connected to an output end of the second NOR gate; the input end of the fourth transmission gate is used for being connected to a second offset reference voltage, the control end of the fourth transmission gate is connected to the output end of the second not gate, and the inverted control end of the fourth transmission gate is connected to the output end of the second not gate; wherein the first offset reference voltage corresponds to a first threshold and is greater than the first reference voltage; the second offset reference voltage corresponds to a second threshold, and the second offset reference voltage is greater than the second reference voltage.

12. The class D audio amplifier of claim 1, wherein the pulse width adjustment module comprises:

the pulse width detection unit is used for detecting whether pulses exist in the first output signal and the second output signal or not and outputting corresponding pulse width control signals;

and the delay control unit is controlled by the mode control signal to enter an enabling state or not, and is used for adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the pulse width control signal in the enabling state and directly outputting the received second pulse width modulation signal to the driving module in a non-enabling state.

13. A method of hybrid modulation for a class D audio amplifier, comprising:

performing pulse width modulation on an input signal to generate a first pulse width modulation signal and a second pulse width modulation signal;

judging whether to adjust the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the amplitude of the input signal;

if so, adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to a first output signal and a second output signal output to a load to form a corresponding first delay signal and a second delay signal; performing differential operation on the first delay signal and the second delay signal to generate two paths of differential operation signals, and then performing power amplification on the two paths of differential operation signals to generate a first output signal and a second output signal which are output to a load, wherein the pulse widths of the first output signal and the second output signal are changed along with the relative delay amount;

if not, keeping the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal unchanged, carrying out power amplification on the first pulse width modulation signal and the second pulse width modulation signal, and generating a first output signal and a second output signal which are output to a load.

14. The hybrid modulation method according to claim 13, wherein if the amplitudes of both signals in the input signals are smaller than a first threshold, the relative delay amount between the second pwm signal and the first pwm signal is adjusted; and if the amplitude of at least one path of signals in the input signals is larger than the first threshold value, keeping the relative delay amount unchanged.

15. The hybrid modulation method according to claim 14, wherein the method of determining whether to adjust the relative delay amount between the second pwm signal and the first pwm signal further comprises: providing a first reference voltage corresponding to the first threshold, comparing the input signal with the first reference voltage; when the amplitudes of two paths of signals in the input signals are smaller than the first reference voltage, adjusting the relative delay amount; and when the amplitude of at least one path of signals in the input signals is greater than or equal to the first reference voltage, keeping the relative delay constant.

16. The hybrid modulation method according to claim 15, wherein the method of determining whether to adjust the relative delay amount between the second pwm signal and the first pwm signal further comprises: providing a first offset reference voltage corresponding to the first threshold, the first offset reference voltage being greater than the first reference voltage; when the amplitude of at least one of the input signals is gradually reduced from being larger than the first offset reference voltage, the subsequent input signal is controlled to be compared with the first reference voltage, and when the amplitude of at least one of the input signals is gradually increased from being smaller than the first reference voltage, the subsequent input signal is controlled to be compared with the first offset reference voltage.

17. The hybrid modulation method according to claim 14, wherein the method of determining whether to adjust the relative delay amount further comprises: and when the amplitudes of the two paths of signals in the input signals are larger than a second threshold value, adjusting the relative delay amount.

18. The hybrid modulation method according to claim 17, wherein the method of determining whether to adjust the relative delay amount comprises: providing a first reference voltage corresponding to the first threshold value and a second reference voltage corresponding to a second threshold value; comparing the input signal to the first and second reference voltages; when the amplitudes of two paths of signals in the input signals are smaller than the first reference voltage, adjusting the relative delay amount; when the amplitude of at least one path of signals in the input signals is greater than or equal to the first reference voltage and smaller than the second reference voltage, keeping the relative delay amount unchanged; and when the amplitudes of the two paths of signals in the input signals are both larger than or equal to the second reference voltage, adjusting the relative delay amount.

19. The hybrid modulation method according to claim 18, further comprising: providing a first offset reference voltage corresponding to the first threshold, a second offset reference voltage corresponding to the second threshold, the first offset reference voltage being greater than the first reference voltage, the second offset reference voltage being greater than the second reference voltage; when the amplitude of at least one path of signals in the input signals is gradually reduced from being larger than the first offset reference voltage, controlling the subsequent input signals to be compared with the first reference voltage; when the amplitude of at least one path of signals in the input signals is gradually increased from being smaller than the first reference voltage, controlling the comparison between the subsequent input signals and the first offset reference voltage; and when the amplitude of at least one of the input signals is gradually increased from being smaller than the second reference voltage, the subsequent input signal is controlled to be compared with the second offset reference voltage.

20. The hybrid modulation method according to claim 13, wherein the method of adjusting the relative delay amount between the second pulse width modulation signal and the first pulse width modulation signal according to the first output signal and the second output signal output to the load comprises: performing level conversion on the first output signal and the second output signal to form a first conversion signal and a second conversion signal; detecting whether the first conversion signal and the second conversion signal have pulses or not and outputting corresponding pulse width control signals; and adjusting the relative delay amount according to the pulse width control signal.

21. The hybrid modulation method according to claim 13, wherein the method of adjusting the relative delay amount further comprises: and delaying the first pulse width modulation signal by a fixed amount to form the first delayed signal.

22. An electronic device, comprising: a class D audio amplifier according to any of claims 1 to 12.

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