CN112798922A

Movatterモバイル変換

Info

Publication number: CN112798922A
Application number: CN201911106204.2A
Authority: CN
Inventors: 蔡振龙; 基因·罗森塔尔
Original assignee: First Inspection Co Ltd
Current assignee: First Inspection Co Ltd
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2021-05-14
Anticipated expiration: 2039-11-13
Also published as: CN112798922B

Abstract

The invention discloses an environment control device and a chip test system. The equipment body of the environment control equipment is provided with a plurality of accommodating chambers, and each accommodating chamber is provided with a temperature adjusting device. Each temperature regulating device comprises a temperature regulator, a contact structure, a frame body and an elastic annular sealing piece. When the chip testing device bearing a plurality of chips is arranged in the accommodating chamber and the contact structure is contacted with one side of the plurality of chips, the elastic annular sealing piece is correspondingly pressed against the chip testing device, and a closed space is formed between the chip testing device and the contact structure. The air extractor connected with the environment control equipment can extract the air in the closed space outwards, and the temperature regulator can correspondingly adjust the temperature of the contact structure, so that each chip is subjected to a preset test program by the chip testing device in a specific temperature environment.

Description

Environment control equipment and chip test system

Technical Field

The present invention relates to an environmental control apparatus and a chip test system, and more particularly, to an environmental control apparatus and a chip test system suitable for testing a semiconductor device (e.g., a memory).

Background

The conventional memory test equipment is designed to detect a large amount of memory, and the conventional memory test equipment must consume a large amount of power when running, and accordingly generates a high electric charge. Therefore, it is necessary for the related developers to avoid sending a small amount of memory into the memory test equipment for testing during the development process unless it is not otherwise necessary.

In addition, the conventional memory test device can only perform the same predetermined stroke test on the same batch of memories in the same time period, so that if two batches of memories need to be tested with different predetermined strokes, one batch of memories can enter the memory test device to be tested only after the other batch of memories completes all tests, and thus, the test time of the whole memory is long.

Disclosure of Invention

The embodiment of the invention provides an environment control device and a chip test system, which are used for improving the problem that the existing memory test device can only perform a single preset test on a batch of memories in the same time period, and related manufacturers cannot perform different preset tests on different memories in the same time period.

Preferably, the environment control equipment further comprises a plurality of limiting devices, each accommodating chamber is provided with one limiting device, and each limiting device is connected with the environment state control device; each limiting device can be controlled by the environment state control device and is mutually connected with the chip testing device arranged in the accommodating chamber, so that the moving range of the chip testing device in the accommodating chamber is limited.

Preferably, the environment control equipment further comprises a plurality of lifting devices, each accommodating chamber is provided with one lifting device, and each lifting device is connected with the environment state control device; each lifting device can be controlled by the environment state control device, so that the chip testing device arranged in the accommodating chamber moves in the accommodating chamber.

Preferably, the environment control apparatus further comprises a chip testing device, the chip testing device comprising: at least one circuit board, wherein two opposite side surfaces of the circuit board are respectively defined as a first side surface and a second side surface; the circuit board is provided with a plurality of positioning holes and a plurality of circuit board locking holes, each positioning hole does not penetrate through the circuit board, and each circuit board locking hole penetrates through the circuit board; the fixing assembly comprises a first fixing component and a second fixing component, the first fixing component is fixedly arranged on the first side surface, the second fixing component is fixedly arranged on the second side surface, the first fixing component is provided with a plurality of first locking holes, the second fixing component is provided with a plurality of second locking holes, and the plurality of first locking holes, the plurality of circuit board locking holes and the plurality of second locking holes are correspondingly arranged; the circuit board is fixed between the first fixing component and the second fixing component; each electric connecting seat is provided with an electric connecting seat body; one side of each electric connection seat body is used for bearing a chip, the other side of the electric connection seat body is provided with at least two positioning pieces, each positioning piece is mutually clamped with the plurality of positioning holes, and each electric connection seat is arranged on the first side surface of the circuit board; the first fixing member comprises a plurality of abutting structures which are correspondingly abutted against a part of the plurality of electric connecting seats, each electric connecting seat is abutted against by the first fixing member and fixed on the first side surface of the electric connecting seat, the first fixing member comprises a plurality of through holes, and a part of each electric connecting seat is correspondingly exposed out of each through hole; the control unit is arranged on the second side face of the circuit board and comprises a plurality of test modules, and each test module is connected with one part of the electric connecting seats; the second fixing component is provided with a plurality of avoidance holes, and a part of the plurality of test modules penetrates through the plurality of avoidance holes; and

a first power supply member connected to the circuit board; the chip testing device must be connected to the power supply device through the first power supply component to obtain the power required by the operation of each test module.

Preferably, each test module comprises: a Pattern Generator (PG), a Device Power supply module (DPS), and a Driver circuit (Driver); the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection seats are divided into a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the plurality of test modules are connected with the electric connecting seats of the plurality of electric connecting seat groups, and each test module is connected with all the electric connecting seats in the corresponding electric connecting seat group.

Preferably, the first fixing member further includes a fixing body, each of the abutting structures is detachably fixed to the fixing body, each of the fixing bodies has a plurality of group receiving holes, and each of the group receiving holes is configured to receive a plurality of electrical connectors in the same electrical connector group.

Preferably, the circuit board has a plurality of first contact structures on the second side, each test module has at least one second contact structure, and the second contact structure of each test module can detachably contact with one of the first contact structures.

Preferably, the first power supply member includes a plurality of connection terminals, the plurality of connection terminals are disposed on the first side surface of the circuit board, and the plurality of connection terminals are exposed from the first fixing member; the second power supply member in each housing chamber includes a plurality of housing chamber terminals; the plurality of connecting terminals are used for being connected with the plurality of accommodating chamber terminals in the accommodating chambers; when the plurality of connecting terminals are connected with the plurality of accommodating chamber terminals in one accommodating chamber, the power supply equipment can supply power to the chip testing device.

Preferably, the first power supply member is a receiving antenna, the second power supply member is a transmitting antenna, the receiving antenna is used for coupling with the transmitting antenna, and the chip testing device can wirelessly receive the power transmitted by the power supply device through the receiving antenna.

Preferably, the chip testing device further comprises at least one first data transmission terminal, the first data transmission terminal is disposed on the circuit board, and the first data transmission terminal is exposed out of the first fixing member; each accommodating chamber also comprises at least one second data transmission terminal; the first data transmission terminals are used for being in contact with the second data transmission terminals in the containing chambers to transmit data to each other.

Preferably, the chip testing device further comprises at least one first data transmission antenna; the equipment body also comprises at least one second data transmission antenna; and the first data transmission antenna is used for transmitting data with the second data transmission antenna in a wireless mode.

Preferably, after each test module completes a predetermined test program for the chips on the plurality of electrical sockets connected thereto, the test module writes test result data and test parameter data of each chip into the chip, so that the test result data and the test parameter data are stored in each chip.

Preferably, each electrical connection socket comprises: the base body is provided with a top wall and an annular side wall, the top wall is provided with an opening, one end of the annular side wall is connected with the periphery of the top wall, the other end of the annular side wall is abutted against the circuit board, and the top wall, the annular side wall and the circuit board form a containing groove together; two opposite side surfaces of the top wall are defined as an outer side surface and an inner side surface, and the inner side surface is positioned in the accommodating groove; one side of the top wall opposite to the circuit board is defined as an outer side surface which is flush with a butting surface of the first fixing component opposite to the circuit board; the supporting structure is abutted against the circuit board and is positioned in the accommodating groove, the supporting structure comprises a plurality of positioning holes, and each positioning hole is provided with a positioning piece; the lifting structure is arranged in the accommodating groove and is provided with a base part and a bearing part, the base part is positioned in the accommodating groove, the base part extends towards one side to form the bearing part, and at least one part of the bearing part is positioned in the opening; the bearing part extends towards one side far away from the base part to form a plurality of limiting parts, at least one part of the limiting parts penetrates through the opening, and a chip containing groove is formed by the limiting parts and the bearing part together and is used for containing a chip; the lifting structure is also provided with a plurality of connecting holes which penetrate through the base part and the bearing part; the elastic components are arranged in the accommodating groove, one end of each elastic component is fixed to the lifting structure, the other end of each elastic component is fixed to the supporting structure, the elastic restoring force generated by the compression of the elastic components enables the base part to abut against the inner side surface of the top wall, and a gap is formed between the lifting structure and the supporting structure; one end of each probe assembly is fixedly arranged on the supporting structure, the other end of each probe assembly abuts against the electric contact structure of the circuit board, and the other ends of the probe assemblies penetrate through the connecting holes; when the chip accommodating groove is provided with the chip and the limiting part is not pressed by the contact structure, the probe assemblies positioned in the connecting holes are not connected with the connecting point parts of the chip, and one part of the lifting structure protrudes out of the outer side surface of the top wall; when the chip accommodating groove is provided with the chip, the limiting part is pressed by the contact structure to retract towards the base body, and the elastic annular sealing element is mutually pressed with the pressing top surface of the first fixing component, the plurality of probe assemblies are pressed against the electric contact structure of the circuit board.

Preferably, at least one air exhaust gap is formed between the frame body of each temperature adjusting device and the contact structure, the frame body is provided with at least one air exhaust hole, the air exhaust hole is communicated with the air exhaust gap, and the air exhaust device can exhaust air in the closed space outwards through the air exhaust hole and the air exhaust gap.

In summary, the environmental control apparatus and the chip testing system disclosed in the embodiments of the present invention provide a plurality of accommodating chambers, each of which can accommodate a chip testing device carrying a plurality of chips (e.g., memory), and the temperature of each of the accommodating chambers is adjusted by a temperature adjusting device in the accommodating chamber, so that the chip testing devices disposed in different accommodating chambers can be tested in different temperature environments at the same time.

Drawings

FIG. 1 is a schematic diagram of a chip testing system according to the disclosure.

FIG. 2 is a block diagram of a chip testing system according to the present disclosure.

FIG. 3 is a schematic diagram of a chip testing apparatus according to the disclosure.

FIG. 4 is a partially exploded view of the chip testing apparatus according to the present invention.

FIG. 5 is another partially exploded view of the chip testing device disclosed in the present invention.

Fig. 6 is a partially enlarged schematic view of the chip testing apparatus disclosed in the present invention.

Fig. 7 is an exploded view of the pressing structure and the fixing body of the chip testing device disclosed in the present invention.

Fig. 8 is an exploded view of the electrical connector and the circuit board of the chip testing device disclosed in the present invention.

Fig. 9 is an exploded view of the test module, the circuit board and the second fixing member of the chip testing apparatus according to the present invention.

FIG. 10 is a block diagram of a chip testing apparatus according to the disclosure.

FIG. 11 is a schematic view of an electrical connector of the chip testing apparatus disclosed in the present invention.

FIG. 12 is an exploded cross-sectional view of an electrical connector of the chip testing apparatus according to the present invention.

Fig. 13 is a schematic cross-sectional view of an electrical connector of a chip testing device without a chip according to the disclosure.

FIG. 14 is a cross-sectional view of an electrical connector with a chip of the chip testing device of the present invention.

Fig. 15 is an exploded view of a pressing structure and a fixing body of another embodiment of the chip testing device disclosed in the present invention.

FIG. 16 is a schematic diagram of an electrical connector of another embodiment of the chip testing apparatus disclosed in the present invention.

FIG. 17 is a diagram of an environment control apparatus of the chip testing system according to the present disclosure.

FIG. 18 is a block diagram of an apparatus and a central control apparatus included in the environmental control device of the chip testing system according to the present invention.

FIG. 19 is a schematic diagram of a temperature adjustment device of the chip testing system according to the disclosure.

FIG. 20 is a partial cross-sectional view of a chip testing apparatus of the chip testing system according to the present disclosure.

FIG. 21 is a schematic cross-sectional view of a temperature adjustment device disposed on a chip testing device of the chip testing system according to the present invention.

Fig. 22 is a partially enlarged schematic view of fig. 19.

FIG. 23 is an enlarged view of a single electrical connector being pressed by a contact structure.

Fig. 24 is a flowchart illustrating a chip testing method used by the chip testing system to test a plurality of chips according to a first embodiment of the present disclosure.

Fig. 25 is a flowchart illustrating a chip testing method used by the chip testing system to test a plurality of chips according to a second embodiment of the present invention.

Fig. 26 is a flowchart illustrating a chip testing method used by the chip testing system to test a plurality of chips according to a third embodiment of the present disclosure.

Fig. 27 is a flowchart illustrating a chip testing method used by the chip testing system according to a fourth embodiment of the present invention.

Fig. 28 is a flowchart illustrating a fifth embodiment of a chip testing method used by the chip testing system to test a plurality of chips according to the present disclosure.

Fig. 29 is a flowchart illustrating a sixth embodiment of a chip testing method used by the chip testing system to test a plurality of chips according to the present disclosure.

Fig. 30 is a flowchart illustrating a chip testing method used by the chip testing system to test a plurality of chips according to a seventh embodiment of the present disclosure.

Fig. 31 is a flowchart illustrating an eighth embodiment of a chip testing method used by the chip testing system to test a plurality of chips according to the present disclosure.

Detailed Description

Referring to fig. 1 to 5 together, fig. 1 is a schematic diagram of a chip testing system disclosed in the present invention, fig. 2 is a schematic block diagram of the chip testing system disclosed in the present invention, fig. 3 is a schematic diagram of a chip testing apparatus disclosed in the present invention, and fig. 4 and 5 are partially exploded schematic diagrams of the chip testing apparatus disclosed in the present invention. The chip test system E disclosed by the invention is used for testing a plurality of chips C. The chip test system E includes: a central control device E1, a chip installation device E2, at least onechip testing device 1, a plurality of environment control devices E3, a transfer device E4 and a sorting device E5.

The central control device E1 is connected with the chip mounting equipment E2, the plurality of environment control equipment E3, the transferring equipment E4 and the sorting equipment E5, and the central control device E1 can control the operation of each equipment; the central control device E1 is, for example, a server, various computer devices, and the like, and is not limited thereto. In practical applications, the central control apparatus E1 may include a plurality of environmental status control apparatuses (e.g., various processors, computers, etc.), and the device body E31 (as shown in fig. 17) of each environmental control device E3 may be correspondingly provided with one environmental status control apparatus, that is, each environmental control device E3 may include one environmental status control apparatus. The chip mounting apparatus E2 may include a robot arm (not shown), which can be controlled by the central control device E1 to take out the chips C on the tray one by one and place the chips C on theelectrical connectors 2 of thechip testing apparatus 1 one by one.

Thechip testing apparatus 1 is used to carry a plurality of chips C, and thechip testing apparatus 1 can be carried by the transfer equipment E4 and transferred among a plurality of workstations (e.g., a chip mounter E2, a plurality of environmental control equipments E3, a transfer equipment E4, and a sorting equipment E5).

As shown in fig. 3 to 5, thechip test apparatus 1 includes: acircuit board 10, a fixing component 11, a plurality ofelectrical connectors 2, acontrol unit 3 and at least one firstpower supply member 4. Two opposite sides of thecircuit board 10 are respectively defined as afirst side 101 and a second side 102 (as shown in fig. 9). Theelectrical connection sockets 2 are fixedly disposed on thefirst side surface 101 of thecircuit board 10, and eachelectrical connection socket 2 is used for carrying a chip C. The form of theelectrical connector 2 can vary from chip to chip, without limitation.

The fixing assembly 11 includes a first fixingmember 111 and asecond fixing member 112. Thefirst fixing member 111 is disposed on thefirst side 101, and the second fixingmember 112 is fixedly disposed on thesecond side 102. Thefirst fixing member 111 has a plurality offirst locking holes 1111, the second fixingmember 112 has a plurality of second locking holes 1121, thecircuit board 10 has a plurality of circuitboard locking holes 103, eachfirst locking hole 1111 is disposed through the first fixingmember 111, eachsecond locking hole 1121 is disposed through the second fixingmember 112, each circuitboard locking hole 103 is disposed through thecircuit board 10, and the plurality offirst locking holes 1111, the plurality of circuitboard locking holes 103, and the plurality of second locking holes 1121 are correspondingly disposed. In practical applications, the number, shape and distribution positions of thefirst locking holes 1111, the circuitboard locking holes 103 and thesecond locking holes 1121 can be varied according to requirements, and are only an exemplary embodiment.

A plurality of locking members (not shown), such as screws, are locked in the plurality offirst locking holes 1111, the plurality of circuitboard locking holes 103 and the plurality of second locking holes 1121, and thecircuit board 10 is fixed between the first fixingmember 111 and the second fixingmember 112. That is, thecircuit board 10 is clamped between the first fixingmember 111 and the second fixingmember 112, and the overall structural strength of thecircuit board 10 is improved by the arrangement of the first fixingmember 111 and the second fixingmember 112. In practical applications, the first fixingmember 111 and the second fixingmember 112 may be made of a high hardness material such as stainless steel; thecircuit board 10 may be formed such that only each of the circuitboard locking holes 103 is disposed through thecircuit board 10, and besides, thecircuit board 10 does not have other holes penetrating through thecircuit board 10.

In particular, in practical applications, eachfirst lock hole 1111 may not be disposed through the first fixingmember 111, and eachfirst lock hole 1111 may be a blind hole, or a part of thefirst lock holes 1111 may be through holes and another part of thefirst lock holes 1111 may be blind holes; in the case that thefirst locking hole 1111 is a blind hole, the correspondingsecond locking hole 1121 is a through hole penetrating through the second fixingmember 112. In the case that thefirst locking hole 1111 is a through hole, at least a portion of thesecond locking hole 1121 may be a blind hole.

Referring to fig. 4, 6 and 7, fig. 6 is a partially enlarged schematic view of a chip testing device disclosed in the present invention, and fig. 7 is an exploded schematic view of a pressing structure and a fixing body of the chip testing device disclosed in the present invention. In practical applications, the first fixingmember 111 may include a plurality ofpressing structures 1112 and a fixingbody 1114, eachpressing structure 1112 and the fixingbody 1114 are independent from each other, and eachpressing structure 1112 is detachably fixed on the fixingbody 1114. Eachpressing structure 1112 is substantially in the shape of a lattice column, and eachpressing structure 1112 is correspondingly formed with a plurality of throughholes 1113.

When the first fixingmember 111 is fixed on thefirst side 101 of thecircuit board 10, the plurality ofpressing structures 1112 are pressed against a portion of theelectrical connector body 21 of the plurality ofelectrical connectors 2, and a portion of eachelectrical connector 2 is exposed to each throughhole 1113. That is, in addition to the first fixingmember 111 and the second fixingmember 112 cooperating with each other to clamp thecircuit board 10, the first fixingmember 111 is also used to fix the plurality ofelectrical connectors 2 disposed on thefirst side 101 of thecircuit board 10 to thefirst side 101 of thecircuit board 10.

The fixedbody 1114 includes a plurality ofgroup receiving holes 1115, and eachgroup receiving hole 1115 is disposed through the fixedbody 1114. Eachgroup receiving hole 1115 is used for receiving a plurality ofelectrical connectors 2. The fixingbody 1114 further includes a plurality ofauxiliary fixing portions 1116, each of theauxiliary fixing portions 1116 is formed by extending a sidewall forming each of thegroup receiving holes 1115 toward the center of thegroup receiving hole 1115. When the fixingbody 1114 is fixed to thecircuit board 10, the height of eachauxiliary fixing portion 1116 relative to thecircuit board 10 is smaller than the depth of eachgroup accommodating hole 1115.

Each of thepressing structures 1112 and theauxiliary fixing portion 1116 may have a plurality of corresponding locking

holes

11121 and 1117, and each of thepressing structures 1112 may be anauxiliary fixing portion 1116 that is locked in each group-containinghole 1115 by a plurality of locking members (not shown), such as screws. When thepressing structure 1112 and theauxiliary fixing portion 1116 are locked together, thepressing structure 1112 will correspondingly press against thepressing portions 213 of theelectrical connector bodies 21 of theelectrical connectors 2 located in the group receiving holes 1115 (as shown in fig. 7 and described in detail later), and a portion of theelectrical connectors 2 is correspondingly exposed through the throughholes 1113 of thepressing structure 1112. As shown in fig. 6, in the present embodiment, when the first fixingmember 111 is fixed to thecircuit board 10, the side of thepressing structure 1112 opposite to thecircuit board 10 is lower than the side of the fixingbody 1114 opposite to thecircuit board 10, that is, the height from the side of thepressing structure 1112 opposite to thecircuit board 10 to the side of thecircuit board 10 where theelectrical connector 2 is disposed is lower than the height from the side of the fixingbody 1114 opposite to thecircuit board 10 to the side of thecircuit board 10 where theelectrical connector 2 is disposed, but not limited thereto; in various embodiments, thepressing structure 1112 on the side opposite to thecircuit board 10 may also be flush with the fixingbody 1114 on the side opposite to thecircuit board 10.

As described above, the first fixingmember 111 is fastened to thefirst side 101 of thecircuit board 10 by a plurality of fastening members, and the plurality ofpressing structures 1112 of the first fixingmember 111 correspondingly press a portion of eachelectrical connector 2, so that eachelectrical connector 2 can be directly fixed on thecircuit board 10 by the first fixingmember 111 in a pressing manner without using screws.

Referring to fig. 6 to 8, fig. 8 is an exploded view of an electrical connector and a circuit board of a chip testing device according to the present invention. On thefirst side 101 of thecircuit board 10, a plurality of sets ofelectrical contact structures 1011 are formed (only two sets ofelectrical contact structures 1011 are shown in fig. 8, but the number ofelectrical contact structures 1011 corresponds to the number of electrical sockets 2). Each set ofelectrical contact structures 1011 includes a plurality of contact pads 10111 (e.g., metal pads). When eachelectrical connection socket 2 is pressed by thepressing structure 1112 and fixed on thefirst side 101 of thecircuit board 10, one end of a plurality of probe elements 20 (described in detail later) of theelectrical connection socket 2 is correspondingly pressed against a plurality ofcontact pads 10111 included in the set ofelectrical contact structures 1011, so that the plurality ofprobe elements 20 of theelectrical connection socket 2 can be electrically connected to electronic components disposed on thecircuit board 10 through the plurality ofcontact pads 10111 when thechip testing apparatus 1 is powered. The number, arrangement, and disposition of theelectrical contact structures 1011, the number, shape, arrangement, and the like of thecontact pads 10111 of each set ofelectrical contact structures 1011 can be varied according to requirements, and are shown as an exemplary embodiment.

It should be noted that, in the above description of the present embodiment, thepressing structures 1112 and the fixingbody 1114 are taken as independent members, but in practical applications, thepressing structures 1112 and the fixingbody 1114 may be integrally formed, that is, the whole first fixingmember 111 is in a fence shape.

In practical applications, eachcontact pad 10111 may be substantially flatly formed on thefirst side 101 of thecircuit board 10, and for the convenience of the relevant personnel or machinery, eachelectrical connector 2 is correctly disposed on each set ofelectrical contact structures 1011, and thefirst side 101 of thecircuit board 10 may be recessed to form at least twopositioning holes 104 around each set ofelectrical contact structures 1011, where eachpositioning hole 104 is not disposed through thecircuit board 10. Correspondingly, eachelectrical connector 2 is configured to abut against one side of thefirst side surface 101 of thecircuit board 10, and may have apositioning element 25, and eachpositioning element 25 may be engaged with thepositioning hole 104, so that, through the mutual cooperation of thepositioning element 25 and thepositioning hole 104, a relevant person or machine can easily and correctly set theelectrical connector 2 on each set ofelectrical contact structures 1011. In practical applications, thepositioning element 25 and theelectrical connection socket 2 may be two independent components, or thepositioning element 25 may be integrally formed with thebase structure 231 of theelectrical connection socket 2.

As mentioned above, since eachelectrical connector 2 is fixedly disposed on thefirst side 101 of thecircuit board 10 only by the pressing of thepressing structure 1112, when assembling theelectrical connector 2, the first fixingmember 111, the second fixingmember 112 and thecircuit board 10, theelectrical connectors 2 must be disposed on thefirst side 101 of thecircuit board 10 first, and then the first fixingmember 111 is locked on thefirst side 101 of thecircuit board 10, in this process, eachelectrical connector 2 is limited by thepositioning element 25 and thepositioning hole 104, and eachelectrical connector 2 is not easy to move relative to thecircuit board 10, and related personnel or machinery can easily lock the first fixingmember 111 on thefirst side 101 of thecircuit board 10. The number of thepositioning members 25 disposed between the singleelectrical connector 2 and thecircuit board 10 is not limited to two in the drawings, and the number thereof can be changed according to the requirement, and the shapes of thepositioning members 25 and the positioning holes 104 can also be changed according to the requirement.

In summary, in thechip testing device 1 of the present invention, the first fixingmember 111 and the second fixingmember 112 are used to cooperate with the plurality of locking members to clamp and fix the plurality ofelectrical connection sockets 2 on thefirst side surface 101 of thecircuit board 10, so that theelectrical connection sockets 2 and thecircuit board 10 can not be locked with each other by the locking members, and thus, the number of through holes of thecircuit board 10 can be greatly reduced.

Referring to fig. 5 and 9, fig. 9 is an exploded view of a testing module, a circuit board and a second fixing member of the chip testing apparatus according to the present invention. Thecontrol unit 3 is disposed on thesecond side 102 of thecircuit board 10. Thecontrol unit 3 includes a plurality oftest modules 30, and eachtest module 30 is fixedly disposed on thesecond side 102 of thecircuit board 10. Thesecond fixing member 112 has a plurality ofrelief holes 1122. When the second fixingmember 112 is fixedly disposed on thesecond side surface 102 of thecircuit board 10, a portion of eachtest module 30 can be correspondingly disposed through the corresponding avoidinghole 1122.

In practical applications, thesecond side 102 of thecircuit board 10 may have a plurality offirst contact structures 1021. Eachtest module 30 may have atest module body 32 and twosecond contact structures 33, an electronic component for testing the chip C disposed on theelectrical connector 2 is disposed in thetest module body 32, thesecond contact structures 33 are exposed at one side of thetest module body 32, and thesecond contact structures 33 of eachtest module body 32 are used for contacting with thefirst contact structures 1021 of thecircuit board 10. When eachtest module 30 is fixedly disposed on thesecond side 102 of thecircuit board 10, thesecond contact structure 33 of eachtest module 30 passes through the corresponding avoidinghole 1122 to contact with thefirst contact structure 1021 of thecircuit board 10. The number of thesecond contact structures 33 included in eachtest module 30 is not limited to two, and the number of thesecond contact structures 33 may be varied according to requirements.

When thesecond contact structure 33 of eachtest module 30 contacts thefirst contact structure 1021 of thecircuit board 10, the associated electronic components in eachtest module 30 can be connected to the associated electronic components disposed on thecircuit board 10. In a specific application, thefirst contact structure 1021 and thesecond contact structure 33 may be, for example, a board-to-board connector, and the form of the first contact structure may be, for example, but not limited to, a Pogo pin or a reed. The number of thesecond contact structures 33 of eachtest module 30 is not limited to two, and may vary according to the type of thesecond contact structures 33.

Through the design of thefirst contact structure 1021 and thesecond contact structure 33, eachtesting module 30 can be detachably fixed on thesecond side 102 of thecircuit board 10, and through the design of detachably mounting eachtesting module 30 on thecircuit board 10, a user can replace thetesting module 30 as required, and related maintenance personnel can also easily disassemble, assemble and maintain aspecific testing module 30. As shown in fig. 5 and 9, in practical applications, thetest module body 32 may have twoauxiliary fixing structures 321, eachauxiliary fixing structure 321 may have a plurality of fixingholes 3211, and the second fixingmember 112 may have a plurality of corresponding fixing holes 1123. Each of thetesting module bodies 32 can be engaged with the fixingholes 3211 and the fixingholes 1123 by a plurality of fasteners (e.g., screws), so that thetesting module 30 can be detachably fixed on the second fixingmember 112. In practical applications, theauxiliary fixing structure 321 may be integrally formed with thetesting module body 32, or theauxiliary fixing structure 321 may be a member (e.g., a similar angle structure) independent from thetesting module body 32. Of course, thetest module body 32 is not limited to be locked to the second fixingmember 112 by screws, and any method that can detachably assemble thetest module body 32 to the second fixingmember 112 is within the scope of the present embodiment, for example, thetest module 30 and the second fixingmember 112 may have engaging structures that can engage with each other, and thetest module 30 may be fixed to the second fixingmember 112 by the engaging structures.

As shown in fig. 6, it is particularly described that, through the design of thepressing structures 1112 and the fixingbodies 1114, eachelectrical connector 2 is directly fixed on thecircuit board 10 in a pressing manner, and each set of electrical connector group is correspondingly pressed by one pressingstructure 1112, so that, when anyelectrical connector 2 fails, a related person only needs to remove a screw between thepressing structure 1112 and the fixingbody 1114 corresponding to theelectrical connector 2, and then can directly remove and replace theelectrical connector 2. That is, the design of thepressing structure 1112 and the fixingbody 1114 can allow the related maintenance personnel or machine to easily and quickly maintain, replace and install the specificelectrical connector 2.

When thetest modules 30 are powered, a predetermined test program can be performed on the chips C on theelectrical connectors 2, for example, the chips C can be various memories (for example, NAND Flash, etc.), and thetest modules 30 can perform at least one of a read test, a write test and an electrical test on the memories. In an embodiment where eachtest module 30 is used to test memory, thetest module body 32 of eachtest module 30 may include a Pattern Generator (PG), a Parametric Measurement Unit (PMU), a Device Power supply module (DPS), and a Driver circuit (Driver).

By the design of connecting theelectrical connectors 2 disposed on thecircuit board 10 todifferent test modules 30, thetest modules 30 and the chips C connected to theelectrical connectors 2 can transmit signals faster and less easily. More specifically, if thecircuit board 10 provided with 72electrical connection sockets 2 is connected to only one signal input source, when the signal emitted from the signal input source is transmitted from one side of thecircuit board 10 to the other side of thecircuit board 10, the signal is attenuated obviously, which may result in inaccurate chip test results.

In practical applications, all theelectrical connectors 2 in each electrical connector group may be connected in parallel, and all theelectrical connectors 2 connected in parallel in the same electrical connector group are connected to thesame test module 30; in other words, all theelectrical sockets 2 to which therespective test modules 30 are connected in parallel. In addition, anyelectrical connector 2 in each electrical connector group is not connected to anyelectrical connector 2 in other electrical connector groups. For example, suppose that fourelectrical connectors 2 are disposed on the circuit board 10: z1, Z2, Q1, Q2, fourelectrical sockets 2 are divided into two groups of electrical sockets, the first group includes Z1, Z2, the second group includes Q1, Q2, then Z1 and Z2 are connected in parallel, Q1 and Q2 are connected in parallel, Z1 is not connected with Q1 (whether in parallel or in series), Z1 is not connected with Q2 (whether in parallel or in series), Z2 is not connected with Q1 (whether in parallel or in series), and Z2 is not connected with Q2 (whether in parallel or in series).

As shown in fig. 5, in practical applications, thechip testing apparatus 1 may further include ahousing 31, thehousing 31 is fixedly disposed on the second fixingmember 112, and thehousing 31 correspondingly covers the plurality oftesting modules 30 to protect the plurality oftesting modules 30. In a specific implementation, thehousing 31 may also be provided with a related heat dissipation device, such as a fan, a heat dissipation fin, etc., according to requirements. In fig. 5 of the present embodiment, thechip testing apparatus 1 includes only asingle housing 31, and thehousing 31 correspondingly covers a plurality oftesting modules 30, but the number of thehousings 31 of thechip testing apparatus 1 is not limited to a single one, and in different applications, thechip testing apparatus 1 may also include a plurality ofhousings 31, and eachhousing 31 may be covered with asingle testing module 30 or two or threetesting modules 30.

As shown in fig. 4 to 6, the firstpower supplying member 4 is connected to thecircuit board 10, and the firstpower supplying member 4 may be connected to the plurality oftest modules 30 through thecircuit board 10. The firstpower supply member 4 may be, for example, a board-to-board connector, and may be, for example, but not limited to, a Pogo pin or a reed. In fig. 4 of the present embodiment, it is exemplified that the firstpower supply member 4 includes a plurality of connection terminals, and the firstpower supply member 4 is disposed on thefirst side surface 101 of thecircuit board 10 and exposed to the first fixingmember 111, but the form and number of the firstpower supply member 4, the position of the firstpower supply member 4 disposed on the circuit board, and the like are not limited to those shown in the drawings.

The firstpower supply member 4 is configured to be connected to a second power supply member (not shown) of the environment control device E3, and the power supply device connected to the environment control device E3 can supply power to eachtest module 30 through the second power supply member, the firstpower supply member 4, the plurality of first contact structures 1021 (shown in fig. 9) and the plurality of second contact structures 33 (shown in fig. 5), the power supply device is a power supply device independent from thechip testing apparatus 1, and the power supply device can be any device capable of providing power, which is not limited herein. That is, thechip testing apparatus 1 basically performs the predetermined test program on the plurality of chips C connected thereto without being connected to the power supply device through the first power supply means 4 by therespective test modules 30. Of course, in different embodiments, thechip testing apparatus 1 may also be provided with at least one battery, the battery is connected to the plurality oftesting modules 30, and the battery can supply power to the plurality oftesting modules 30.

In another embodiment, the first power supply means 4 may comprise a receiving antenna, and the first power supply means 4 can receive power wirelessly to provide power to eachtest module 30. In the embodiment where the first power supply means 4 is a receiving antenna, thechip testing device 1 may include a rechargeable battery module, and the first power supply means 4 is connected to the rechargeable battery module, and the first power supply means 4 can receive power wirelessly to charge the rechargeable battery module; in a specific implementation, the power required by eachtest module 30 to test the chip C carried by the test module may be provided from the rechargeable battery module and the power supply device through the receiving antenna (the first power supply member 4). In the embodiment where the firstpower supply member 4 is a receiving antenna, the firstpower supply member 4 may be disposed at a position not exposed to thechip testing apparatus 1, but embedded in thecircuit board 10 or hidden in thechip testing apparatus 1. In addition, the number of the firstpower supply members 4 of eachchip test apparatus 1 may be changed according to the requirements, and is not limited to a single one, and may be two or more.

Referring to fig. 11 to 14, fig. 11 is a schematic view of an electrical connection socket of a chip testing device disclosed in the present invention, fig. 12 is a schematic cross-sectional exploded view of the electrical connection socket of the chip testing device disclosed in the present invention, fig. 13 is a schematic cross-sectional view of the electrical connection socket of the chip testing device disclosed in the present invention without a chip, and fig. 14 is a schematic cross-sectional view of the electrical connection socket of the chip testing device disclosed in the present invention with a chip.

Eachelectrical connector socket 2 comprises: a plurality ofprobe assemblies 20, anelectrical connector body 21, a liftingstructure 22, a supportingstructure 23 and a plurality ofelastic assemblies 24. Eachprobe assembly 20 includes aneedle 201 and aspring 202. One end of thepin 201 is used to connect with the electrical connection C1 (shown in fig. 14) of the chip C. Thespring 202 is sleeved on theneedle body 201, and when one end of theneedle body 201 is pressed, thespring 202 is pressed to generate an elastic restoring force correspondingly, so that when theneedle body 201 is not pressed any more, theneedle body 201 is restored to an uncompressed position under the action of the elastic restoring force.

Theelectrical connector body 21 has atop wall 211, a ring-shapedsidewall 212 and a top 213. Thetop wall 211 has anopening 21A, one side of theannular side wall 212 is connected to the periphery of thetop wall 211, the other side of theannular side wall 212 is fixedly disposed on thecircuit board 10, and thetop wall 211, theannular side wall 212 and thecircuit board 10 together form a receivingslot 21B. Opposite sides of thetop wall 211 define anouter side 2111 and an inner side 2112 (shown in fig. 13). In practical applications, thetop wall 211 and theannular side wall 212 may be integrally formed.

Theannular sidewall 212 further protrudes outward to form a top 213. As shown in fig. 6 and 7, when thepressing structure 1112 is fixed to the fixingbody 1114, thepressing structure 1112 will correspondingly abut against the abuttingportion 213 of eachelectrical connector 2. That is, each abuttingportion 213 is disposed to facilitate the abutting of the abuttingstructure 1112, and the shape of the abuttingportion 213 may be designed to correspond to the abuttingstructure 1112 and the throughhole 1113.

The liftingstructure 22 includes abase 221 and a supportingportion 222. Thebase 221 is completely disposed in the receivinggroove 21B, thebase 221 extends toward one side to form a bearingportion 222, and a portion of the bearingportion 222 can pass through theopening 21A. The carryingportion 222 extends to a side away from thebase portion 221 to form four limitingportions 223, the four limitingportions 223 may be located at four corners of the carryingportion 222, and the four limitingportions 223 and the carryingportion 222 together form a chipaccommodating groove 22B, thechip accommodating groove 22B is used for providing a chip C, and the four limitingportions 223 are used for being mutually clamped with the chip C. The liftingstructure 22 further has a plurality ofconnection holes 22A (shown in fig. 12), and eachconnection hole 22A is disposed through thebase portion 221 and the bearingportion 222.

A portion of the plurality ofprobe assemblies 20 is fixedly disposed in the supportingstructure 23, and the plurality ofprobe assemblies 20 are fixedly disposed at one end of the supportingstructure 23 for connecting with the electrical contact structure 1011 (shown in fig. 8) of thecircuit board 10; the other ends of theprobe assemblies 20 are located in the connectingholes 22A, and one end of theprobe assembly 20 located in the connectingholes 22A is used to connect with the electrical connection portion C1 of the chip C.

In practical applications, the supportingstructure 23 may include abase structure 231 and anauxiliary structure 232. Thebase structure 231 is disposed in the receivingcavity 21B, and thebase structure 231 and theelectrical connector body 21 are fixed to each other (for example, fixed to theelectrical connector body 21 by matching with a plurality of screws). Thebase structure 231 has a plurality of throughholes 2311, and one end of the plurality ofprobe assemblies 20 is fixedly disposed in the plurality of throughholes 2311 of thebase structure 231. Theauxiliary structure 232 is disposed in the receivinggroove 21B, theauxiliary structure 232 is located between thebase structure 231 and thetop wall 211, and theauxiliary structure 232 and thebase structure 231 are fixed to each other (for example, fastened to each other by screws). Theauxiliary structure 232 has a plurality of supportingholes 2321 disposed at intervals, the supportingholes 2321 communicate with the throughholes 2311 of thebase structure 231, the supportingholes 2321 are disposed corresponding to the connectingholes 22A, the supportingholes 2321 and the throughholes 2311 together form a plurality of probe channels, and theprobe assemblies 20 are disposed in the probe channels.

As shown in fig. 8 and 12, it should be noted that thebase structure 231 may include a plurality ofpositioning holes 2312, and eachpositioning hole 2312 is used for passing through thepositioning element 25. In practical applications, the positioning holes 2312 may be disposed through thebase structure 231, but not limited thereto.

As shown in fig. 13, the supportingstructure 23 is disposed in theaccommodating groove 21B, and theelastic component 24 is disposed between the supportingstructure 23 and the liftingstructure 22. Theelastic assembly 24 enables thebase 221 of the liftingstructure 22 to abut against theinner side 2112 of thetop wall 211, and a gap S is correspondingly formed between the base 221 and the supportingstructure 23.

In practical applications, when theelectrical connector 2 is fixed on thecircuit board 10 and the limitingportion 223 of theelectrical connector 2 is not pressed by an external force, the fourelastic elements 24 located between the liftingstructure 22 and the supportingstructure 23 may be slightly compressed, and the elastic restoring force generated by the compression of theelastic elements 24 will make the liftingstructure 22 firmly abut against theinner side 2112 of thetop wall 211.

As shown in fig. 14, when the chip C is fixedly disposed in the chipaccommodating slot 22B and the liftingstructure 22 is not pressed, the electrical connection portions C1 of the chip C are correspondingly accommodated in the connection holes 22A, and theprobe assemblies 20 are not connected with the electrical connection portions C1 (e.g., do not contact each other). When the liftingstructure 22 is pressed, at least a portion of the liftingstructure 22 will be retracted into theelectrical connector body 21, that is, the liftingstructure 22 will move toward thecircuit board 10 relative to the supportingstructure 23, and theprobe assemblies 20 will be connected to the electrical connection portions C1 (shown in fig. 23) of the chip C.

Referring to fig. 7 again, in the embodiment shown in fig. 7, the number of the throughholes 1113 of thepressing structure 1112 is corresponding to the number of theelectrical connectors 2 located in the group of theaccommodating holes 1115, and when thepressing structure 1112 is located in the group of theaccommodating holes 1115, each throughhole 1113 of thepressing structure 1112 penetrates through a portion of oneelectrical connector 2. Referring to fig. 15, in various embodiments, the number of the throughholes 1113 of thepressing structure 1112 may not completely correspond to the number of theelectrical connectors 2. For example, thepressing structure 1112 may have only three throughholes 1113, and when thepressing structure 1112 presses theelectrical connectors 2 disposed in thegroup receiving hole 1115, each throughhole 1113 penetrates a portion of theelectrical connectors 2. In other words, the number or shape of the throughholes 1113 of thepressing structure 1112 may vary according to the requirement, and is not limited to the number and shape shown in fig. 7 or fig. 15.

Referring to fig. 15 and 16, when thepressing structure 1112 is the same as thepressing structure 1112 shown in fig. 15, the shape of eachelectrical connector 2 can be as shown in fig. 16. Theelectrical connector socket 2 shown in fig. 16 is largely different from theelectrical connector socket 2 shown in fig. 11 in that: the top 213 of eachelectrical connector 2 has a ring-shapedtop 2131, and the ring-shapedsidewall 212 is correspondingly located in the area surrounded by the ring-shapedtop 2131. When thepressing structure 1112 presses the plurality ofelectrical connectors 2 in thegroup receiving hole 1115, thepressing structure 1112 will press a portion of the annularpressing surface 2131 of eachelectrical connector 2.

Referring to fig. 13, 17 and 18, fig. 17 is a schematic diagram of an environment control apparatus of a chip testing system according to the present disclosure, and fig. 18 is a block schematic diagram of the environment control apparatus and a central control device of the chip testing system according to the present disclosure. A plurality of environment control devices E3 are connected to the central control unit E1, and the central control unit E1 can control any one of the environment control devices E3 to operate independently. Each of the environment control devices E3 is configured to perform a predetermined test procedure on the plurality of chips C disposed on thechip testing apparatus 1 in an environment with a predetermined temperature (e.g., a predetermined high temperature or a predetermined low temperature).

Each environmental control equipment E3 includes an equipment body E31. The apparatus body E31 includes a plurality of accommodation chambers E311. The containing chamber E311 is mainly used for containing thechip testing apparatus 1, and the containing chambers E311 included in the environmental control equipment E3 may be connected or not connected, which is not limited herein. In practical applications, the central control device E1 may include a plurality of environment state control devices (e.g., various microprocessors) and a central computer, and each environment state control device may be disposed in each environment control apparatus E3 and connected to the central computer.

It should be noted that in the embodiment where the plurality of chambers E311 included in the environmental control apparatus E3 are independent from each other and are not communicated with each other, each chamber E311 may be provided with a movable door, and the environmental control apparatus E3 may be connected with an air extractor E37. When thechip testing device 1 is disposed in the accommodating chamber E311, the central control device E1 can control the corresponding movable door to operate, so that the accommodating chamber E311 becomes a closed space, and then the central control device E1 can control the air extractor E37 to operate, so that the accommodating chamber E311 is in a state similar to vacuum, so that the temperature in the accommodating chamber E311 is not easily affected by the external environment.

In the embodiment where the firstpower supply member 4 of thechip testing apparatus 1 includes a plurality of connection terminals, a second power supply member may be disposed in each of the receiving chambers E311, the second power supply member may include a plurality of receiving chamber terminals E33 (corresponding to the first power supply member 4), and a plurality of receiving chamber terminals E33 may be connected to the plurality of connection terminals of thechip testing apparatus 1. The position of the housing terminal E33 may be designed according to the position of thechip testing apparatus 1 in the housing E311 and the positions of the plurality of connection terminals of the firstpower feeding member 4, and is not limited thereto. In the embodiment where the firstpower supply component 4 of thechip testing apparatus 1 is a receiving antenna for wireless charging, the second power supply component disposed in each receiving chamber E311 may correspond to a transmitting antenna for wireless charging, the transmitting antenna is connected to a power supply device, and when thechip testing apparatus 1 is disposed at a predetermined position in the receiving chamber E311, the transmitting antenna in the receiving chamber E311 can be coupled to the receiving antenna (the first power supply component 4) of thechip testing apparatus 1, and the power supply device can provide power to eachtesting module 30.

Each temperature adjustment device E34 is connected to the central control device E1, and each temperature adjustment device E34 can be controlled by the central control device E1 to make the ambient temperature of the chips C on the plurality ofelectrical connection sockets 2 of thechip testing device 1 in the corresponding accommodation chamber E311 reach a predetermined temperature.

In practical applications, the single thermostat E34 may have only heating coils or only fluid passages, and the temperature of the contact structure E341 of the single thermostat E34 will only rise to a predetermined high temperature or fall to a predetermined low temperature with the corresponding thermostat. That is, the single temperature adjustment device E34 can only raise the ambient temperature of the plurality of chips C carried by the correspondingchip testing device 1 to the predetermined high temperature or lower to the predetermined low temperature through the contact structure E341. More specifically, the temperature adjustment device E34 in the single chamber E311 can only make the chip C carried by thechip testing device 1 disposed therein at a predetermined high temperature or a predetermined low temperature, and if thechip testing device 1 needs to be at different temperature conditions, thechip testing device 1 must be moved to another chamber E311 by the related transfer device (e.g. a robot).

In another embodiment, the single thermostat E34 may also include two thermostats, for example, one thermostat of the single thermostat E34 may be a heating coil and the other thermostat may include a fluid channel for passing a cryogenic fluid, whereby the single thermostat E34 may be controlled to raise the temperature of the contact structure E341 to a predetermined high temperature or lower the temperature of the contact structure E341 to a predetermined low temperature. That is, after thechip testing device 1 is disposed in one of the accommodating chambers E311, the temperature adjusting device E34 can make the chip C carried by thechip testing device 1 contact the contact structure E341 reaching the predetermined high temperature first, and then make the chip C carried by thechip testing device 1 contact the contact structure E341 reaching the predetermined low temperature according to the testing requirement; alternatively, the chip C carried by thechip testing apparatus 1 is first contacted with the contact structure E341 reaching the predetermined low temperature, and then the chip C carried by thechip testing apparatus 1 is contacted with the contact structure E341 reaching the predetermined high temperature.

The frame E35 of the temperature adjustment device E34 is disposed around the contact structure E341, and a contact surface E3411 of the contact structure E341 may be disposed flush with a ring pressing surface E351 of the frame E35, and the ring pressing surface E351 is correspondingly disposed with an elastic annular sealing member E36. In different embodiments, the contact surface E3411 may be higher than the ring pressing surface E351, but the contact surface E3411 is not lower than the ring pressing surface E351. An elastic annular seal E36 is disposed on the annular pressing surface E351, and an elastic annular seal E36 is disposed around the contact structure E341. The elastic ring-shaped sealing element E36 may be made of rubber or other material capable of returning to its original shape under pressure, and is not limited herein; as for the cross-sectional shape of the elastic annular seal E36, for example, it may be circular, oval, trapezoidal, etc., without limitation.

Referring to fig. 19 and 20, fig. 20 is a partial cross-sectional view of thechip testing apparatus 1. Under the condition that thechip testing device 1 is not pressed by the temperature adjusting device E34, atop surface 11141 of the fixingbody 1114 of the first fixingmember 111 is flush with theouter side surface 2111 of eachelectrical connector body 21, and a portion of the liftingstructure 22 of eachelectrical connector 2 is disposed higher than thetop surface 11141. That is, when each chip C is disposed in theelectrical connection socket 2 and thechip testing device 1 is not pressed by the temperature adjustment device E34, a portion of the liftingstructure 22 may be disposed higher than thetop surface 11141; the chip C disposed in the liftingstructure 22 may be higher than the withstandingsurface 11141 or not higher than the withstandingsurface 11141, which is not limited herein.

Referring to fig. 17 and 21, fig. 21 is a schematic cross-sectional view of the temperature adjustment device E34 pressing against thechip testing device 1. When thechip testing apparatus 1 is moved to one of the accommodating chambers E311 by a moving device (e.g., a robot), the lifting device E38 disposed in the accommodating chamber E311 is controlled by the central control device E1, so that thechip testing apparatus 1 moves toward the temperature adjustment device E34 until one side of the chips C carried by thechip testing apparatus 1 is pressed by the contact structure E341 of the temperature adjustment device E34. As shown in fig. 21, when the contact structure E341 presses against a side surface of the chips C carried by thechip testing apparatus 1, a portion of the contact structure E341 will simultaneously press against thetop surface 11141 of the fixingbody 1114, and the elastic ring-shaped sealing member E36 is correspondingly pressed against thetop surface 11141 of the fixingbody 1114, and the contact structure E341, the fixingbody 1114, thepressing structure 1112 and thecircuit board 10 will together form a closed space SP in which theelectrical connectors 2 are correspondingly located.

When the contact structure E341 presses against a side of the chips C carried by thechip testing apparatus 1 and theelectrical connectors 2 are correspondingly located in the enclosed space SP, the central control apparatus E1 can control the air extractor E37 to extract air in the enclosed space SP, so that the enclosed space SP is in a state similar to vacuum, and during the process of extracting air by the air extractor E37, thechip testing apparatus 1 will be under the action of negative pressure and pressed against the temperature regulator E34 more tightly. As shown in fig. 19 and 22, fig. 22 is a partially enlarged schematic view of fig. 19. In practical applications, an air-extracting gap H may be formed between the contact structure E341 and the frame E35, the air-extracting gap H may be disposed around the contact structure E341, and the frame E35 may be formed with a plurality of air-extracting holes E352, the air-extracting holes E352 are communicated with the air-extracting gap H (for example, the frame E35 has corresponding passages therein), and the air-extracting holes E352 are used for communicating with the air-extracting device E37. In the embodiment, the air-extracting gap H is disposed to substantially surround the contact structure E341, but the specific forming position and shape of the air-extracting gap H are not limited thereto, as long as the enclosed space SP can be communicated with the air-extracting device E37 through the air-extracting gap H and the air-extracting hole E352. In addition, the number, shape and arrangement position of the air pumping holes E352 can be changed according to requirements.

It should be noted that, in practical applications, after thechip testing apparatus 1 is disposed in one of the accommodating chambers E311, the central control device E1 may control the lifting device E38 to move a predetermined distance, so that thechip testing apparatus 1 moves to a position contacting with the temperature adjustment device E34, i.e., the elastic annular sealing member E36 contacts with the abuttingtop surface 11141 of thechip testing apparatus 1; then, the central control device E1 can control the air extractor E37 and the lifting device E38 to operate together, so that the enclosed space SP gradually assumes a state similar to vacuum, and at the same time, the contact structure E341 will press against the liftingstructure 22 of eachelectrical socket 2, so that each liftingstructure 22 retracts into the correspondingelectrical socket 2.

As shown in fig. 21 and 23, fig. 23 is a partially enlarged schematic view of a single electrical connection socket pressed by a contact structure, when the contact structure E341 presses against the liftingstructure 22 of eachelectrical connection socket 2 to retract each liftingstructure 22 into the correspondingelectrical connection socket 2, the plurality ofprobe assemblies 20 in eachelectrical connection socket 2 are correspondingly connected with the plurality of electrical connection portions C1 of the chip C. When theprobe assemblies 20 are connected to the electrical connections C1 of the chip C, the connection terminals of the first power supply member 4 (shown in fig. 6) are correspondingly connected to the chamber terminals E33 (shown in fig. 18) of the chamber E311 (shown in fig. 17), and thetest modules 30 are powered, so that the central control device E1 can control thetest modules 30 to perform a predetermined test procedure on the chip C on theelectrical connector 2 connected thereto.

In practical applications, the central control device E1 controls the air extracting device E37, and the time point of extracting the air in the enclosed space SP can be designed according to the requirement. For example, the central control device E1 may determine whether thechip testing device 1 is already disposed at a predetermined position in the accommodating chamber E311 by at least one sensor (e.g., an optical sensor or a mechanical pressing sensor) disposed in the accommodating chamber E311 (as shown in fig. 17), and the central control device E1 controls the air extractor E37 to operate to extract the air in the enclosed space SP when thechip testing device 1 is determined to be located at the predetermined position in the accommodating chamber E311 by the sensor.

As shown in fig. 19 and 20, by the design that theouter side surface 2111 of eachelectrical connection socket 2 is flush with theabutting surface 11141, the contact surface E3411 of the contact structure E341 is flush with the ring abutting surface E351 (or the contact surface E3411 is not lower than the ring abutting surface E351), the elastic annular sealing element E36 is disposed on the ring abutting surface E351, and the like, the acting force required by the lifting device E38 to abut against thechip testing device 1 can be greatly reduced by the operation of the air extractor E37. More specifically, the elevating device E38 is to make thechip testing device 1 approach the contact structure E341 of the temperature adjusting device E34, and make the contact structure E341 contact the chips C on the plurality ofelectrical sockets 2 at the same time. As previously explained, when the contact structure E341 contacts the chips C on a plurality ofelectrical sockets 2 simultaneously, the lifting device E38 will have to resist the elastic restoring force generated by the compression of theelastic component 24 from eachelectrical socket 2 and the elastic restoring force generated by the compression of eachprobe component 20 in eachelectrical socket 2; therefore, the air in the enclosed space SP is evacuated by the air evacuation device E37 to make the enclosed space SP in a negative pressure state, so that the force required for pushing the lifting device E38 against thechip testing device 1 can be greatly reduced.

In particular, according to the above description of thechip testing device 1, since only the circuitboard locking hole 103 is disposed through thecircuit board 10 of thechip testing device 1, when the temperature adjusting device E34 abuts against the first fixingmember 111, the sealing performance of the enclosed space SP is easily controlled, and the air exhausting device E37 is relatively easy to reach a state of approximately vacuum in the process of exhausting the air in the enclosed space SP outwards. That is, in thechip testing apparatus 1 according to the present invention, the number of through holes in thecircuit board 10 is significantly reduced by the design of the first fixingmember 111, the second fixingmember 112, and the like, so that the closed space SP can be relatively easily brought into a vacuum state when the air extracting device E37 extracts air from the closed space SP.

Referring to fig. 1 and 2 again, the transfer equipment E4 is disposed between the environmental control equipments E3, and the transfer equipment E4 is used for carrying thechip testing apparatus 1. The transfer apparatus E4 may comprise a robot and a holding component for holding thechip testing device 1. The central control device E1 is connected to the transfer facility E4, and the central control device E1 can control the transfer facility E4 to set thechip testing apparatus 1 carrying a plurality of chips C in any of the accommodation chambers E311 (see fig. 17) of any of the environment control facilities E3. In contrast, the transfer device E4 may be controlled by the central control device E1 to move thechip testing apparatus 1 disposed in any of the accommodating chambers E311 out of the accommodating chamber E311.

The sorting apparatus E5 is connected to the central control device E1, and the sorting apparatus E5 can be controlled by the central control device E1 to detach the chips C from theelectrical connectors 2 of thechip testing apparatus 1, and the sorting apparatus E5 can place the chips C on a tray of a good area a1 or a tray of a defective area a2 according to the test results of the chips C after passing a predetermined test procedure. The sorting device E5 may for example comprise a robot arm. In an embodiment where the sorting apparatus E5 and the chip mounting apparatus E2 are disposed at adjacent positions, the chip mounting apparatus E2 and the sorting apparatus E5 may share the same robot arm. In practical applications, the good area a1 may be divided into a plurality of areas according to requirements, and the sorting apparatus E5 may arrange the chips C in different areas of the good area a1 according to the test results of the chips C after passing through the predetermined test procedures, for example, the chips C may be distinguished according to the operation performance of the chips C.

Fig. 24 is a schematic flow chart of a chip testing method according to a first embodiment of the present invention. The chip test system E may perform a predetermined test procedure on the plurality of chips C by using a chip test method including:

a chip mounting step S1: transferring a plurality of chips (C) from a carrying tray to a plurality of electric connection seats (2) of a chip testing device (1) by a chip mounting device (E2);

a shift to step S2: transferring a chip testing device (1) carrying a plurality of chips (C) to one of the accommodating chambers (E311) of one of the environment control devices (E3);

a temperature adjustment step S3: controlling a temperature adjusting device (E34) in the accommodating chamber (E311) to operate so that the plurality of chips (C) are in an environment with a preset temperature;

a test step S4: supplying power to a chip testing device (1) arranged in the accommodating chamber (E311) so that each testing module (30) performs a preset testing program on a plurality of chips (C) connected with the testing module;

a shift-out step S6: removing the chip testing device (1) from the accommodating chamber (E311), and transferring the chip testing device (1) to a sorting device (E5);

a classification step S7: a sorting device (E5) is used for placing a plurality of chips (C) into a good product area (A1) or a defective product area (A2) respectively according to the test results of the chips (C) after the chips (C) complete the predetermined test procedures.

In the embodiment where the first power supply means 4 of thechip testing device 1 includes a plurality of connection terminals, before the testing step S4, a connection step may be further included: the plurality of connection terminals of the firstpower feeding member 4 of thechip testing apparatus 1 are connected to the plurality of housing chamber terminals E33 provided in the housing chamber E311. In an embodiment, the connection step may be located between the moving-in step S2 and the temperature adjustment step S3, or the connection step may be located between the temperature adjustment step S3 and the test step S4.

Fig. 25 is a schematic flow chart of a chip testing method according to a second embodiment of the present invention. The biggest difference between this embodiment and the embodiment shown in fig. 24 is that: an air-extracting step S21 may be further included between the moving step S2 and the temperature adjusting step S3. In the moving-in step S2, the elastic ring-shaped sealing member E36 of the temperature adjustment device E34 disposed in the accommodating chamber E311 is connected to thecircuit board 10 of thechip testing apparatus 1, so that the temperature adjustment device E34 and thecircuit board 10 together form the enclosed space SP (as shown in fig. 21), and then, in the air-extracting step S21, the air-extracting device E37 connected to the enclosed space SP is operated to extract the air in the enclosed space SP.

As shown in fig. 21 and described in the corresponding embodiment, when the temperature adjustment device E34 and thecircuit board 10 together form the enclosed space SP, eachelectrical connector socket 2 is correspondingly located in the enclosed space SP. After the air-extracting step S21 is performed, eachelectrical connector 2 will be located in a near vacuum environment, so that, when the temperature adjusting step S3 is performed subsequently, the temperature of the enclosed space SP will not be affected by the external environment, and the ambient temperature of theelectrical connector 2 and the chip C carried thereby will be easily maintained at the predetermined temperature.

Fig. 26 is a schematic flow chart of a chip testing method according to a third embodiment of the present invention. The present embodiment is different from the previous embodiments in the following point: between the test step S4 and the shift-out step S6, the following steps may be included:

a separation step S5: after the chip testing device (1) completes a predetermined testing procedure for all the chips (C) connected with the chip testing device, the first power supply member (4) of the chip testing device (1) is controlled to be separated from the plurality of accommodating chamber terminals (E33) in the accommodating chamber (E311).

As shown in fig. 3, 17 and 18, in practical applications, the environmental control apparatus E3 may further include a plurality of lifting devices E38, and each of the accommodating chambers E311 is provided with one lifting device E38. Each of the elevating devices E38 is connected to an environmental condition control device of the central control device E1. Each of the elevating devices E38 is controlled by the central control device E1 to elevate thechip testing apparatus 1 disposed in the accommodating chamber E311, so that the plurality of connection terminals of the firstpower supply member 4 of thechip testing apparatus 1 and the accommodating chamber terminal E33 are connected to or separated from each other.

In practical applications, when eachchip testing apparatus 1 is transferred into the accommodating chamber E311 by the transfer apparatus E4, the firstpower supply members 4 of thechip testing apparatus 1 may not be connected to the accommodating chamber terminals E33, and when the central control apparatus E1 determines that achip testing apparatus 1 is disposed in any one of the accommodating chambers E311, the central control apparatus E1 may control the corresponding lifting apparatus E38 to move thechip testing apparatus 1 in the accommodating chamber E311, so that the connection terminals of the firstpower supply members 4 are connected to the accommodating chamber terminals E33, whereby the power supply apparatus can provide power to thetest modules 30 through the firstpower supply members 4.

In the embodiment where the firstpower supply component 4 is a receiving antenna, when thechip testing apparatus 1 is disposed in the accommodating chamber E311, the corresponding transmitting antenna in the accommodating chamber E311 may be coupled to the receiving antenna, and thechip testing apparatus 1 may obtain power through the firstpower supply component 4. Of course, in another embodiment, the receiving antenna may be coupled to the receiving antenna when thechip testing device 1 is disposed at a predetermined position in the accommodating chamber E311, which is not limited herein.

In practical applications, before the temperature adjusting step S3, the central control device E1 controls the air extracting device E37 to extract air from the enclosed space SP so that the enclosed space SP is in a state close to vacuum, and thus, after the temperature adjusting step S3, the temperature in the enclosed space SP is not easily affected by the external environment.

In the testing step S4, thechip testing apparatus 1 is coupled or connected to the corresponding transmitting antenna or the receiving chamber terminal through the receiving antenna or the plurality of connecting terminals, so as to obtain power, and eachtesting module 30 can test the chip C connected thereto.

As shown in fig. 17 and 18, in practical applications, in order to firmly connect the plurality of connection terminals of the firstpower supply member 4 of thechip testing apparatus 1 and the plurality of receiving chamber terminals E33 to each other, the environmental control device E3 may further include a plurality of position-limiting devices E39, and the plurality of position-limiting devices E39 are disposed in the plurality of receiving chambers E311. Each of the stopper devices E39 is connected to a central control device E1. Each of the position-limiting devices E39 can be controlled by the central control device E1 to limit the moving range of thechip testing device 1 in the accommodating chamber E311. The specific structure of the position-limiting device E39 can be designed according to the requirement, for example, thechip testing device 1 can be provided with a locking hole, and the position-limiting device E39 includes a corresponding hook structure, when the position-limiting device E39 is actuated, the hook structure can be correspondingly locked in the locking hole; alternatively, the stopper E39 may include a plurality of retractable pins, and the retractable pins may be inserted into the engaging holes of thechip testing apparatus 1.

In the embodiment that each of the accommodation chambers E311 of each of the environmental control apparatuses E3 has the contact structure E341, the lifting device E38 and the position-limiting device E39, the chip testing method may include the following steps in the moving step S2:

a step of moving into the accommodating chamber: moving the chip testing device (1) into the accommodating chamber (E311);

a rising step: controlling a lifting device (E38) in the accommodating chamber (E311) to move the chip testing device (1) towards the contact structure (E341);

a locking step: controlling a limiting device (E39) in the accommodating chamber (E311) to enable the limiting device (E39) to limit the moving range of the chip testing device (1) in the accommodating chamber (E311).

In summary, the chip testing method of the present invention may be that a plurality of chips are mounted on thechip testing device 1; next, thechip testing apparatus 1 is moved into one of the accommodating chambers E311 of the environmental control device E3; then, controlling the lifting device E38 to lift thechip testing device 1 so that one side of the chips C of thechip testing device 1 is adjacent to the contact structure E341 of the temperature adjusting device E34, and the elastic annular sealing member E36 of the temperature adjusting device E34 is pressed against thecircuit board 10 of thechip testing device 1 to form a closed space SP; subsequently, the air extractor E37 is controlled to extract air from the enclosed space SP, so that one side of the chips C on thechip testing apparatus 1 is attached to the contact structure E341, and the temperature regulator E34 is controlled to operate, so that the chips C reach a predetermined temperature; when the temperature adjusting device E34 is activated, power is supplied to thechip testing apparatus 1 so that the plurality oftest modules 30 test the plurality of chips C.

Referring to fig. 27, which is a flowchart illustrating a fourth embodiment of the chip testing method according to the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeatedly performed twice, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, and the testing step S42, respectively.

In the temperature adjusting step S31 and the testing step S41 (i.e., the temperature adjusting step S3 and the testing step S4 are executed for the first time), the temperature adjusting device E34 corresponding to the accommodating chamber E311 is controlled to enable the chips C to be in an environment with a temperature above 115 ℃, and then eachtesting module 30 is controlled to perform at least one of a read test, a write test and an electrical test on the chips C. The temperature adjustment step S31 and the test step S41 are performed to Burn-In (Burn-In) the memory.

In the temperature adjusting step S32 and the testing step S42 (i.e., the temperature adjusting step S3 and the testing step S4 are executed for the second time), the temperature adjusting device E34 corresponding to the accommodating chamber E311 is controlled to enable the chips C to be in an environment with a temperature of 75 ℃ to 95 ℃, and then eachtesting module 30 is controlled to perform at least one of a read test, a write test and an electrical test on the chips C. The temperature adjustment step S32 and the test step S42 are performed to test the memory at a high temperature.

Specifically, in various embodiments, the test step S41 and the temperature adjustment step S32 may include a shift-out step and a shift-in step; the moving-out step is to move thechip testing device 1 out of the current chamber E311, and the moving-in step is to move thechip testing device 1 into another chamber E311. That is, thechip testing apparatus 1 can be sequentially located in two different chambers E311 (which can be located in the same environmental control equipment E3 or in different environmental control equipment E3) with a temperature above 115 ℃ and a temperature between 75 ℃ and 95 ℃ for testing.

Referring to fig. 28, which is a flowchart illustrating a fifth embodiment of the chip testing method according to the disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 27 in the following point: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeated three times, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, the testing step S42, the temperature adjusting step S33 and the testing step S43, respectively.

After the temperature adjusting step S32 and the testing step S42 are performed, the temperature adjusting step S33 and the testing step S43 (i.e., the temperature adjusting step S3 and the testing step S4 are performed for the third time) are performed by controlling the temperature adjusting device E34 corresponding to the accommodating chamber E311 to make the chips C in the environment with the temperature of-55 ℃ to-35 ℃, and then controlling eachtesting module 30 to perform at least one of the read test, the write test and the electrical test on the chips C. In other words, the chip testing method disclosed In this embodiment sequentially performs a Burn-In (Burn-In) test, a high temperature test, and a low temperature test on the plurality of chips C.

Referring to fig. 29, which is a flowchart illustrating a sixth embodiment of the chip testing method according to the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 28 in the following point: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeated four times, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, the testing step S42, the temperature adjusting step S33, the testing step S43, the temperature adjusting step S34, and the testing step S44, respectively.

After the temperature adjusting step S33 and the testing step S43 are performed, the temperature adjusting step S34 and the testing step S44 (i.e., the temperature adjusting step S3 and the testing step S4 are performed for the fourth time) are performed by controlling the temperature adjusting device E34 corresponding to the accommodating chamber E311 to make the chips C in the environment with the temperature of 20 ℃ to 30 ℃ (normal temperature), and then controlling eachtesting module 30 to perform at least one of the read test, the write test and the electrical test on the chips C. In other words, the chip testing method disclosed In this embodiment sequentially performs a Burn-In (Burn-In) test, a high temperature test, a low temperature test, and a normal temperature test on the plurality of chips C.

As described above, the chip testing method of the present embodiment may be performed by using the chip testing system E in which the temperature adjustment devices E34 of the environment control apparatuses E3 are controlled to increase the temperature of the contact structure E341 and also controlled to decrease the temperature of the contact structure E341 in the foregoing description. After thechip testing apparatus 1 is moved into the accommodating chamber E311 of the environment control device E3, at least one of a read test, a write test, and an electrical test is sequentially performed In an environment at a temperature of 115 ℃ or higher, an environment at a temperature of 75 ℃ to 95 ℃, an environment at a temperature of-55 ℃ to-35 ℃, and an environment at a temperature of 20 ℃ to 30 ℃, that is, a Burn-In (Burn-In) test, a high temperature test, a low temperature test, and a normal temperature test are sequentially performed on the plurality of chips C. Of course, In practical applications, thechip testing apparatus 1 may perform the Burn-In (Burn-In) test, the high temperature test, the low temperature test and the normal temperature test on the plurality of chips C In the sequence, which may be arranged according to the requirement, and is not limited to the above sequence.

Referring to fig. 30, which is a flowchart illustrating a chip testing method according to a seventh embodiment of the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 27 in the following point: the following steps may be included between the shift-out step S6 and the sorting step S7:

a move-in step SX 1: transferring a chip testing apparatus (1) carrying a plurality of chips (C) to an accommodating chamber (E311) of another environment control device (E3);

a temperature adjustment step SX 2: controlling a temperature adjusting device (E34) in the accommodating chamber (E311) to operate so that the plurality of chips (C) are in an environment of-55 ℃ to-35 ℃;

a test step SX 3: power is supplied to a chip testing device (1) arranged in the accommodating chamber (E311) so that each testing module (30) performs a predetermined testing procedure on a plurality of chips (C) connected with the testing module.

In the chip testing method of the present embodiment, thechip testing apparatus 1 is first disposed in the accommodating chamber E311 of one of the environment control devices E3, and the plurality of chips C are sequentially subjected to at least one of a read test, a write test, and an electrical test in an environment with a temperature of 115 ℃ or higher and in an environment with a temperature of 75 ℃ to 95 ℃; then, thechip testing apparatus 1 is moved out of the containing chamber E311, and thechip testing apparatus 1 is moved into one of the containing chambers E311 of different environmental control devices E3 (or moved into another containing chamber E311 of the same environmental control device E3); subsequently, the temperature control device E34 of the accommodating chamber E311 operates to make the plurality of chips C carried by thechip testing apparatus 1 in an environment with a temperature of-55 ℃ to-35 ℃ for at least one of a read test, a write test and an electrical test.

The chip testing method of the present embodiment may be performed by using the chip testing system E in the foregoing description, and particularly, the temperature adjusting devices E34 of the environment control devices E3 may be controlled only to raise or lower the temperature of the contact structure E341.

In the chip testing method of the present embodiment, since the temperature of the single accommodating chamber E311 is not decreased from the temperature of more than 100 ℃ to the temperature of less than 0 ℃, the time required for the temperature around each chip C to reach the predetermined high temperature and the predetermined low temperature can be greatly shortened, and the energy consumed for the temperature adjusting devices E34 to reach the predetermined temperature in the accommodating chamber E311 can be greatly reduced.

As shown in fig. 31, which is a flowchart illustrating an eighth embodiment of the chip testing method disclosed in the present invention, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: after the temperature adjustment step SX2 and the test step SX3, a temperature adjustment step SX4 and a test step SX5 may be further included. In the temperature adjusting step SX4, the temperature adjusting device E34 in the accommodating chamber E311 is controlled to operate, so that the plurality of chips C are in an environment of 20 ℃ to 30 ℃. In the testing step SX5, power is supplied to thechip testing apparatus 1 disposed in the accommodating chamber E311, so that eachtesting module 30 performs a predetermined testing procedure on the plurality of chips C connected thereto. That is, in the temperature adjustment step SX2 and the test step SX3, the plurality of chips C are tested in a low temperature environment, and in the temperature adjustment step SX4 and the test step SX5, the plurality of chips C are tested in a normal temperature environment.

It should be noted that, in different embodiments, after eachtest module 30 completes a predetermined test program for the chips C on theelectrical connectors 2 connected thereto, thetest module 30 may write the test result data and the corresponding test parameters of each chip C into each chip C, so that the test result data and the test parameter data are stored in each chip C. More specifically, the test result data may include, for example: the test conditions of the chip C in the high temperature test, the pre-burning test, the low temperature test and the normal temperature test may be respectively determined, or only whether the chip C passes the high temperature test, the pre-burning test, the low temperature test and the normal temperature test may be recorded. In a specific chip testing method, after each of the testing steps S41, S42, S43, S44 (as shown in fig. 29), the following steps may be respectively included: a test result writing step: and storing the test result data after each memory completes the preset test program and the corresponding test parameter data in each memory.

The test parameter data may for example comprise: an identification Number (ID Number) of thechip testing apparatus 1, an identification Number of thetest module 30, an identification Number of theelectrical connector 2, an identification Number of the environmental control device E3 and an identification Number of the housing chamber E311 thereof, a temperature value at the time of high temperature test, a temperature value at the time of burn-in test, a temperature value at the time of low temperature test, a temperature value at the time of normal temperature test, and the like.

Through the above design that thetest module 30 writes the test result data and the test parameter data of the chip C into the chip C, when any chip C is handed to a consumer, the consumer can read the data stored in the chip C through the related device to confirm the detection state during the production; and when the relevant production personnel receive any chip C returned by the consumer, the detection process of the chip C can be quickly traced by reading the test result data and the test parameter data stored in the chip C, so that the production personnel can be effectively helped to find out the possible defects in the detection process.

In different embodiments, the chip testing method may also include, after the classifying step S7 (as shown in fig. 29): a test result writing step: and storing the test result data after each memory completes the preset test program and the corresponding test parameter data in each memory. Specifically, when the memory carried by thechip testing apparatus 1 completes all tests (for example, burn-in test and high temperature test, or burn-in test, high temperature test, low temperature test, and normal temperature test) according to the requirements, the central control apparatus E1 may first control the sorting device E5 to sort each memory according to the test result of each memory. Then, the central control device E1 controls the related read/write device to perform the related read/write operation on the memories classified into the good area a1, so as to store the corresponding test result data and the corresponding test parameter data in each memory. That is, only the memory divided into good memory is stored with the test result data and the test parameter data.

The chip testing method may also include, before the classifying step S7 (shown in fig. 29): a test result writing step: and storing the memory passing through each preset test program, the corresponding test result data and the corresponding test parameter data in the corresponding memory. Specifically, when the memory carried by thechip testing device 1 is tested according to the requirements and passes all tests (such as a burn-in test and a high-temperature test, or a burn-in test, a high-temperature test, a low-temperature test, and a normal-temperature test), thechip testing device 1 writes the test result corresponding to the memory and the related test parameter data into the memory; on the contrary, if the memory fails at least one of the tests, thechip testing apparatus 1 will not write any test-related data corresponding to the memory into the memory. Thus, in the classifying step S7, the classifying device may rapidly determine whether the memory passes the test by determining whether any of the test-related data is written in the memory, and if the classifying device determines that the data is not written in the memory, the classifying device may directly classify the memory into the defective area.

In addition, it should be emphasized that in any of the above embodiments in which the power supply member includes a plurality of connection terminals, the connection terminals and the housing chamber terminals can be directly replaced by the receiving antenna and the transmitting antenna. Of course, since the receiving antenna and the transmitting antenna are wirelessly used for power transmission, the related process steps of contacting or separating the connecting terminal and the accommodating chamber terminal in some embodiments can be omitted when the connecting terminal and the accommodating chamber terminal are directly replaced by the receiving antenna and the transmitting antenna.

In summary, the chip testing system, the chip testing apparatus and the chip testing method applied to the chip testing system disclosed by the invention have the advantages of cost and better testing efficiency compared with the existing chip testing equipment. In addition, the chip testing system disclosed by the invention has the advantages that the plurality of chips are arranged on the chip testing device, then the chip testing device is moved to enable the chips to be in different temperature environments for carrying out related testing operations, therefore, the chips are arranged on the same chip testing device in the testing process in different temperature environments, the chips cannot be repeatedly disassembled and assembled in the whole testing process, and the chips are not easy to have unexpected damage and other problems. In contrast, in the conventional memory detection device, the memory is repeatedly detached and mounted on the electrical connection socket in different temperature environments, so that the memory is easily damaged unexpectedly after repeated detachment and mounting.

The disclosure is only a preferred embodiment of the invention and is not intended to limit the scope of the invention, so that all equivalent technical changes made by using the contents of the specification and the drawings are included in the scope of the invention.

Claims

1. An environmental control apparatus, wherein the environmental control apparatus is used to perform a predetermined test procedure on a plurality of chips disposed on a chip testing device in an environment with a predetermined high temperature or a predetermined low temperature, the chip testing device includes at least a first power supply component, the environmental control apparatus is connected to an air extractor, the environmental control apparatus includes:

the equipment body comprises a plurality of accommodating chambers; each accommodating chamber is internally provided with at least one second power supply component, and the equipment body is connected with power supply equipment; when the chip testing device is arranged in one of the accommodating chambers, the power supply equipment can supply power to the chip testing device through the first power supply component and the second power supply component;

the environment state control device is connected with the equipment body;

a plurality of temperature adjusting devices connected to the environmental condition control device, one temperature adjusting device being provided in each of the accommodating chambers, each temperature adjusting device including:

at least one temperature regulator;

at least one contact structure having a contact surface for contacting a side surface of the plurality of chips carried by the chip testing apparatus; the temperature regulator can be controlled to raise the temperature of the contacting structure to the predetermined high temperature, and the temperature regulator can also be controlled to lower the temperature of the contacting structure to the predetermined low temperature;

the frame body is arranged around the contact structure and provided with a ring abutting surface which is flush with the contact surface, or the contact surface is higher than the ring abutting surface;

an elastic annular sealing element arranged on the ring abutting surface; when the contact surface is contacted with one side surface of a plurality of chips carried by the chip testing device, the elastic annular sealing element is correspondingly pressed against the chip testing device, and a closed space is correspondingly formed between the contact structure and the chip testing device; the air extraction device can be controlled to extract air in the closed space outwards;

wherein each of said temperature adjustment devices is controllable by said ambient condition control device to operate independently of the other of said temperature adjustment devices;

when the chip testing device is arranged in one of the accommodating chambers, the contact structure abuts against one side surface of the chips carried by the chip testing device, the chip testing device is powered on, the contact structure reaches the preset high temperature or the preset low temperature, and the air in the closed space is pumped out by the air pumping device, the chip testing device can be controlled to carry out the preset testing program on the chips carried by the chip testing device.

2. The environmental control apparatus according to claim 1, further comprising a plurality of position limiting devices, one position limiting device being disposed in each of the receiving chambers, each position limiting device being connected to the environmental condition control device; each limiting device can be controlled by the environment state control device and is mutually connected with the chip testing device arranged in the accommodating chamber, so that the moving range of the chip testing device in the accommodating chamber is limited.

3. The environmental control apparatus according to claim 1, further comprising a plurality of lifting devices, one lifting device being disposed in each of the receiving chambers, each lifting device being connected to the environmental condition control device; each lifting device can be controlled by the environment state control device, so that the chip testing device arranged in the accommodating chamber moves in the accommodating chamber.

4. The environmental control apparatus according to claim 1, wherein the environmental control apparatus further comprises the chip testing device, the chip testing device comprising:

at least one circuit board, wherein two opposite side surfaces of the circuit board are respectively defined as a first side surface and a second side surface; the circuit board is provided with a plurality of positioning holes and a plurality of circuit board locking holes, each positioning hole does not penetrate through the circuit board, and each circuit board locking hole penetrates through the circuit board;

a fixing assembly, including a first fixing member and a second fixing member, wherein the first fixing member is fixedly disposed on the first side surface, the second fixing member is fixedly disposed on the second side surface, the first fixing member has a plurality of first locking holes, the second fixing member has a plurality of second locking holes, and the plurality of first locking holes, the plurality of circuit board locking holes and the plurality of second locking holes are correspondingly disposed; the circuit board is fixed between the first fixing component and the second fixing component;

the electric connection seats are provided with an electric connection seat body; one side of each electric connection seat body is used for bearing one chip, the other side of each electric connection seat body is provided with at least two positioning pieces, each positioning piece is mutually clamped with the plurality of positioning holes, and each electric connection seat is arranged on the first side surface of the circuit board; the first fixing member comprises a plurality of abutting structures, the plurality of abutting structures are correspondingly abutted against a part of the plurality of electric connecting seats, each electric connecting seat is abutted against and fixed on the first side surface of the electric connecting seat by the first fixing member, the first fixing member comprises a plurality of through holes, and a part of each electric connecting seat is correspondingly exposed out of each through hole;

the control unit is arranged on the second side face of the circuit board and comprises a plurality of test modules, and each test module is connected with one part of the electric connecting seats; the second fixing component is provided with a plurality of avoidance holes, and a part of the plurality of test modules penetrates through the avoidance holes; and

the first power supply component is connected with the circuit board;

wherein the chip testing device must be connected with the power supply device through the first power supply member to obtain the power required by the operation of each of the test modules.

5. The environmental control apparatus according to claim 4, wherein each of the test modules comprises: the device comprises a graph generator, a component power supply module and a driving circuit; the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection seats are partitioned into a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the plurality of test modules are connected with the electric connecting seats of the plurality of electric connecting seat groups, and each test module is connected with all the electric connecting seats in the corresponding electric connecting seat group.

6. The environmental control apparatus according to claim 5, wherein the first fixing member further comprises a fixing body, each of the pressing structures is detachably fixed to the fixing body, each of the fixing bodies has a plurality of group receiving holes, and each of the group receiving holes is configured to receive a plurality of electrical connectors in the same electrical connector group.

7. The environmental control apparatus according to claim 6, wherein the circuit board has a plurality of first contact structures on the second side, each of the test modules has at least one second contact structure, and the second contact structure of each of the test modules is detachably contactable with one of the first contact structures.

8. The environmental control apparatus according to claim 4, wherein the first power supply member includes a plurality of connection terminals, the plurality of connection terminals being provided on the first side surface of the circuit board, and the plurality of connection terminals being exposed to the first fixing member; the second power supply member in each of the housing chambers includes a plurality of housing chamber terminals; the plurality of connecting terminals are used for being connected with the plurality of accommodating chamber terminals in the accommodating chambers; when a plurality of the connection terminals are connected with a plurality of the accommodation chamber terminals in one of the accommodation chambers, the power supply device can supply power to the chip testing device.

9. The environmental control apparatus according to claim 4, wherein the first power supply means is a receiving antenna, the second power supply means is a transmitting antenna, the receiving antenna is configured to be mutually coupled with the transmitting antenna, and the chip testing device is configured to wirelessly receive the power transmitted by the power supply apparatus through the receiving antenna.

10. The environmental control apparatus according to claim 4, wherein the chip testing device further comprises at least a first data transmission terminal disposed on the circuit board and exposed from the first fixing member; each accommodating chamber also comprises at least one second data transmission terminal; the first data transmission terminals are used for being in contact with the second data transmission terminals in the containing chambers to transmit data to each other.

11. The environmental control apparatus according to claim 4, wherein the chip testing device further comprises at least a first data transmission antenna; the equipment body also comprises at least one second data transmission antenna; the first data transmission antenna is used for wirelessly transmitting data with the second data transmission antenna.

12. The environmental control apparatus according to claim 4, wherein after each of the test modules completes the predetermined test procedure for the chips on the plurality of electrical connectors connected thereto, the test module writes test result data and test parameter data of each of the chips into the chip, so that each of the chips stores the test result data and the test parameter data.

13. The environmental control apparatus of claim 4, wherein each electrical connector comprises:

the base body is provided with a top wall and an annular side wall, the top wall is provided with an opening, one end of the annular side wall is connected with the periphery of the top wall, the other end of the annular side wall is abutted against the circuit board, and a containing groove is formed by the top wall, the annular side wall and the circuit board together; two opposite side surfaces of the top wall are defined as an outer side surface and an inner side surface, and the inner side surface is positioned in the accommodating groove; one side of the top wall opposite to the circuit board is defined as an outer side face, and the outer side face is flush with a butting face of the first fixing member opposite to the circuit board;

the supporting structure is abutted against the circuit board and is positioned in the accommodating groove, the supporting structure comprises a plurality of positioning holes, and each positioning hole is provided with one positioning piece;

the lifting structure is arranged in the accommodating groove and is provided with a base part and a bearing part, the base part is positioned in the accommodating groove, the base part extends towards one side to form the bearing part, and at least one part of the bearing part is positioned in the opening; the bearing part extends towards one side far away from the base part to form a plurality of limiting parts, at least one part of the limiting parts penetrates through the opening, a chip containing groove is formed by the limiting parts and the bearing part together, and the chip containing groove is used for containing the chip; the lifting structure is also provided with a plurality of connecting holes which penetrate through the base part and the bearing part;

at least one elastic component, which is arranged in the containing groove, one end of each elastic component is fixed on the lifting structure, the other end of each elastic component is fixed on the supporting structure, the elastic restoring force generated by the compression of the elastic components enables the base part to be abutted against the inner side surface of the top wall, and a gap is formed between the lifting structure and the supporting structure;

one end of each probe assembly is fixedly arranged on the supporting structure, the other end of each probe assembly abuts against the electric contact structure of the circuit board, and the other ends of the probe assemblies penetrate through the connecting holes;

when the chip accommodating groove is provided with the chip and the limiting part is not pressed by the contact structure, the probe assemblies positioned in the connecting holes are not connected with the contact parts of the chip, and part of the lifting structure protrudes out of the outer side surface of the top wall;

when the chip accommodating groove is provided with the chip, the limiting part is pressed by the contact structure to retract towards the base body, and the elastic annular sealing element and the abutting top surface of the first fixing component are pressed against each other, the plurality of probe assemblies abut against the electric contact structure of the circuit board.

14. The environmental control apparatus according to claim 1, wherein at least one air exhaust gap is formed between the frame body of each of the temperature adjustment devices and the contact structure, the frame body has at least one air exhaust hole, the air exhaust hole is communicated with the air exhaust gap, and the air exhaust device can exhaust the air in the closed space to the outside through the air exhaust hole and the air exhaust gap.

15. A chip test system, comprising:

the chip testing device is used for bearing a plurality of chips and comprises at least one first power supply component;

a central control device, said central control device including an environmental status control device; and

at least one environmental control apparatus, the environmental control apparatus is connected to an air extractor, the environmental control apparatus includes:

the equipment body comprises a plurality of accommodating chambers; each accommodating chamber is internally provided with at least one second power supply component, and the equipment body is connected with power supply equipment; when the chip testing device is arranged in one of the accommodating chambers, the power supply equipment can supply power to the chip testing device through the first power supply component and the second power supply component; and

at least one temperature regulator;

the frame body is arranged around the contact structure and provided with a ring abutting surface which is flush with the contact surface, or the contact surface is higher than the ring abutting surface; and

when the chip testing device is arranged in one of the accommodating chambers, the contact structure abuts against one side surface of the chips carried by the chip testing device, the chip testing device is powered, the contact structure reaches the preset high temperature or the preset low temperature, and the air in the closed space is pumped out by the air pumping device, the chip testing device can be controlled to carry out the preset testing program on the chips carried by the chip testing device.

16. The chip testing system according to claim 15, wherein the environmental control apparatus further comprises a plurality of position-limiting devices, one position-limiting device being disposed in each of the receiving chambers, each position-limiting device being connected to the environmental condition control device; each limiting device can be controlled by the environment state control device and is mutually connected with the chip testing device arranged in the accommodating chamber, so that the moving range of the chip testing device in the accommodating chamber is limited.

17. The chip testing system according to claim 15, wherein the environmental control apparatus further comprises a plurality of lifting devices, one lifting device is disposed in each of the accommodating chambers, and each lifting device is connected to the environmental condition control device; each lifting device can be controlled by the environment state control device, so that the chip testing device arranged in the accommodating chamber moves in the accommodating chamber.

18. The chip test system according to claim 15, wherein the environmental control apparatus further comprises the chip test device, the chip test device comprising:

the first power supply component is connected with the circuit board;

19. The chip test system according to claim 18, wherein each of the test modules comprises: the device comprises a graph generator, a component power supply module and a driving circuit; the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection seats are partitioned into a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the plurality of test modules are connected with the electric connecting seats of the plurality of electric connecting seat groups, and each test module is connected with all the electric connecting seats in the corresponding electric connecting seat group.

20. The chip testing system of claim 19, wherein the first fixing member further comprises a fixing body, each of the pressing structures is detachably fixed to the fixing body, each of the fixing bodies has a plurality of group receiving holes, and each of the group receiving holes is configured to receive a plurality of electrical connectors in the same electrical connector group.

21. The chip test system according to claim 20, wherein the circuit board has a plurality of first contact structures on the second side, each of the test modules has at least one second contact structure, and the second contact structure of each of the test modules is detachably contactable with one of the first contact structures.

22. The chip test system according to claim 18, wherein the first power supply member comprises a plurality of connection terminals, the plurality of connection terminals are disposed on the first side surface of the circuit board, and the plurality of connection terminals are exposed to the first fixing member; the second power supply member in each of the housing chambers includes a plurality of housing chamber terminals; the plurality of connecting terminals are used for being connected with the plurality of accommodating chamber terminals in the accommodating chambers; when a plurality of the connection terminals are connected with a plurality of the accommodation chamber terminals in one of the accommodation chambers, the power supply device can supply power to the chip testing device.

23. The chip testing system according to claim 18, wherein the first power supplying means is a receiving antenna, the second power supplying means is a transmitting antenna, the receiving antenna is configured to be mutually coupled with the transmitting antenna, and the chip testing apparatus is configured to wirelessly receive the power transmitted by the power supplying device through the receiving antenna.

24. The chip testing system according to claim 18, wherein the chip testing device further comprises at least a first data transmission terminal disposed on the circuit board and exposed from the first fixing member; each accommodating chamber also comprises at least one second data transmission terminal; the first data transmission terminals are used for being in contact with the second data transmission terminals in the containing chambers to transmit data to each other.

25. The chip test system according to claim 18, wherein the chip test apparatus further comprises at least a first data transmission antenna; the equipment body also comprises at least one second data transmission antenna; the first data transmission antenna is used for wirelessly transmitting data with the second data transmission antenna.

26. The system for testing chips of claim 18 wherein, after each of said test modules completes said predetermined test procedure on said chips on said plurality of electrical connectors connected thereto, said test modules writes test result data and test parameter data of each of said chips into said chips so that each of said chips stores test result data and test parameter data therein.

27. The chip test system according to claim 18, wherein each of the electrical connectors comprises:

28. The system for testing chips of claim 15 wherein at least one air-extracting gap is formed between the frame body and the contact structure of each of the temperature adjustment devices, the frame body has at least one air-extracting hole, the air-extracting hole is communicated with the air-extracting gap, and the air-extracting device can extract air in the enclosed space through the air-extracting hole and the air-extracting gap.