Step 2, on the premise of ensuring the maximum transmitting power (+26dBm) of the time division duplex carrier, according to the maximum transmitting power difference delta P of the frequency division duplex carrier_{PowerClassFDD}The maximum transmit power of the frequency division duplex carrier is reduced such that a maximum scheduled time slot of the frequency division duplex carrier is allowed to exceed a maximum time slot limit (MaxUplinkDuty).

In some embodiments of the present disclosure, the super uplink power control method may further include: and performing power control so that the maximum transmission power difference of the frequency division duplex carrier meets a preset formula (2).

In some embodiments of the present disclosure, the predetermined formula (2) may be: upper limit P of actual transmitting power of terminal_{CMAX_H,f,c}Equal to the first transmission power value and the maximum transmission power P of the base station configuration terminal_EMAXWherein the first transmission power value is equal to the actual maximum transmission power P of the terminal frequency division duplex carrier_{PowerClassFDD}Maximum transmitting power difference delta P of sum frequency duplex carrier_{PowerClassFDD}The difference of (a).

P_{CMAX_H,f,c}＝MIN{P_EMAX,c,P_{PowerClassFDD}–ΔP_{PowerClassFDD}} (2)

The super uplink power control method provided by the above embodiment of the present disclosure can be applied to the field of 5G communication. The embodiment of the disclosure provides a mechanism for controlling the super uplink transmission power of a terminal, and when the scheduling time slot proportion of an FDD carrier exceeds the limit of a Duty Cycle (Duty Cycle), the embodiment of the disclosure can dynamically adjust the maximum transmission power capability of the FDD carrier terminal, and ensure that the average power meets the SAR regulation requirement by reducing the power. The embodiment of the disclosure can fully exert the capacity capability of the super uplink in the center of the cell.

Fig. 2 is a schematic diagram of some embodiments of the terminal of the present disclosure. As shown in fig. 2, the terminal of the present disclosure may include a powerdifference determining module 21 and apower adjusting module 22, wherein:

a powerdifference determination module 21 for determining a frequency division duplex carrierWave maximum transmission power difference delta P_{PowerClassFDD}。

In some embodiments of the present disclosure, the frequency division duplex carrier maximum transmit power difference Δ P_{PowerClassFDD}A difference between the adjusted maximum transmit power and the current maximum transmit power may be desired.

In some embodiments of the present disclosure, the powerdifference determination module 21 may be configured to obtain a normalized total maximum transmission timeslot limit MaxUplinkDuty_totalPractical time slot uplink Duty scheduling of time division duplex carrier_TDDAnd actual scheduling time slot uplink Duty of frequency division duplex carrier_FDD(ii) a MaxUplinkdity limited according to normalized total maximum transmit time slot_totalPractical time slot uplink Duty scheduling of time division duplex carrier_TDDAnd actual scheduling time slot uplink Duty of frequency division duplex carrier_FDDAnd determining the maximum transmitting power difference of the frequency division duplex carrier.

In some embodiments of the present disclosure, the powerdifference determination module 21 limits maxuplinkdity according to the normalized total maximum transmission timeslot_totalPractical time slot uplink Duty scheduling of time division duplex carrier_TDDAnd actual scheduling time slot uplink Duty of frequency division duplex carrier_FDDAnd the method can be used for limiting MaxUpLinkDuty according to the normalized total maximum transmission time slot under the condition of determining the maximum transmission power difference of the frequency division duplex carrier_totalPractical time slot uplink Duty scheduling of time division duplex carrier_TDDAnd actual scheduling time slot uplink Duty of frequency division duplex carrier_FDDDetermining a first transmit power difference; taking the inverse number of the first transmission power difference value and the minimum value of 0 as the maximum transmission power difference delta P of the frequency division duplex carrier_{PowerClassFDD}。

In some embodiments of the present disclosure, the powerdifference determination module 21 limits maxuplinkdity according to the normalized total maximum transmission timeslot_totalPractical time slot uplink Duty scheduling of time division duplex carrier_TDDAnd actual scheduling time slot uplink Duty of frequency division duplex carrier_FDDIn the case of determining the first transmit power difference value, it may be used to limit the normalized total maximum transmit time slot to maxuplinkdity_totalActual scheduling with twice time division duplex carrierTime slot uplink duty_TDDDifference of (a) and the actual scheduled time slot uplink duty of the frequency division duplex carrier_FDDThe ratio of (a) is taken as a first ratio; and taking 10 times of logarithm of the base-10 of the first ratio as the first transmission power difference value.

In some embodiments of the present disclosure, the powerdifference determining module 21 may be configured to determine the maximum transmission power difference Δ P of the frequency division duplex carrier according to formula (1)_{PowerClassFDD}。

Apower adjustment module 22, configured to guarantee the maximum transmit power (+26dBm) of the tdd carrier according to the maximum transmit power difference Δ P of the fdd carrier_{PowerClassFDD}The maximum transmit power of the frequency division duplex carrier is reduced such that a maximum scheduled time slot of the frequency division duplex carrier is allowed to exceed a maximum time slot limit (MaxUplinkDuty).

In some embodiments of the present disclosure, thepower control module 22 may be further configured to perform power control such that the frequency division duplex carrier maximum transmission power difference satisfies a predetermined formula (2).

P_{CMAX_H,f,c}＝MIN{P_EMAX,c,P_{PowerClassFDD}–ΔP_{PowerClassFDD}} (2)

In some embodiments of the present disclosure, the terminal may be configured to perform an operation for implementing the super uplink power control method according to any of the above embodiments (for example, the embodiment of fig. 1).

Based on the terminal provided by the above embodiment of the present disclosure, a scheme for calculating and reducing the maximum transmission power based on the current scheduling time slot is designed, so that the scheme for reducing the ratio of the average power to the time slot is guaranteed to be equivalent to the SAR limit.

The terminal in the above embodiments of the present disclosure mainly aims to reduce the maximum transmit power of an FDD carrier and obtain more schedulable time slot resources, and is specifically designed as follows: the terminal reduces the maximum transmitting power delta P of the FDD carrier wave according to the formula (1) on the premise of ensuring the maximum transmitting power (+26dBm) of the TDD carrier wave_{PowerClassFDD}Therefore, the maximum schedulable time slot of the FDD carrier is allowed to exceed the maximum time slot (MaxUpLinkDuty) limit, and the total transmission power can meet the SAR regulation requirement of the region.

Fig. 3 is a schematic diagram of other embodiments of the terminal of the present disclosure. As shown in fig. 3, the disclosed terminal may include amemory 31 and aprocessor 32, wherein:

amemory 31 for storing instructions.

Aprocessor 32, configured to execute the instructions, so that the terminal performs operations to implement the super uplink power control method according to any one of the embodiments (for example, the embodiment in fig. 1) described above.

The inventor finds that: the existing 3GPP standard research focuses on a standardized solution to the SAR problem of a high-power terminal with 23dBm +23dBm, and focuses on ensuring the overall high-power performance of the system. And therefore do not involve a power reduction scheme. This is different from the case of 23dBm +26dBm, for the cell-centric scenario, there is a case where 23dBm FDD carrier power reduction guarantees schedulable time slots, which is hardly discussed in the 3GPP standard.

The above embodiment of the present disclosure is directed to a solution to the SAR problem of super uplink with 23dBm +26dBm, and the advantages of the above embodiment of the present disclosure are as follows: making full use of relevant technical parameter delta P_{PowerClassFDD}And the parameter is assigned as a constant in the standard and is applied to the areas where high power is forbidden to reduce the transmitting power of the high-power terminal. The method is expanded to dynamically adjust the power of the terminal in the above embodiment scheme of the present disclosure, so that the method can meet the application of different scenes. The design principle of the above embodiment of the disclosure reduces standard change as much as possible, and can be popularized as a new standard。

According to another aspect of the present disclosure, a computer-readable storage medium is provided, where the computer-readable storage medium stores computer instructions, and the instructions, when executed by a processor, implement the super uplink power control method according to any one of the embodiments (for example, the embodiment of fig. 1) above.

Based on the computer readable storage medium provided by the above embodiment of the present disclosure, the FDD carrier can be made to be used to the maximum extent under the super uplink specification by reducing power to obtain more schedulable timeslot resources.

The embodiment of the disclosure can reduce the maximum power, and ensure that the average power meets the requirements of SAR regulations by reducing the power, thereby fully exerting the capacity capability of the super uplink in the center of the cell. The above-described embodiments of the present disclosure propose Δ P by improvement_{PowerClassFDD}Equation (1) to dynamically adjust the maximum transmit power of the FDD carrier.

The terminals described above may be implemented as a general purpose processor, a Programmable Logic Controller (PLC), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any suitable combination thereof, for performing the functions described herein.

Thus far, the present disclosure has been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware to implement the above embodiments, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disk, or the like.

The description of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to practitioners skilled in this art. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A super uplink power control method, comprising:

2. The super uplink power control method according to claim 1, wherein the determining the maximum transmit power difference of the fdd carriers comprises:

3. The method of claim 2, wherein the determining the maximum transmit power difference of the fdd carrier according to the normalized total maximum transmit timeslot limit, the tdd carrier actual scheduling timeslot, and the tdd carrier actual scheduling timeslot comprises:

4. The method of claim 3, wherein the determining the first transmit power difference based on the normalized total maximum transmit time slot limit, the tdd carrier actual scheduling time slot, and the tdd carrier actual scheduling time slot comprises:

5. The super uplink power control method according to any one of claims 1 to 4, further comprising:

6. The super uplink power control method according to claim 5,

the predetermined formula is: and the upper limit of the actual transmitting power of the terminal is equal to the minimum value between the first transmitting power value and the maximum transmitting power of the terminal configured by the base station, wherein the first transmitting power value is equal to the difference value between the actual maximum transmitting power of the frequency division duplex carrier of the terminal and the maximum transmitting power of the frequency division duplex carrier.

7. A terminal, comprising:

8. The terminal of claim 7, wherein the terminal is configured to perform operations for implementing the super uplink power control method according to any one of claims 1 to 6.

9. A terminal, comprising:

a memory to store instructions;

a processor configured to execute the instructions to cause the terminal to perform operations to implement the super uplink power control method according to any one of claims 1 to 6.

10. A computer-readable storage medium storing computer instructions which, when executed by a processor, implement the super uplink power control method according to any one of claims 1 to 6.