Disclosure of Invention
In view of the above problems, an object of an embodiment of the present invention is to provide a method for improving a read/write speed, a device for improving a read/write speed, and a NAND flash memory, so as to solve the problem of slow read/write speed in a manner that an SRAM reads/writes a register in the prior art.
In order to solve the above problems, an embodiment of the present invention discloses a method for improving read/write speed, applied to a NAND flash memory, where the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charge selection signals corresponding to the N register areas one to one, periods of the N charge selection signals include delay times, there are time delays between the N charge selection signals, and the delay times in the N charge selection signal periods are overlapped and then equal to total delay times of register selection signal routing of the N register areas, the method includes:
receiving a register address;
Determining a register area to be subjected to read-write operation according to the register address;
and setting the charging selection signal corresponding to the register area to be subjected to read-write operation to be effective.
Optionally, the determining the register area to be subjected to the read-write operation according to the register address includes:
And determining the register area to be subjected to read-write operation according to the high-K bit address of the register address, wherein N=2K.
Optionally, the falling edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is after the falling edge of the register selection signal of the Mth register in the register area to be subjected to the read-write operation, and the Mth register is the furthest register of the register selection signal lines in the register area to be subjected to the read-write operation.
Optionally, the rising edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is before the rising edge of the register selection signal of the first register in the register area to be subjected to the read-write operation, and the first register is a register with the nearest register selection signal routing in the register area to be subjected to the read-write operation.
In order to solve the above-mentioned problems, the embodiment of the present invention further discloses a device for improving read-write speed, which is applied to a NAND flash memory, where the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charge selection signals corresponding to the N register areas one by one, periods of the N charge selection signals include delay times, there are time delays between the N charge selection signals, and the delay times in the N charge selection signal periods are overlapped and then equal to a total delay time of register selection signal routing of the N register areas, where the device includes:
The receiving module is used for receiving the register address;
the register area determining module is used for determining a register area to be subjected to read-write operation according to the register address;
The setting module is used for setting the charging selection signal corresponding to the register area to be subjected to the read-write operation to be effective.
Optionally, the register area determining module includes:
And the register area determining unit is used for determining the register area to be subjected to read-write operation according to the high-K bit address of the register address, wherein N=2K.
Optionally, the falling edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is after the falling edge of the register selection signal of the Mth register in the register area to be subjected to the read-write operation, and the Mth register is the furthest register of the register selection signal lines in the register area to be subjected to the read-write operation.
Optionally, the rising edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is before the rising edge of the register selection signal of the first register in the register area to be subjected to the read-write operation, and the first register is a register with the nearest register selection signal routing in the register area to be subjected to the read-write operation.
In order to solve the above problems, the embodiment of the present invention further discloses a NAND flash memory, where the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one to one, periods of the N charging selection signals include delay times, time delays exist between the N charging selection signals, and the delay times in the N charging selection signal periods are overlapped and then equal to total delay times of register selection signal routing lines of the N register areas.
Optionally, the N register areas are the same in size, the delay time difference of the charging selection signals corresponding to two adjacent register areas is the total delay time/N of the register selection signal routing, and the total delay time of the register selection signal routing is the delay of the register selection signal routing between the register closest to the register selection signal routing and the register farthest from the register selection signal routing in the N register areas.
The embodiment of the invention has the advantages that the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals corresponding to the N register areas one by one, the period of the N charging selection signals comprises delay time, the N charging selection signals have time delay, and the total delay time of the register selection signal wiring of the N register areas is equal to the sum of the delay time in the N charging selection signal periods. After receiving the register address, determining a register area to be subjected to read-write operation according to the register address, and further setting a charging selection signal corresponding to the register area to be subjected to read-write operation to be effective. Therefore, the invention selects the charging selection signals in regions through the register addresses, the delay time in the charging selection signal period is far less than the wiring delay, the time for reading and writing the register by the SRAM is effectively reduced, the speed for reading and writing the register by the SRAM is greatly improved, the read-write frequency on a high-capacity NAND flash memory interface is conveniently improved, and the realization is simple.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 3, a step flow diagram of an embodiment of a method for improving a read/write speed of the present invention is shown, where the method for improving a read/write speed is applied to a NAND flash memory, the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charge selection signals corresponding to the N register areas one by one, periods of the N charge selection signals include delay times, time delays exist between the N charge selection signals, and the sum of the delay times in the N charge selection signal periods is equal to a total delay time of register selection signal routing of the N register areas. Wherein, N register areas are transversely distributed in a row in turn. N is an integer greater than or equal to 2.
Optionally, when the sizes of the N register areas are the same, the delay time difference of the charging selection signals corresponding to the adjacent two register areas is the total delay time/N of the register selection signal routing. The total delay time of the register selection signal wires is the delay of the register selection signal wire between the register with the nearest register selection signal wire and the register with the farthest register selection signal wire in the N register areas.
For example, assuming that the N register areas are four register areas, and the four register areas have the same size, and the total delay time of the register selection signal traces of the four register areas is tdly, the period of the N charge selection signals includes a delay time of tdly/4, and the delay time difference of the charge selection signals corresponding to the adjacent two register areas is tdly/4, at this time, the period of the N charge selection signals is reduced by 3tdly/4.
Referring to fig. 3, the method may specifically include the steps of:
S1, receiving a register address.
The register address is a read-write address of the register.
S2, determining a register area to be subjected to read-write operation according to the register address.
For example, assuming that the N register areas are 2 register areas (a first register area and a second register area), if the register address is the address of the first register area, step S2 determines that the register area to be subjected to the read/write operation is the first register area, and if the register address is the address of the second register area, step S2 determines that the register area to be subjected to the read/write operation is the second register area.
S3, setting a charging selection signal corresponding to a register area to be subjected to read-write operation to be effective.
Specifically, although the delay time in the charge selection signal period corresponding to the register area to be read/write operated in step S3 is much smaller than the total delay time of the wirings, since the size of the register area to be read/write operated is much smaller than the size of all registers in the NAND flash memory, the delay of the register selection signal wiring between the register closest to the register and the register farthest from the register selection signal wiring is also much smaller than the total delay time of the wirings. Therefore, after step S3, the SRAM can still correctly read and write the register area to be read and written. The delay time in the charging selection signal period corresponding to the register area to be subjected to read-write operation is far smaller than the total delay time of the wiring, and the method for improving the read-write speed effectively reduces the time for reading and writing the register of the SRAM and greatly improves the speed for reading and writing the register of the SRAM.
Alternatively, in another embodiment of the present invention, referring to fig. 4, step S2 of determining a register area to be subjected to a read/write operation according to a register address may include:
S21, determining a register area to be subjected to read-write operation according to a high-K bit address of the register address, wherein N=2K.
For example, if n=2, i.e., the NAND flash memory includes 2 register areas (first register area and second register area), k=1. At this time, if the high-K bit address of the register address is 0, the step S21 determines that the register area to be subjected to the read/write operation is the first register area, if the high-K bit address of the register address is 1, the step S21 determines that the register area to be subjected to the read/write operation is the second register area, or if the high-K bit address of the register address is 1, the step S21 determines that the register area to be subjected to the read/write operation is the first register area, and if the high-K bit address of the register address is 0, the step S21 determines that the register area to be subjected to the read/write operation is the second register area.
Optionally, in one embodiment of the present invention, the falling edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is after the falling edge of the register selection signal of the mth register in the register area to be subjected to the read-write operation, where the mth register is a register with the farthest register selection signal trace in the register area to be subjected to the read-write operation. Therefore, when the register area to be subjected to read-write operation is subjected to read-write operation, the condition that the charging selection signal and the register selection signal are simultaneously effective can be avoided, and data in the register can be protected.
Optionally, in an embodiment of the present invention, a rising edge of a charging selection signal corresponding to a register area to be subjected to a read/write operation is before a rising edge of a register selection signal of a first register in the register area to be subjected to the read/write operation, where the first register is a register with a nearest register selection signal trace in the register area to be subjected to the read/write operation. Therefore, when the register area to be subjected to read-write operation is subjected to read-write operation, the condition that the charging selection signal and the register selection signal are simultaneously effective can be avoided, and data in the register can be protected.
The method for improving the read-write speed has the advantages that the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals corresponding to the N register areas one by one, the period of the N charging selection signals comprises delay time, time delay exists among the N charging selection signals, and the total delay time of the register selection signal wiring of the N register areas is equal to the sum of the delay time in the N charging selection signal periods. After receiving the register address, determining a register area to be subjected to read-write operation according to the register address, and further setting a charging selection signal corresponding to the register area to be subjected to read-write operation to be effective. Therefore, the invention selects the charging selection signals in regions through the register addresses, the delay time in the charging selection signal period is far smaller than the wiring delay, even if the Page capacity of NAND FLASH and the total delay time of the register selection signal wiring of N register areas are very large, the time for reading and writing the register of the SRAM can be effectively reduced, the speed for reading and writing the register of the SRAM is greatly improved, the read-write frequency on a high-capacity NAND flash memory interface is conveniently improved, and the realization is simple.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Referring to fig. 5, a block diagram of an embodiment of an apparatus for improving a read/write speed of the present invention is shown, where the apparatus for improving a read/write speed is applied to a NAND flash memory, the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charge selection signals corresponding to the N register areas one by one, periods of the N charge selection signals include delay times, and there is a time delay between the N charge selection signals, and the sum of the delay times in the N charge selection signal periods is equal to a total delay time of register selection signal traces of the N register areas. Wherein N is an integer greater than or equal to 2.
Optionally, in an embodiment of the present invention, N register areas are the same in size, and a delay time difference of the charging selection signals corresponding to two adjacent register areas is a total delay time/N of the register selection signal routing. The total delay time of the register selection signal wires is the delay of the register selection signal wires between the register with the nearest register selection signal wire and the register with the farthest register selection signal wire in the N register areas.
Referring to fig. 5, the apparatus for improving a read/write speed may specifically include the following modules:
A receiving module 1, configured to receive a register address.
The register area determining module 2 is used for determining a register area to be subjected to read-write operation according to the register address.
The setting module 3 is configured to set the charging selection signal corresponding to the register area to be subjected to the read-write operation to be valid.
Alternatively, in another embodiment of the present invention, referring to fig. 6, the register area determining module 2 may include:
The register area determining unit 21 is configured to determine a register area to be subjected to a read/write operation according to a high K bit address of the register address, where n=2K.
Optionally, in one embodiment of the present invention, the falling edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is after the falling edge of the register selection signal of the mth register in the register area to be subjected to the read-write operation, where the mth register is a register with the farthest register selection signal trace in the register area to be subjected to the read-write operation.
Optionally, in an embodiment of the present invention, a rising edge of a charging selection signal corresponding to a register area to be subjected to a read/write operation is before a rising edge of a register selection signal of a first register in the register area to be subjected to the read/write operation, where the first register is a register with a nearest register selection signal trace in the register area to be subjected to the read/write operation.
The device for improving the read-write speed has the advantages that the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals corresponding to the N register areas one by one, the period of the N charging selection signals comprises delay time, time delay exists among the N charging selection signals, and the total delay time of the register selection signal wiring of the N register areas is equal to the total delay time of the register selection signal wiring of the N register areas after the delay time in the N charging selection signal periods is overlapped. After receiving the register address, determining a register area to be subjected to read-write operation according to the register address, and further setting a charging selection signal corresponding to the register area to be subjected to read-write operation to be effective. Therefore, the invention selects the charging selection signals in regions through the register addresses, the delay time in the charging selection signal period is far smaller than the wiring delay, even if the Page capacity of NAND FLASH and the total delay time of the register selection signal wiring of N register areas are very large, the time for reading and writing the register of the SRAM can be effectively reduced, the speed for reading and writing the register of the SRAM is greatly improved, the read-write frequency on a high-capacity NAND flash memory interface is conveniently improved, and the realization is simple.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
Referring to fig. 7, a block diagram of a NAND flash memory embodiment of the present invention is shown. The NAND flash memory includes an SRAM, N register areas (e.g., first register area, & gt, and/or an nth register area) connected to the SRAM, and N charge selection signals (e.g., first charge selection signal pres 1, & gt, and/or an nth charge selection signal PREBN) corresponding to the N register areas one by one, wherein periods of the N charge selection signals include delay times, the N charge selection signals have time delays with respect to each other, and the delay times in the N charge selection signal periods are superimposed and are equal to a total delay time of register selection signal traces of the N register areas. Wherein N is an integer greater than or equal to 2.
Specifically, when the SRAM reads and writes N register areas, the SRAM first receives the register address, then determines the register area to be read and written according to the register address, and then sets the charging selection signal corresponding to the register area to be read and written to be effective. Because the delay time in the charging selection signal period corresponding to the register area to be subjected to read-write operation is far smaller than the total delay time of the wiring, the NAND flash memory of the embodiment of the invention can effectively reduce the time for reading and writing the register of the SRAM and greatly improve the speed for reading and writing the register of the SRAM.
Alternatively, in one embodiment of the present invention, the NAND flash memory may determine the register area to be subjected to the read/write operation according to the register address through the decoder, wherein the decoder may determine the register area to be subjected to the read/write operation according to the high K bit address of the register address. Alternatively, in one embodiment of the present invention, the NAND flash memory may delay the N charge selection signals by a delay circuit so that the N charge selection signals have a time delay with respect to each other. Optionally, in an embodiment of the present invention, the NAND flash memory may select a charge selection signal corresponding to a register area to be subjected to a read/write operation through a selector, and set the charge selection signal corresponding to the register area to be subjected to the read/write operation to be valid.
Optionally, in an embodiment of the present invention, N register areas are the same in size, and a delay time difference of the charging selection signals corresponding to two adjacent register areas is a total delay time/N of the register selection signal routing. The total delay time of the register selection signal wires is the delay of the register selection signal wires between the register with the nearest register selection signal wire and the register with the farthest register selection signal wire in the N register areas.
Optionally, in one embodiment of the present invention, the falling edge of the charge selection signal is subsequent to the falling edge of the register selection signal of the mth register in the corresponding register area, and the mth register is the furthest register of the register selection signal traces in the register area.
Optionally, in one embodiment of the present invention, the rising edge of the charge select signal is preceded by a rising edge of a register select signal of a first register in the corresponding register region, the first register being a register in the register region where the register select signal is routed closest.
In one embodiment of the present invention, a circuit structure of SRAM reading data from a register in a NAND flash memory may be as shown in fig. 8, where the PREB signal is a charge selection signal corresponding to a register area to be read and written in the N charge selection signals, and the SELC signal is a register selection signal corresponding to a register to be read and written. Here, assuming that the NAND flash memory includes four register areas (a first register area, a second register area, a third register area, and a fourth register area), the N charge selection signals are respectively preg 1, preg 2, preg 3, and preg 4, and the NAND flash memory includes W registers (a first register,..the third, the W-th register).
The process of the SRAM in fig. 8 for reading and writing the first register in the first register area is illustrated as follows:
The SRAM reads the first register, the charge select signal preb1=0, and the power supply charges bus nodes Q and QB between the SRAM and the first register to the voltage VDD. The selection signal selc1=1 of the first register, if flg=0, inv=1, the bus node Q discharges FLG, and the bus node QB voltage is maintained at VDD. The select signal selc1=0 of the first register, and the sram amplifies the voltage difference of QB-Q (e.g., 100 mv) to a full swing signal "0" and outputs through DOUT. The selection signal selc=1 of the first register, if flg=1, inv=0, the bus node Q is maintained at VDD, and the bus node QB discharges INV. The selection signal selc1=0 of the first register, the sram amplifies the voltage difference of Q-QB to the full swing signal "1" and outputs through DOUT.
The SRAM writes to the first register with a charge select signal preb1=0 and the power supply charges bus nodes Q and QB between the SRAM and the first register to a voltage VDD. The select signal selc1=1 of the first register, if din=0, the sram discharges the bus node Q voltage to 0, and the bus node QB is maintained at VDD, thereby inputting 0 to FLG, SELC1 is turned off, and writing "0" is completed.
SELC1 is turned on, if din=1, sram discharges 0 to QB, q remains VDD, thus inputting 1 to FLG, SELC1 is turned off, and writing "1" is completed.
As shown in fig. 9, the timing of reading and writing the first register by the SRAM is that of reading and writing the first register by the SRAM, and the period (trd) of the preg 1 is that of reading and writing the first register by the SRAM, and is composed of a minimum high level time (th) of the SELC1, a minimum low level time (tl) of the preg 1, and a delay time (total trace delay time/4). The minimum high time of SELC1 is limited by the read accuracy of the SRAM, for example, if the read accuracy of the SRAM is 100mV, then the minimum high time (th) of SELC1 is the time that bus nodes Q and QB discharge to 100mV differential. The PREB1 minimum low time is limited by the time that PREB1 recharges the bus node Q and QB voltages back to voltage VDD. Because the delay time is only 1/4 of the total delay time of the wiring, the period of the PREB1 is effectively reduced, namely the speed of the SRAM for reading and writing the first register is effectively improved. In fig. 9, tdly is the total delay time of the trace.
The NAND flash memory provided by the embodiment of the invention has the advantages that the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals corresponding to the N register areas one by one, the periods of the N charging selection signals comprise delay time, the N charging selection signals have time delay, and the total delay time of the register selection signal wiring lines of the N register areas is equal to the sum of the delay time in the N charging selection signal periods. After receiving the register address, determining a register area to be subjected to read-write operation according to the register address, and further setting a charging selection signal corresponding to the register area to be subjected to read-write operation to be effective. Therefore, the invention selects the charging selection signals in regions through the register addresses, the delay time in the charging selection signal period is far smaller than the wiring delay, even if the Page capacity of NAND FLASH and the total delay time of the register selection signal wiring of N register areas are very large, the time for reading and writing the register of the SRAM can be effectively reduced, the speed for reading and writing the register of the SRAM is greatly improved, the read-write frequency on a high-capacity NAND flash memory interface is conveniently improved, and the realization is simple.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
While the foregoing has described in some detail and with reference to specific examples, the principles and embodiments of the present invention have been described herein for purposes of illustration only and as such are not to be construed as limiting the invention to the specific embodiments and applications contemplated by those of ordinary skill in the art to which the invention pertains.