CN112653638B - Device for switching routes of multiple paths of intermediate frequencies and baseband at high speed and communication method thereof - Google Patents

Abstract

The invention has proposed a multi-channel intermediate frequency and high-speed exchange routing device and its communication method of the baseband, realize the interaction of the data communication through constructing the communication bridge, further include step one, construct the communication link and send the communication data; step two, receiving communication data and converting the form of the communication data; and step three, outputting the converted communication data to finish data communication. The conversion of the communication data format is realized by multiport mapping, and a polling mechanism is adopted to realize the resource traversal reading, so that the link resource is reasonably used; meanwhile, an occupation identifier is added in a protocol of a communication data packet to lock the current link, so that interference of other buffers to be connected to the current link is avoided. The invention solves the problem that the single-path common public radio interface can not meet the requirement of high-speed data transmission with large data volume between the radio remote unit and the baseband processing unit through protocol conversion, a polling mechanism and multi-port mapping.

Description

Device for switching routes of multiple paths of intermediate frequencies and baseband at high speed and communication method thereof

Technical Field

The invention relates to a device for multi-path intermediate frequency and baseband high-speed exchange routing and a communication method thereof, in particular to the technical field of communication.

Background

With the development of computer network technology, under the advance of 5G network technology, in order to implement high-speed access of a network, an antenna end adopts a mode array of a large-scale antenna technology.

In the prior art, during high-speed access of a network, a single-path common public radio interface cannot meet the requirement of high-speed data transmission of a large data volume between a radio remote unit and a baseband processing unit, and has the defects of transmission delay, low reliability and low practicability due to low expandability.

Disclosure of Invention

The purpose of the invention is as follows: an object of the present invention is to provide a device for switching routes between multiple intermediate frequencies and multiple baseband high speeds, so as to solve the above-mentioned problems in the prior art. A further object is to propose a device based communication method.

The technical scheme is as follows: a device for multi-path intermediate frequency and baseband high-speed exchange routing specifically comprises: the system comprises an intermediate frequency board module, a public radio interface board card module, a baseband board module and a communication connection module; the intermediate frequency board module and the public radio interface board module construct a data communication link through the communication connection module; the public radio interface board module constructs a data communication link with the intermediate frequency board module and the baseband board module through the communication connection module; the baseband board module and the intermediate frequency board module exchange and transmit data with the communication connection module through the public radio interface board card module.

In a further embodiment, the communication connection module further includes an SRIO protocol link module, an optical fiber link module; the SRIO protocol link module sends data transmitted by the intermediate frequency board module to a public radio interface board card in the public radio interface board card module through an SRIO link; and the optical fiber link module transmits the data in the card module of the public radio interface board to the baseband board module through an optical port of an optical fiber.

In a further embodiment, when the public radio interface board card module performs data communication, the communication data packet further includes a CPRI service frame and an SRIO service frame, where the CPRI framing module formed by the CPRI service frame further includes an IQ mapping module, an IQ indication signal mapping module, and a control module, and corresponding control information is added in the control module, so as to reduce delay of data transmission and improve throughput of the system.

A method for switching routes of multiple paths of intermediate frequencies and baseband high speed specifically comprises the following steps based on the device:

step one, constructing a communication link and sending communication data;

step two, receiving communication data and converting the form of the communication data;

and step three, outputting the converted communication data to finish data communication.

In a further embodiment, the first step is further to construct a communication link for transmitting communication data, specifically including an SRIO link between the intermediate frequency board and the CPRI board, and an optical fiber link between the CPRI board and the baseband board.

In a further embodiment, the SRIO link is used for receiving communication data in the intermediate frequency board and sending the communication data to the CPRI board card in the communication from the intermediate frequency board to the baseband board; in the communication from the baseband board to the intermediate frequency board, the method and the device are used for packaging the CPRI board card into service data in an SRIO protocol frame format, determining a destination identifier according to a designated field in the service data, and sending an SRIO packet to the corresponding intermediate frequency board.

In a further embodiment, during data communication between the intermediate frequency board and the baseband board, the optical fiber link transmits communication data through a CPRI optical interface in the CPRI board and the baseband board by using an optical fiber.

In a further embodiment, in the second step, in the data communication process, format conversion of communication data between the intermediate frequency board and the baseband board is realized by using framing and deframing between corresponding protocols in the CPRI board card; the format conversion comprises the mapping from the SRIO data packet to the CPRI optical interface and the mapping from the CPRI data packet to the SRIO data packet of the intermediate frequency board.

In a further embodiment, the mapping process from the SRIO data packet to the CPRI optical port specifically includes receiving the SRIO data packet transmitted by the intermediate frequency board through the SRIO link, and converting the protocol data format through framing and deframing between the corresponding protocols, and further includes the following steps:

step 2.1, the CPRI board card analyzes the service data from the SRIO frame, filters the error data packet and records the number of the received data packets;

step 2.2, the CPRI board card receives SRIO data packets of the intermediate frequency board, the SRIO packet divider separates all the received service data packets by detecting the source SRIO identifiers of the SRIO data packets, and correspondingly writes the data into the first-in first-out data buffers with corresponding quantity;

step 2.3, the CPRI board card corresponds to 2 baseband boards, the multi-port mapping completes the port mapping by detecting the appointed field in the data packet, all the received SRIO packets are respectively sent to the corresponding CPRI optical ports, and the service data of the SRIO is checked and filtered;

step 2.4, the controller reads the data stored in the first-in first-out buffer by the SRIO sub-packet device and caches the SRIO data packet for primary service data; the controllers are two uplink ping-pong controllers, and each uplink ping-pong controller internally comprises a group of ping-pong first-in first-out buffers;

and step 2.5, the CPRI framer respectively reads the complete service data in the uplink ping-pong first-in first-out buffer, frames according to the CPRI protocol, and synchronously outputs the complete service data to the corresponding CPRI IP core.

In a further embodiment, the mapping process of the CPRI data packet to the SRIO data packet of the intermediate frequency board specifically includes receiving the CPRI data packet transmitted by the baseband board through the optical fiber link, and converting the protocol data format through framing and deframing between the corresponding protocols, and further includes the following steps:

step I, a CPRI deframer detects data of a CPRI IP core in real time, and when detecting that service data is transmitted, the data is analyzed from a CPRI protocol frame format;

step II, the downlink buffer receives the output data of the CPRI deframer and writes the output data into the buffer for the reading of a back link;

step III, the controller reads the data of the downlink buffer memory, stores the data into a first-in first-out buffer memory, and outputs the data as one-time complete service data; the controller is two downlink ping-pong controllers, and each controller internally comprises a group of ping-pong first-in first-out buffers;

step IV, the downlink simultaneously receives data transmitted by the optical interface, and the multiplexer traversably reads the data of the downlink ping-pong controller in a many-to-one mapping mode;

and step V, the SRIO framer packs the service data into an SRIO protocol frame format, determines a target SRIO identifier according to a designated field in the service data, and sends the SRIO packet to a corresponding intermediate frequency plate.

In a further embodiment, when the communication information data format is converted, the second step further includes parsing of the data packet, when the SRIO data packet is used for data transmission, the SRIO service frame has only one frame header and contains frame header identification characters, the target channel number indicates to which CPRI optical port the current service data should be routed, the target channel is composed of 8 bytes, and two groups of signals are defined in the system application to control the channel switch of the switching module; the two groups of signals are collectively a lower optical port channel with the channel number of 0 and an upper optical port channel with the channel number of 1; when the CPRI data packet is used for data transmission, the service frame format of the CPRI consists of IQ mapping, IQ indication signal mapping and a control module.

In a further embodiment, the multi-port mapping further detects a service frame header and a target channel number in a clock cycle when SRIO data arrives, opens a switching channel according to the direction of the channel number, and locks a data path being transmitted; the SRIO end and the CPRI end of the CPRI board card are both designed as FIFO interfaces, and are used for reading SRIO FIFO data and writing the SRIO FIFO data into the CPRI FIFO; the locking of the data path in transmission further introduces an occupation signal into the transmitted data packet for locking the signal connection of the address switching module; the occupancy signal indicates that the current link is undergoing data exchange for avoiding signals on other links from establishing a connection with the current link.

In a further embodiment, the address switching module is further configured to connect and release signals between the SRIO FIFO and the CPRI FIFO according to the configuration of the routing table; the routing table comprises a channel protocol definition table, and realizes connection and release between signals according to a set identifier to finish reading and inputting of data; and the connection and the release between the signals further adopt a polling mechanism, and update of a routing table is carried out through one-to-many polling one by one so as to complete data exchange mapping.

In a further embodiment, the polling mechanism further comprises a parallel polling mechanism, an equalized polling mechanism; the parallel polling mechanism comprises two first-in first-out modules, wherein the parallel polling mechanism simultaneously judges whether SRIO FIFO has data or not during polling, whether the SRIO FIFO is locked or not, if the SRIO FIFO does not have data or is locked, the SRIO FIFO directly polls downwards, if the SRIO FIFO has data or is not locked, whether the SRIO FIFO is a current exchange port or not is judged, a polling result is reflected on a routing register, and if a communicating link signal is locked, the current communication link is not polled; the first-in first-out module comprises a CPRI FIFO0 polling module and a CPRI FIFO1 polling module.

In a further embodiment, the balanced polling mechanism is that after processing data of one SRIO FIFO, whether the subsequent SRIO FIFO has data is checked, if so, the switch of the current SRIO FIFO is forcibly closed, and the polling control module of the CPRI FIFO0 can continue to process the following data; and if the subsequent SRIO FIFO has no data or is closed, opening all SRIO FIFO switches and starting the second polling.

Has the advantages that: the invention provides a device for multi-path intermediate frequency and baseband high-speed exchange routing and a communication method thereof, which adopt an FPGA (field programmable gate array) hard connection mode in hardware connection to realize data analysis and exchange between a plurality of radio remote unit ports and a plurality of baseband processing unit ports and realize parallel polling and balanced polling of dynamic mapping, improve the reliability of a system, avoid data congestion and further reduce the delay of dynamic mapping exchange. The time delay is reduced, the switching speed is high, and the reliability is better. The invention supports the access of a plurality of radio remote unit ports with different numbers, is convenient for capacity expansion and capacity reduction, has the characteristics of low time delay and manageability, supports the real-time monitoring of Ethernet and has strong practicability.

Drawings

Fig. 1 is a block diagram of a receiving link between 8 sets of if boards and 2 sets of baseband boards according to the present invention.

Fig. 2 is a block diagram of a transmission link between 8 sets of if boards and 2 sets of baseband boards according to the present invention.

Fig. 3 is a block diagram of an implementation of the common radio interface framing of the present invention.

Fig. 4 is a diagram of the switching control architecture of the present invention.

FIG. 5 shows signals between the SRIO FIFO and the CPRI FIFO according to the present invention.

Fig. 6 is a block diagram of a routing register of the present invention.

Fig. 7 is a block diagram of an implementation of the parallel polling process of the present invention.

Fig. 8 is a block diagram of an implementation of the balanced polling process of the present invention.

Fig. 9 is a flow chart of a communication method of the present invention.

Detailed Description

The invention realizes that a plurality of public radio interfaces are connected to a switch through high-speed optical fibers through a device for switching routes of a plurality of paths of intermediate frequencies and a baseband at a high speed and a communication method thereof, thereby realizing the purpose of data communication. The present invention will be further described in detail with reference to the following embodiments and accompanying drawings.

In this application, we propose a device for switching routes of multiple intermediate frequencies and multiple baseband high speeds and a communication method thereof, which includes a device for switching routes of multiple intermediate frequencies and multiple baseband high speeds, comprising: the system comprises an intermediate frequency board module, a public radio interface board card module, a baseband board module and a communication connection module.

The intermediate frequency board module and the public radio interface board module construct a data communication link through the communication connection module, the public radio interface board module constructs a data communication link with the intermediate frequency board module and the baseband board module through the communication connection module, and the baseband board module and the intermediate frequency board module exchange and transmit data through the public radio interface board module and the communication connection module.

The communication connection module further comprises an SRIO protocol link module and an optical fiber link module. The SRIO protocol link module sends the data transmitted by the intermediate frequency board module to a public radio interface board card in the public radio interface board card module through the SRIO link. The optical fiber link module transmits the data in the public radio interface board card module to the baseband board module through an optical port of an optical fiber. The public radio interface board card comprises an SRIO IP core, an SRIO deframer, an SRIO subpackage device, a multi-path processor, a pingpong controller, a CPRI framer and a CPRI IP core. According to the communication requirement, the multi-path processor is used for multi-port mapping and multi-path selection, and when the intermediate frequency board and the baseband board form a receiving link, the multi-path processor is used for realizing the multi-port mapping; when the intermediate frequency board and the baseband board form a transmission link, the multiprocessor is used for realizing multi-path selection.

When the public radio interface board card module carries out data communication, the communication data packet further comprises a CPRI service frame and an SRIO service frame, wherein the CPRI framing module formed by the CPRI service frame further comprises an IQ mapping module, an IQ indication signal mapping module and a control module. The control module is added with corresponding control information, so that the delay of data transmission is reduced, and the throughput of the system is improved.

The SRIO end and the CPRI end of the CPRI board card are both designed as FIFO interfaces for reading the data of the SRIO FIFO and writing the data into the CPRI FIFO.

Because the bit width and the rate of the data of the CPRI protocol and the SRIO protocol are not matched, the public radio interface board card uses a ping-pong first-in first-out buffer to convert SRIO asynchronous data into synchronous data of CPRI, performs data caching and rate matching, and adopts dynamic mapping 'parallel polling' and 'balanced polling', thereby improving the reliability of the system, avoiding SRIO FIFO data congestion and reducing the time delay of dynamic mapping exchange.

A communication method for multi-path intermediate frequency and baseband high-speed exchange routing is based on the device, particularly relates to data communication between eight intermediate frequency boards and two baseband boards, and comprises the following steps:

step one, constructing a communication link and sending communication data; the step builds a communication link for transmitting communication data, and specifically comprises an SRIO link between an intermediate frequency board and a CPRI board card and an optical fiber link between the CPRI board card and a baseband board. The SRIO link is used for receiving communication data in the intermediate frequency board and sending the communication data to the CPRI board card in the communication from the intermediate frequency board to the baseband board; in the communication from the baseband board to the intermediate frequency board, the method and the device are used for packaging the CPRI board card into service data in an SRIO protocol frame format, determining a destination identifier according to a designated field in the service data, and sending an SRIO packet to the corresponding intermediate frequency board. In the data communication process between the intermediate frequency board and the baseband board, the optical fiber link transmits communication data by using optical fibers through the CPRI optical port in the CPRI board card and the baseband board.

Step two, receiving communication data and converting the form of the communication data; in the data communication process, the format conversion of communication data between the intermediate frequency board and the baseband board is realized by using framing and unframing between corresponding protocols in the CPRI board card; the format conversion comprises the mapping from the SRIO data packet to the CPRI optical interface and the mapping from the CPRI data packet to the SRIO data packet of the intermediate frequency board.

The mapping process from the SRIO data packet to the CPRI optical port specifically includes receiving the SRIO data packet transmitted by the intermediate frequency board through the SRIO link, and converting the protocol data format through framing and deframing between the corresponding protocols, and further includes the following steps:

and 2.1, the CPRI board card analyzes the service data from the SRIO frame, filters the error data packet according to the checking function of the data packet, and records the number of the received data packets.

Step 2.2, the CPRI board card receives SRIO data packets of eight intermediate frequency boards, the SRIO packet divider separates all received service data packets by detecting source SRIO identifiers of the SRIO data packets, and correspondingly writes data into eight first-in first-out data buffers;

step 2.3, the CPRI board card corresponds to two baseband boards, multiport mapping is completed by detecting specified fields in thedata packet 8

And 2, port mapping, namely respectively sending all the received SRIO packets to corresponding CPRI optical ports, and verifying and filtering the service data of the SRIO packets so as to ensure that the link is normal.

And 2.4, the SRIO is in an asynchronous transmission mode, and the SRIO packet cannot transmit complete service data at a time, so that two uplink ping-pong controllers are adopted in the CPRI board card and used for reading the data stored in the first-in first-out buffer by the SRIO packet distributor and caching the SRIO data packet into the service data at a time, thereby meeting the CPRI synchronous transmission mode. Wherein, the two uplink ping-pong controllers each internally comprise a group of ping-pong first-in first-out buffers.

And step 2.5, the CPRI framer respectively reads the complete service data in the uplink ping-pong first-in first-out buffer, frames according to the CPRI protocol, and synchronously outputs the complete service data to the corresponding CPRI IP core. The CPRI framers are two in the CPRI board card and respectively correspond to the two CPRI IP cores.

The mapping process from the CPRI data packet to the SRIO data packet of the intermediate frequency board is specifically to receive the CPRI data packet transmitted by the baseband board through the optical fiber link, and convert the protocol data format through framing and unframing between the corresponding protocols, and further comprises the following steps:

step I, the CPRI deframer detects data of the CPRI IP core in real time, and when the transmission of service data is detected, the data is analyzed from a CPRI protocol frame format.

And step II, the downlink buffer receives the output data of the CPRI deframer and writes the output data into the buffer for reading by a back link, and the conversion from the CPRI to the SRIO protocol is the conversion from synchronous transmission to an asynchronous output mode.

Step III, the controller reads the data of the downlink buffer memory, stores the data into a first-in first-out buffer memory, and outputs the data as one-time complete service data; the controller is two downlink ping-pong controllers, and each controller comprises a group of ping-pong first-in first-out buffers.

Step IV, the down link receives the data transmitted by two optical ports at the same time, the multiplexer adopts 2

1, traversing and reading the data of the two downlink ping-pong controllers.

And step V, the SRIO framer packs the service data into an SRIO protocol frame format, determines a target SRIO identifier according to a designated field in the service data, and sends the SRIO packet to a corresponding intermediate frequency plate.

When the communication information data form is converted, the analysis of the data packet is further included, when the SRIO data packet carries out data transmission, each SRIO packet contains 256 bytes of data at most, and one service packet of the intermediate frequency board needs to be composed of a plurality of SRIOs. The bit width of the CPRI optical interface data interface provided by Xilinx is 16 bytes, and data of one service frame needs to be continuously sent out in a bit width of 16 bytes, for example, 1440 symbols exist in one time slot of data with x15 times bandwidth, each symbol has 32 bytes, i.e., 1440 × 32 bytes, and the CPRI optical interface needs to transmit the whole service packet without interruption when transmitting. Therefore, SRIO to CPRI is a process from asynchronous transmission to synchronous transmission, and a certain space of cache is needed to ensure the continuity of CPRI optical interface data.

In the transmission protocol, the SRIO service frame has only one frame header, which contains frame header identification characters, the target channel number indicates which CPRI optical port the current service data should be routed to, the target channel is composed of 8 bytes, the system application defines the lower optical port channel number as 0, the upper optical port channel number as 1, and these two groups of signals will switch the channel controlling the switching module. When the CPRI data packet is used for data transmission, the service frame format of the CPRI consists of IQ mapping, IQ indication signal mapping and a control module.

In the step of realizing multi-port mapping, the multi-path controller specifically adopts a First World Fall Through mode, when SRIO data arrives, a service frame header and a target channel number are detected in a clock cycle, a switching channel is opened according to the direction of the channel number, and a data channel which is being transmitted is locked.

The SRIO end and the CPRI end are both designed as FIFO interfaces, that is, data of the SRIO FIFO is read and written into the CPRI FIFO, so that the SRIO FIFO interface is controlled to be connected with a read-write control line of the CPRI FIFO interface, and switching can not be performed due to arrival of data of other SRIO FIFO when data is read and written, that is, a data path being transmitted is locked.

The polling mechanism further comprises a parallel polling mechanism and an equilibrium polling mechanism; the parallel polling mechanism comprises two first-in first-out modules, and is characterized in that whether SRIO FIFO has data or not is judged simultaneously during polling, whether the SRIO FIFO is locked or not, if the SRIO FIFO has no data or is locked, downward polling is directly carried out, if the SRIO FIFO has data or is not locked, whether the SRIO FIFO is a current exchange port or not is judged, a polling result is reflected on a routing register, and if a communication link signal is locked, the current communication link is not polled; the first-in first-out module comprises a CPRI FIFO0 polling module and a CPRI FIFO1 polling module.

The balanced polling mechanism is that after processing data of one SRIO FIFO, whether the subsequent SRIO FIFO has data or not is checked, if the data exists, a switch of the current SRIO FIFO is forcibly closed, and a polling control module of the CPRI FIFO0 can continue to process the following data; and if the subsequent SRIO FIFO has no data or is closed, opening all SRIO FIFO switches and starting the second polling.

In a specific embodiment, as shown in fig. 5, when the SRIO FIFO0 and the CPRI FIFO0 are connected, the busy signal is simultaneously output to lock the signal connection of the MAP module, so as to prevent other SRIO FIFOX from being connected with the current CPRI FIFO, and when the data transmission is completed, the busy signal is released, and simultaneously the signal connection between the SRIO FIFO0 and the CPRI FIFO0 is released, and a new SRIO FIFO is waited to be established again.

The MAP module is further used for connecting and releasing signals between the SRIO FIFO and the CPRI FIFO according to the configuration of the routing table; the routing table comprises a channel protocol definition table, and realizes connection and release between signals according to a set identifier to finish reading and inputting of data; and the connection and the release between the signals further adopt a polling mechanism, and update of a routing table is carried out through one-to-many polling one by one to complete data exchange mapping. The channel protocol definition table is shown in table 1 below, in which the set signal identifier SRIO _ data is connected to CPRI _ data signal for SRIO and CPRI data transmission, and SRIO _ rd is connected to CPRI _ rd signal for reading SRIO FIFO data and writing the SRIO FIFO data into CPRI FIFO.

Table 1 channel protocol definition table

Signal line	Definition of functions	Description of the function
			srio_data	Output data of SRIO FIFO	64bits
cpri_data	Input data of CPRI FIFO	64bits
			empty	SRIO FIFO empty indication	Empty is pulled low when there is data in FIFO
valid	CPRI FIFO write enable control	valid is connected with the inverted empty signal to carry out data validity control, and when the empty is 0, the CPRI FIFO is written to be valid
			srio_rd	SRIO read enable
cpri_rd	CPRI port controlled read enable

In a specific embodiment, a 8 × 2= 16-bit routing register is designed, and a 1 bit is 1 to indicate connection and 0 to indicate release. As shown in the routing register map of FIG. 6 below, bits 0-7 indicate the connection relationship between 8 SRIO FIFOs and CPRI FIFO0, and bits 8-15 indicate the connection relationship between 8 SRIO FIFOs andCPRI FIFO 1. For example, when the second bit is 1, it indicates that SRIO FIFO2 is connected to CPRI FIFO0, and when the twelfth bit is 1, it indicates thatSRIO FIFO 5 is connected toCPRI FIFO 1.

As one CPRI FIFO can only be connected with one SRIO FIFO in the same time, the bits 0-7 have 1 bit at most as 1, the other bits are 0,8-15 bits also have 1 bit at most as 1, the other bits are 0, and at most 2 marks are 1 in the whole routing table. And the same SRIO FIFO does not exist in the same time to connect two CPRI FIFOs at the same time, for example, when the second bit does not exist and is 1, the tenth bit is also 1. That is, the map routing register is controlled by the first data header indication byte in the SRIO FIFO, so as to determine the connection relationship between the SRIO FIFO and the CPRI FIFO, but there may be a plurality of SRIO FIFOs all connected to the CPRI FIFO, for example, SRIO FIFO0 and SRIO FIFO1 are both connected to the CPRI FIFO0, and when the CPRI FIFO0 is connected to the SRIO FIFO0, the signal is locked, that is, busy is pulled high, so as to prevent the subsequent SRIO FIFO1 from being connected to theCPRI FIFO 0.

And the CPRI FIFO0 and the CPRI FIFO1 adopt a polling mechanism for 8 SRIO FIFOs at the same time, namely the CPRI FIFO0 polls theSRIO FIFOs 0 to 7 one by one, and the CPRI FIFO1 polls the 8 SRIO FIFOs at the same time, if service data matched with port numbers in the SRIO FIFOs exist, the MAP routing table is updated, and data exchange mapping is completed. The parallel polling process is shown in fig. 7, and the balanced polling process is shown in fig. 8.

The mode for realizing the parallel polling is that a CPRI FIFO0 polling module and a CPRI FIFO1 polling module are adopted, and the SRIO FIFO 0-SRIO FIFO 7 are polled one by one in parallel. The polling result is reflected on the routing register map. When a certain SRIO FIFO is already locked, the current SRIO FIFO is not polled any more. For example, SRIO FIFO2 is already connected and locked with CPRI FIFO0, CPRI FIFO1 skips SRIO FIFO2 at the time of polling, thereby improving polling efficiency. And when polling, judging whether the SRIO FIFO has data or not and is locked or not, directly polling downwards if the SRIO FIFO has no data or is locked, and judging whether the SRIO FIFO has data or not is a current exchange port if the SRIO FIFO has data or is not locked. Meanwhile, the switching relation of 8 SRIO FIFOs is judged in one clock period by using the combinational logic of if condition judgment.

In order to improve the polling efficiency, the data in 8 SRIO FIFOs are processed in a balanced manner, that is, the same SRIO FIFO cannot be processed all the time, so that other SRIO FIFO data are accumulated, and finally the SRIO FIFO is full.

In order to meet the condition of balanced polling, a switch which can be accessed by the SRIO FIFO is controlled. After processing data of one SRIO FIFO, checking whether the subsequent SRIO FIFO has data, if so, forcibly closing a switch of the current SRIO FIFO, and continuing to process the following data by a polling control module of theCPRI FIFO 0. And if the subsequent SRIO FIFOs have no data or are closed, opening all SRIO FIFO switches and starting the second polling. For example, CPRI FIFO0 is connected to SRIO FIFO2, and meanwhile, whether data exists in the subsequent SRIO FIFO is detected, and if data exists inSRIO FIFO 7, the use of CPRI FIFO0 and SRIO FIFO2 is closed, even if there is still available data in SRIO FIFO2 for transmission. After the CPRI FIFO0 and theSRIO FIFO 7 are connected, the SRIO FIFO switches on the CPRI FIFO0 and theSRIO FIFO 7 can be opened to start the second polling because the SRIO FIFO does not exist at the back.

And step three, outputting the converted communication data to finish data communication.

As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (6)

1. A device for multi-path intermediate frequency and baseband high-speed exchange routing is characterized by specifically comprising: the system comprises an intermediate frequency board module, a public radio interface board card module, a baseband board module and a communication connection module; the intermediate frequency board module and the public radio interface board module construct a data communication link through the communication connection module; the public radio interface board module constructs a data communication link with the intermediate frequency board module and the baseband board module through the communication connection module; the baseband board module and the intermediate frequency board module exchange and transmit data with the communication connection module through the public radio interface board card module;

the communication connection module further comprises an SRIO protocol link module and an optical fiber link module; the SRIO protocol link module transmits the data transmitted by the intermediate frequency board module to a public radio interface board card in the public radio interface board card module through an SRIO link; the optical fiber link module transmits data in the public radio interface board card module to the baseband board module through an optical port of an optical fiber;

when the public radio interface board card module carries out data communication, the communication data packet further comprises a CPRI service frame and an SRIO service frame, wherein the CPRI service frame forming CPRI framing module further comprises an IQ mapping module, an IQ indication signal mapping module and a control module;

in the process of realizing communication by adopting the multi-channel intermediate frequency and baseband high-speed exchange routing device, the method specifically comprises the following steps:

step one, constructing a communication link and sending communication data;

step two, receiving communication data and converting the form of the communication data; the format conversion of communication data between the intermediate frequency board and the baseband board is realized by utilizing framing and deframing between corresponding protocols in the CPRI board card; the format conversion comprises mapping from an SRIO data packet to a CPRI optical port and mapping from the CPRI data packet to an SRIO data packet of an intermediate frequency board;

the mapping process from the SRIO data packet to the CPRI optical port specifically includes receiving the SRIO data packet transmitted by the intermediate frequency board through the SRIO link, and converting the protocol data format through framing and deframing between the corresponding protocols, and further includes the following steps:

step 2.1, the CPRI board card analyzes the service data from the SRIO frame, filters the error data packet and records the number of the received data packets;

step 2.2, the CPRI board card receives SRIO data packets of the intermediate frequency board, the SRIO packet divider separates all the received service data packets by detecting the source SRIO identifiers of the SRIO data packets, and correspondingly writes the data into the first-in first-out data buffers with corresponding quantity;

step 2.3, the CPRI board card corresponds to 2 baseband boards, the multi-port mapping completes the port mapping by detecting the appointed field in the data packet, all the received SRIO packets are respectively sent to the corresponding CPRI optical ports, and the service data of the SRIO is checked and filtered;

step 2.4, the controller reads the data stored in the first-in first-out buffer by the SRIO sub-packet device and buffers the SRIO data packet into primary service data; the controllers are two uplink ping-pong controllers, and each controller internally comprises a group of ping-pong first-in first-out buffers;

step 2.5, the CPRI framer reads the complete service data in the uplink ping-pong first-in first-out buffer respectively, frames according to the CPRI protocol, and synchronously outputs the complete service data to the corresponding CPRI IP core;

the mapping process from the CPRI data packet to the SRIO data packet of the intermediate frequency board is specifically to receive the CPRI data packet transmitted by the baseband board through the optical fiber link, and convert the protocol data format through framing and deframing between the corresponding protocols, and further includes the following steps:

step I, a CPRI deframer detects data of a CPRI IP core in real time, and when service data transmission is detected, the data is analyzed from a CPRI protocol frame format;

step II, the downlink buffer receives the output data of the CPRI deframer and writes the output data into the buffer for the reading of a back link;

step III, the controller reads the data of the downlink buffer memory, stores the data into a first-in first-out buffer memory, and outputs the data as one-time complete service data; the controllers are two downlink ping-pong controllers, and each downlink ping-pong controller internally comprises a group of ping-pong first-in first-out buffers;

step IV, the downlink simultaneously receives data transmitted by the optical interface, and the multiplexer traversably reads the data of the downlink ping-pong controller in a many-to-one mapping mode;

step V, the SRIO framer packs the service data into an SRIO protocol frame format, determines a target SRIO identifier according to a designated field in the service data, and sends an SRIO packet to a corresponding intermediate frequency plate;

and step three, outputting the converted communication data to finish data communication.

2. A method for switching a route between a plurality of intermediate frequencies and a baseband high speed, which is based on the device of claim 1, and is characterized by comprising the following steps:

step one, constructing a communication link and sending communication data;

step two, receiving communication data and converting the form of the communication data;

step three, outputting the converted communication data to finish data communication;

the first step is further to construct a communication link for transmitting communication data, and specifically comprises an SRIO link between the intermediate frequency board and the CPRI board, and an optical fiber link between the CPRI board and the baseband board;

the SRIO link is used for receiving communication data in the intermediate frequency board and sending the communication data to the CPRI board card in the communication from the intermediate frequency board to the baseband board; in the communication from the baseband board to the intermediate frequency board, the method is used for packaging the CPRI board card into service data in an SRIO protocol frame format, determining a destination identifier according to a designated field in the service data, and sending an SRIO packet to the corresponding intermediate frequency board;

the optical fiber link transmits communication data by using optical fibers through a CPRI optical port in the CPRI board card and the baseband board in the data communication process between the intermediate frequency board and the baseband board;

in the second step, in the data communication process, the format conversion of the communication data between the intermediate frequency board and the baseband board is realized by utilizing the framing and the deframing between the corresponding protocols in the CPRI board card; the format conversion comprises mapping from an SRIO data packet to a CPRI optical port and mapping from the CPRI data packet to an SRIO data packet of an intermediate frequency board;

the mapping process from the SRIO data packet to the CPRI optical port specifically includes receiving the SRIO data packet transmitted by the intermediate frequency board through the SRIO link, and converting the protocol data format through framing and deframing between the corresponding protocols, and further includes the following steps:

step 2.1, the CPRI board card analyzes the service data from the SRIO frame, filters the error data packet and records the number of the received data packets;

2.2, the CPRI board card receives SRIO data packets of the intermediate frequency board, and the SRIO packet packer separates all the received service data packets by detecting source SRIO identifiers of the SRIO data packets and correspondingly writes data into a corresponding number of first-in first-out data buffers;

step 2.3, the CPRI board card corresponds to 2 baseband boards, the multi-port mapping completes the port mapping by detecting the appointed field in the data packet, all the received SRIO packets are respectively sent to the corresponding CPRI optical ports, and the service data of the SRIO is checked and filtered;

step 2.4, the controller reads the data stored in the first-in first-out buffer by the SRIO sub-packet device and buffers the SRIO data packet into primary service data; the controllers are two uplink ping-pong controllers, and each controller internally comprises a group of ping-pong first-in first-out buffers;

step 2.5, the CPRI framer reads the complete service data in the uplink ping-pong first-in first-out buffer respectively, frames according to the CPRI protocol, and synchronously outputs the complete service data to the corresponding CPRI IP core;

the mapping process from the CPRI data packet to the SRIO data packet of the intermediate frequency board is specifically to receive the CPRI data packet transmitted by the baseband board through the optical fiber link, and convert the protocol data format through framing and deframing between the corresponding protocols, and further includes the following steps:

step I, a CPRI deframer detects data of a CPRI IP core in real time, and when detecting that service data is transmitted, the data is analyzed from a CPRI protocol frame format;

step II, the downlink buffer receives the output data of the CPRI deframer and writes the output data into the buffer for reading by a rear link;

step III, the controller reads the data of the downlink buffer memory, stores the data into a first-in first-out buffer memory, and outputs the data as one-time complete service data; the controllers are two downlink ping-pong controllers, and each downlink ping-pong controller internally comprises a group of ping-pong first-in first-out buffers;

step IV, the downlink simultaneously receives data transmitted by the optical interface, and the multiplexer traversably reads the data of the downlink ping-pong controller in a many-to-one mapping mode;

and step V, the SRIO framer packs the service data into an SRIO protocol frame format, determines a target SRIO identifier according to a designated field in the service data, and sends the SRIO packet to a corresponding intermediate frequency plate.

3. The method according to claim 2, wherein the second step further comprises parsing the packet during the data format conversion of the communication information, when the SRIO packet performs data transmission, the SRIO service frame has only one frame header, and contains frame header identification characters, the target channel number indicates which CPRI optical port the current service data should be routed to, the target channel consists of 8 bytes, and two groups of signals are defined in the system application to control the channel switch of the switching module; the two groups of signals are collectively a lower optical port channel with the channel number of 0 and an upper optical port channel with the channel number of 1; when the CPRI data packet is used for data transmission, the service frame format of the CPRI consists of IQ mapping, IQ indication signal mapping and a control module.

4. The method according to claim 2, wherein the multi-port mapping further comprises detecting a service frame header and a target channel number within a clock cycle when SRIO data arrives, opening a switching channel according to the direction of the channel number, and locking a data path being transmitted; the SRIO end and the CPRI end of the CPRI board card are both designed as FIFO interfaces, and are used for reading SRIO FIFO data and writing the SRIO FIFO data into the CPRI FIFO; the locking of the data path in transmission further introduces an occupation signal into the transmitted data packet for locking the signal connection of the address switching module; the occupancy signal indicates that the current link is undergoing data exchange for avoiding signals on other links from establishing a connection with the current link.

5. The method according to claim 4, wherein the address switching module further connects and releases signals between the SRIO FIFO and the CPRI FIFO according to the configuration of the routing table; the routing table comprises a channel protocol definition table, and realizes connection and release between signals according to a set identifier to finish reading and inputting of data; and the connection and the release between the signals further adopt a polling mechanism, and update of a routing table is carried out through one-to-many polling one by one so as to complete data exchange mapping.

6. The method of claim 5, wherein the polling mechanism further comprises a parallel polling mechanism and an equalizing polling mechanism; the parallel polling mechanism comprises two first-in first-out modules, wherein the parallel polling mechanism simultaneously judges whether SRIO FIFO has data or not during polling, whether the SRIO FIFO is locked or not, if the SRIO FIFO does not have data or is locked, the SRIO FIFO directly polls downwards, if the SRIO FIFO has data or is not locked, whether the SRIO FIFO is a current exchange port or not is judged, a polling result is reflected on a routing register, and if a communicating link signal is locked, the current communication link is not polled; the first-in first-out module comprises a CPRI FIFO0 polling module and a CPRI FIFO1 polling module;

the balanced polling mechanism is that after processing data of one SRIO FIFO, whether the subsequent SRIO FIFO has data or not is checked, if the data exists, a switch of the current SRIO FIFO is forcibly closed, and a polling control module of the CPRI FIFO0 can continue to process the following data; and if the subsequent SRIO FIFO has no data or is closed, opening all SRIO FIFO switches and starting the second polling.

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