CN112614846B - Manufacturing method of channel hole, memory and manufacturing method of memory - Google Patents

Abstract

Translated fromChinese

本发明提供了一种沟道孔的制作方法、存储器及其制作方法。该制作方法包括以下步骤：第一堆叠结构中形成有贯穿至衬底的多个第一沟道通孔，在各第一沟道通孔中形成填充层，第一堆叠结构具有至少一个切割区域，第一沟道通孔位于第一堆叠结构中除切割区域之外的区域中；在第一堆叠结构表面覆盖中间层，在与切割区域对应的中间层中形成第一对位槽；在中间层上形成第二堆叠结构，第二堆叠结构对应于第一对位槽的位置形成有第二对位槽；采用套刻工艺形成顺序贯穿第二堆叠结构和中间层至填充层的第二沟道通孔，去除填充层以使第二沟道通孔与第一沟道通孔连通。上述方法提高了第二沟道通孔与第一沟道通孔之间的对准精度，保证了器件的电学性能。

The present invention provides a method for fabricating a channel hole, a memory and a method for fabricating the same. The manufacturing method includes the following steps: forming a plurality of first channel through holes penetrating to the substrate in a first stack structure, forming a filling layer in each of the first channel through holes, and having at least one cutting region in the first stack structure , the first channel through hole is located in the area other than the cutting area in the first stack structure; the surface of the first stack structure is covered with an intermediate layer, and a first alignment groove is formed in the intermediate layer corresponding to the cutting area; in the middle A second stack structure is formed on the layer, and a second alignment groove is formed in the second stack structure corresponding to the position of the first alignment groove; an overetching process is used to form a second groove that sequentially runs through the second stack structure and the intermediate layer to the filling layer A via hole is removed, and the filling layer is removed so that the second via hole is communicated with the first via hole. The above method improves the alignment accuracy between the second channel through hole and the first channel through hole, and ensures the electrical performance of the device.

Description

Manufacturing method of channel hole, memory and manufacturing method of memory

Technical Field

The invention relates to the technical field of memories, in particular to a manufacturing method of a channel hole, a memory and a manufacturing method of the memory.

Background

In order to continuously increase the memory density capacity and reduce the critical dimension of the memory with certain physical limitations, many memory designs and manufacturers change the conventional 2D integration mode, and adopt the three-dimensional stacking technology to increase the storage density of the NAND flash memory.

In the current 3D NAND memory, a stacked 3D NAND memory structure is generally implemented by vertically stacking multiple layers of data storage units. In order to obtain the stacked 3D NAND memory structure, it is necessary to form a stacked structure in which sacrificial layers and isolation layers are alternately stacked on a silicon substrate, etch the stacked structure to form a Channel (CH), form a memory structure in the channel, form a gate spacer (GLS) in the stacked structure, and then remove the sacrificial layer to fill a gate in contact with the memory structure.

Along with the gradual increase of the number of layers of vertical stacking, the thickness accuracy and uniformity of the stacking structure are difficult to ensure, and the etching difficulty of the channel with the high depth-to-width ratio is gradually improved, so that the problems of channel reaming (bending), skewing (twisting) and the like are easy to generate. In order to solve the above problems, a double stacking technique (double stacking) is proposed in the prior art, that is, a stacking structure and a channel are deposited twice, and the number of layers of the stacking structure deposited each time is less than that of a single stacking, and the depth of an etched channel is shallow, thereby facilitating the improvement of yield.

In the above-mentioned double-stacking technique, an alignment process is usually adopted to form a Lower Channel Hole (LCH) and an Upper Channel Hole (UCH) in two stacked structures, respectively, so as to connect the two channel holes to form a deep hole, and in the process of forming two stacked structures, an alignment groove is formed on the surface of the upper stacked structure by the alignment process, and is used for aligning the subsequently formed upper channel hole with the lower channel hole, however, the alignment groove is formed after the upper stacked structure, and has a longer distance from the lower channel hole, and a step of heat treatment is usually required in the deposition process of forming the stacked structure, the heat treatment can cause the substrate to bend, thereby affecting the alignment precision (OVL) of the alignment process of forming the alignment groove, the alignment deviation can further affect the alignment precision of the subsequently formed upper channel hole, and further increase the alignment error of the lower channel hole and the upper channel hole, ultimately affecting the performance of the resulting memory structure.

Disclosure of Invention

The invention mainly aims to provide a method for manufacturing a channel hole, a memory and a method for manufacturing the memory, so as to solve the problem that the device performance is influenced by large alignment error of a lower channel hole and an upper channel hole in the prior art.

In order to achieve the above object, according to an aspect of the present invention, there is provided a method of fabricating a channel hole, including the steps of: providing a substrate with a first stacked structure on the surface, wherein a plurality of first channel through holes penetrating through the substrate are formed in the first stacked structure, a filling layer is formed in each first channel through hole, the first stacked structure is provided with at least one cutting area, and the first channel through holes are located in the first stacked structure except the cutting area; covering the surface of the first stacked structure with an intermediate layer, and forming a first alignment groove in the intermediate layer corresponding to the cutting area; forming a second stacking structure on the middle layer, wherein a second alignment groove is formed in the second stacking structure at a position corresponding to the first alignment groove; and forming a second channel through hole which sequentially penetrates through the second stacking structure and the middle layer to the filling layer by adopting an alignment process based on the second alignment groove, and removing the filling layer to enable the second channel through hole to be communicated with the first channel through hole.

Further, the first stacked structure includes first sacrificial layers and first isolation layers alternately stacked in a direction away from the substrate; the intermediate layer includes a second sacrificial layer and a second isolation layer alternately stacked in a direction away from the substrate; the second stack structure includes third sacrificial layers and third isolation layers alternately stacked in a direction away from the substrate.

Further, the intermediate layer includes at least two sets of second sacrificial layers and second isolation layers.

Further, the first alignment groove penetrates through the first stacking structure.

Further, a first alignment groove is formed in the intermediate layer corresponding to the cutting region using a photolithography process.

Further, the step of forming a second trench via includes: covering a hard mask on the surface of the second stacking structure, and forming a third alignment groove at the position of the hard mask corresponding to the second alignment groove; and forming an opening on the hard mask except the third alignment groove by adopting a photoetching process, and etching the second stacking structure through the opening to form a second channel through hole.

According to another aspect of the present invention, there is provided a method for manufacturing a memory, including the steps of: forming a stacked structure on the substrate by adopting the manufacturing method, wherein the stacked structure is provided with a channel hole penetrating through the substrate and comprises sacrificial layers and isolating layers which are alternately stacked along the direction far away from the substrate; forming a storage structure in the channel hole; forming gate isolation grooves penetrating through the substrate in the stacked structure, wherein the gate isolation grooves are positioned between adjacent channel holes; and removing the sacrificial layer and forming a gate layer at the position corresponding to the sacrificial layer.

Further, the step of forming the memory structure includes: a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer are sequentially formed on sidewalls of the channel hole in a stacked manner.

Further, a grid isolation groove penetrating through the substrate is formed in the cutting area of the stacked structure, wherein the second alignment groove is formed in the cutting area.

According to another aspect of the present invention, there is also provided a memory device, including a substrate having a dual gate stack structure and a memory structure, the dual gate stack structure includes a first gate stack structure, an intermediate gate stack structure and a second gate stack structure sequentially stacked along a direction away from the substrate, the first gate stack structure has a first channel via penetrating through the substrate, the intermediate gate stack structure and the second gate stack structure have a second channel via communicating with the first channel via, the memory structure is located in the first channel via and the second channel via, a side of the intermediate gate stack structure away from the substrate has a first alignment groove, a portion of the second gate stack structure is filled in the first alignment groove, and a side surface of the second gate stack structure away from the substrate has a second alignment groove corresponding to the first alignment groove.

By applying the technical scheme of the invention, the manufacturing method of the channel hole is provided, after a first channel through hole in a first stacked structure is formed, the surface of the first stacked structure is covered with an intermediate layer, the first stacked structure is provided with a cutting area, the first channel through hole is positioned in an area except the cutting area in the first stacked structure, and a first alignment groove is formed on the surface of the intermediate layer corresponding to the cutting area, so that the deviation of the forming position of the first alignment groove is reduced by carrying out alignment in the step of forming the first alignment groove; and then forming a second stacking structure on the intermediate layer, forming a second alignment groove on the surface of the second stacking structure at a position corresponding to the first alignment groove, forming a second channel through hole sequentially penetrating through the second stacking structure and the intermediate layer by adopting an alignment process based on the second alignment groove, and removing the filling layer to communicate the second channel through hole with the first channel through hole, so that the deviation of the forming position of the second channel through hole is reduced by alignment in the step of forming the second channel through hole, the alignment precision between the second channel through hole and the first channel through hole is improved, and the electrical performance of the device is ensured.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic cross-sectional view illustrating a substrate after a plurality of first trench vias penetrating through a substrate are formed in a first stacked structure and a filling layer is formed in each first trench via in a method for forming a trench hole according to an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional view of the substrate after the surface of the first stacked structure shown in FIG. 1 is covered with an intermediate layer;

FIG. 3 is a schematic cross-sectional view illustrating a substrate after forming a first alignment groove in the intermediate layer corresponding to the cutting region shown in FIG. 2 by using an alignment process;

FIG. 4 is a schematic cross-sectional view of the substrate after a second stacked structure is formed on the intermediate layer shown in FIG. 3, wherein a second alignment groove is formed in the second stacked structure corresponding to the first alignment groove;

FIG. 5 is a schematic cross-sectional view of the substrate after the second stack structure shown in FIG. 4 is covered with a hard mask and a photoresist;

FIG. 6 is a schematic cross-sectional view of the substrate after forming a second trench via penetrating to the filling layer in the second stacked structure shown in FIG. 5 by using an overlay process and removing the filling layer to communicate the second trench via with the first trench via;

fig. 7 is a schematic cross-sectional view illustrating a memory according to an embodiment of the present disclosure.

Wherein the figures include the following reference numerals:

10. a first stacked structure; 110. a first sacrificial layer; 120. a first isolation layer; 130. a first gate structure; 20. a channel hole; 210. a first trench via; 211. a filling layer; 220. a second trench via; 30. an epitaxial layer; 40. an intermediate layer; 410. a second sacrificial layer; 420. a second isolation layer; 430. a second gate stack structure; 510. a first alignment slot; 520. a second alignment slot; 60. a second stacked structure; 610. a third sacrificial layer; 620. a third isolation layer; 630. a third gate structure; 70. a hard mask; 80. a second photoresist layer; 100. a substrate; 200. a first gate stack structure; 300. an intermediate gate stack structure; 400. a second gate stack structure; 500. and storing the structure.

Detailed Description

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As described in the background art, in the process of forming the lower channel hole in the prior art, an alignment groove needs to be formed on the surface of the upper stacked structure by using an alignment process for aligning the subsequently formed upper channel hole with the lower channel hole, however, the alignment groove is formed after the upper stacked structure and is far away from the lower channel hole, and a thermal treatment step is usually required in the deposition process for forming the stacked structure, the thermal treatment may cause the substrate to bend, thereby affecting the alignment precision (OVL) of the alignment process for forming the alignment groove, and the alignment deviation may further affect the alignment precision of the alignment process for subsequently forming the upper channel hole, thereby increasing the alignment error between the lower channel hole and the upper channel hole, and finally affecting the performance of the manufactured memory structure.

The inventors of the present invention have studied the above problems and have proposed a method for forming a channel hole, as shown in fig. 1 to 6, comprising the steps of:

providing asubstrate 100 having a firststacked structure 10 on a surface thereof, the firststacked structure 10 having a plurality of first channel throughholes 210 formed therein and penetrating through thesubstrate 100, afilling layer 211 formed in each of the first channel throughholes 210, the firststacked structure 10 having at least one cutting region, the first channel throughholes 210 being located in a region of the firststacked structure 10 other than the cutting region;

covering theintermediate layer 40 on the surface of the firststacked structure 10, and forming afirst alignment groove 510 in theintermediate layer 40 corresponding to the cutting region;

forming asecond stack structure 60 on theintermediate layer 40, thesecond stack structure 60 having asecond alignment groove 520 formed at a position corresponding to thefirst alignment groove 510;

based on thesecond alignment groove 520, the second trench via 220 sequentially penetrating through thesecond stack structure 60 and theintermediate layer 40 is formed using an alignment process, and thefilling layer 211 is removed to communicate the second trench via 220 with the first trench via 210.

By adopting the manufacturing method of the channel hole, the deviation of the forming position of the first alignment groove is reduced by carrying out alignment in the step of forming the first alignment groove; and then, the deviation of the forming position of the second channel through hole is reduced through the alignment of the overlay in the step of forming the second channel through hole, so that the alignment precision between the second channel through hole and the first channel through hole is improved, and the electrical performance of the device is ensured.

An exemplary embodiment of a method for fabricating a channel hole provided according to the present invention will be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.

First, asubstrate 100 having a firststacked structure 10 on a surface thereof is provided, a plurality offirst channel vias 210 penetrating through thesubstrate 100 are formed in the firststacked structure 10, afilling layer 211 is formed in each of thefirst channel vias 210, the firststacked structure 10 has at least one cutting region, and thefirst channel vias 210 are located in a region of the firststacked structure 10 except the cutting region, as shown in fig. 1. Theepitaxial layer 30 may be formed at the bottom of the first trench via 210 before thefilling layer 211 is formed.

The material of thesubstrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.

The method for forming the channel hole of the present invention may be applied to different semiconductor device manufacturing processes, where the semiconductor device may be a three-dimensional NAND memory, and at this time, the firststacked structure 10 in the step S1 may be formed by stacking the firstsacrificial layer 110 and thefirst isolation layer 120, as shown in fig. 1, the firstsacrificial layer 110 needs to be removed in a subsequent manufacturing process, and a gate structure contacting a storage structure formed in the first trench via 210 in a region where the firstsacrificial layer 110 is removed is formed.

In the above step of forming the firststacked structure 10, thefirst isolation layer 120 and the firstsacrificial layer 110 may be formed by a conventional deposition process in the prior art, such as a chemical vapor deposition process. The number of the firstsacrificial layer 110 and thefirst isolation layer 120 can be set by those skilled in the art according to practical requirements, and thefirst isolation layer 120 can be SiO₂The firstsacrificial layer 110 may be SiN, but is not limited to the above-mentioned kind, and those skilled in the art can also reasonably select the kinds of thefirst isolation layer 120 and the firstsacrificial layer 110 according to the prior art.

In the step of forming the firststacked structure 10, the first dielectric material forming thefilling layer 211 may be carbon, but is not limited to the above-mentioned kind, and those skilled in the art can reasonably select the kind of the first dielectric material according to the prior art.

After the steps of forming the first trench via 210 and thefilling layer 211, covering theintermediate layer 40 on the surface of the firststacked structure 10, and forming afirst alignment groove 510 in theintermediate layer 40 corresponding to the cutting region by using an overlay process, as shown in fig. 2 and 3.

In the step of forming the first trench via 210, a first alignment mark is simultaneously formed on the firststacked structure 10, and the step of forming thefirst alignment groove 510 by using an overlay process may include: covering a first photoresist layer on the surface of themiddle layer 40, and providing a first mask plate, wherein the first mask plate is provided with a first alignment pattern and a first main body pattern for forming afirst alignment groove 510, the first alignment pattern and the first main body pattern can enable a light source to expose the first photoresist layer, the first mask plate is arranged above the first photoresist layer, the first alignment pattern corresponds to the first alignment mark, then patterning the first photoresist layer through processes of exposure, development and the like, and etching themiddle layer 40 by taking the patterned first photoresist layer as a mask to form thefirst alignment groove 510.

Theintermediate layer 40 may also include a secondsacrificial layer 410 and asecond isolation layer 420 alternately stacked along a direction away from thesubstrate 100, as shown in fig. 2, the secondsacrificial layer 410 needs to be removed in a subsequent manufacturing process, and a gate structure contacting a memory structure subsequently formed in the first trench via 210 is formed in a region where the secondsacrificial layer 410 is removed.

The secondsacrificial layer 410 and thesecond isolation layer 420 can be formed by a conventional deposition process, such as a chemical vapor deposition process. The secondsacrificial layer 410 may have the same material type as the firstsacrificial layer 110, such as SiN, and thesecond isolation layer 420 may have the same material type as thefirst isolation layer 120, such as SiO₂。

In order to ensure that thefirst alignment groove 510 has a sufficient depth, it is preferable that themiddle layer 40 includes at least two sets of the secondsacrificial layer 410 and thesecond isolation layer 420; also, preferably, the first aligninggroove 510 penetrates to the first stackingstructure 10, as shown in fig. 3.

After the steps of forming theintermediate layer 40 and thefirst alignment groove 510, asecond stack structure 60 is formed on theintermediate layer 40, and asecond alignment groove 520 is formed at a position of thesecond stack structure 60 corresponding to thefirst alignment groove 510, as shown in fig. 4. Since a portion of the material is filled in thefirst alignment groove 510 when thesecond stack structure 60 is formed, a recess is formed on the surface of thesecond stack structure 60 corresponding to thefirst alignment groove 510, and the recess is thesecond alignment groove 520.

Thesecond stack structure 60 may include thirdsacrificial layers 610 and third isolation layers 620 alternately stacked in a direction away from thesubstrate 100, as shown in fig. 4. The thirdsacrificial layer 610 needs to be removed in a subsequent manufacturing process, and a gate structure contacting a storage structure formed in the second trench via 220 is formed in a region where the thirdsacrificial layer 610 is removed.

The thirdsacrificial layer 610 and thethird isolation layer 620 may also be formed by a conventional deposition process in the prior art, such as a chemical vapor deposition process. The number of the thirdsacrificial layer 610 and thethird isolation layer 620 can be set by those skilled in the art according to practical requirements, and thethird isolation layer 620 can be SiO₂The thirdsacrificial layer 610 may be SiN, but is not limited to the above-mentioned kind, and those skilled in the art can also reasonably select the kinds of the thirdsacrificial layer 610 and thethird isolation layer 620 according to the prior art.

After the steps of forming thesecond stack structure 60 and thesecond alignment groove 520, forming a second trench throughhole 220 sequentially penetrating through thesecond stack structure 60 and theintermediate layer 40 based on thesecond alignment groove 520 by using an overlay process, removing thefilling layer 211 to communicate the second trench throughhole 220 with the first trench throughhole 210, and forming atrench hole 20 after communicating for forming a memory structure.

In a preferred embodiment, the step of forming the second trench via 220 includes: covering ahard mask 70 on the surface of the secondstacked structure 60, wherein a third alignment groove is formed in a position of thehard mask 70 corresponding to thesecond alignment groove 520; an opening is formed on thehard mask 70 except for the third alignment groove using a photolithography process, and thesecond stack structure 60 is etched through the opening to form a second channel via 220.

In the step of forming thefirst alignment groove 510, a second alignment mark is simultaneously formed on theintermediate layer 40, and the step of forming the second trench via 220 by using an overlay process may include: sequentially covering thehard mask 70 and thesecond photoresist layer 80 on the surface of the secondstacked structure 60, and providing a second mask plate having a second alignment pattern and a second main pattern for forming a second channel via 220, the second alignment pattern and the second main pattern enabling a light source to expose thesecond photoresist layer 80, disposing the second mask plate above thesecond photoresist layer 80, and corresponding the second alignment pattern to the second alignment mark to enable the second main pattern to correspond to the first channel via 210, then patterning thesecond photoresist layer 80 through processes of exposure and development, and etching theintermediate layer 40 using the patternedsecond photoresist layer 80 as a mask to form the second channel via 220.

According to another aspect of the present invention, there is also provided a method for manufacturing a memory, as shown in fig. 1 to 7, including the following steps: forming a stacked structure on thesubstrate 100 by using the above manufacturing method, wherein the stacked structure has achannel hole 20 penetrating through thesubstrate 100, and the stacked structure comprises a sacrificial layer and an isolation layer which are alternately stacked in a direction away from thesubstrate 100; forming a memory structure in thechannel hole 20; forming gate spacers penetrating to thesubstrate 100 in the stacked structure, the gate spacers being located between adjacent channel holes 20 for forming an Array Common Source (ACS); and removing the sacrificial layer and forming a gate layer at the position corresponding to the sacrificial layer.

The above-described stacked structure includes a firststacked structure 10, anintermediate layer 40, and a secondstacked structure 60 sequentially formed on asubstrate 100, the firststacked structure 10 including firstsacrificial layers 110 and first isolation layers 120 alternately stacked in a direction away from thesubstrate 100, theintermediate layer 40 including secondsacrificial layers 410 and second isolation layers 420 alternately stacked in the direction away from thesubstrate 100, and the secondstacked structure 60 including thirdsacrificial layers 610 and third isolation layers 620 alternately stacked in the direction away from thesubstrate 100, as shown in fig. 6.

Thechannel hole 20 is formed by communicating the first channel via 210 and the second channel via 220, thememory structure 500 is formed in thechannel hole 20, and after the firstsacrificial layer 110, the secondsacrificial layer 410 and the thirdsacrificial layer 610 are replaced by thefirst gate structure 130, the secondgate stack structure 430 and thethird gate structure 630, respectively, thememory structure 500 is in contact with the gate layers, respectively, as shown in fig. 7.

In a preferred embodiment, the step of forming the memory structure comprises: a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer are sequentially formed on sidewalls of the channel hole in a stacked manner.

The material of each functional layer in the memory structure can be reasonably selected by those skilled in the art according to the prior art, such as the material of the charge blocking layerThe material can be SiO₂The charge trapping layer may be SiN and the tunneling layer may be SiO₂The material of the channel layer may be polysilicon. Moreover, a person skilled in the art may form the above memory structure by a conventional deposition process in the prior art, and details thereof are not repeated herein.

In a preferred embodiment, gate isolation trenches penetrating through thesubstrate 100 are formed in the cutting region of the stacked structure where thesecond alignment trench 520 is formed.

According to another aspect of the present invention, there is also provided a memory, as shown in fig. 7, including asubstrate 100 having a dual gate stack structure including a firstgate stack structure 200, an intermediategate stack structure 300, and a secondgate stack structure 400 sequentially stacked in a direction away from thesubstrate 100, the firstgate stack structure 200 having a first channel via 210 penetrating to thesubstrate 100 therein, the intermediategate stack structure 300 and the secondgate stack structure 400 having a second channel via 220 communicating with the first channel via 210 therein, and amemory structure 500 located in the communicating first channel via 210 and second channel via 220, the side of the middlegate stack structure 300 away from thesubstrate 100 has afirst alignment groove 510, a portion of the secondgate stack structure 400 is filled in thefirst alignment groove 510, the surface of the second gate stack structure away from thesubstrate 100 has asecond alignment groove 520 corresponding to thefirst alignment groove 510.

In the secondgate stack structure 400, a portion of the same film layer corresponding to thefirst alignment trench 510 is recessed downward, as shown in fig. 7.

In the above memory, the firstgate stack structure 200 includes thefirst spacers 120 and thefirst gate structures 130 which are alternately stacked, the middlegate stack structure 300 includes thesecond spacers 420 and the secondgate stack structures 430 which are alternately stacked, and the secondgate stack structure 400 includes thethird spacers 620 and thethird gate structures 630 which are alternately stacked, as shown in fig. 7.

From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:

by adopting the manufacturing method of the channel hole, the deviation of the forming position of the first alignment groove is reduced by carrying out alignment in the step of forming the first alignment groove; and then, the deviation of the forming position of the second channel through hole is reduced through the alignment of the overlay in the step of forming the second channel through hole, so that the alignment precision between the second channel through hole and the first channel through hole is improved, and the electrical performance of the device is ensured.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

Translated fromChinese

1.一种沟道孔的制作方法，其特征在于，包括以下步骤：1. a preparation method of channel hole, is characterized in that, comprises the following steps:提供表面具有第一堆叠结构(10)的衬底(100)，所述第一堆叠结构(10)中形成有贯穿至所述衬底(100)的多个第一沟道通孔(210)，在各所述第一沟道通孔(210)中形成填充层(211)，所述第一堆叠结构(10)具有至少一个切割区域，所述第一沟道通孔(210)位于所述第一堆叠结构(10)中除所述切割区域之外的区域中；A substrate (100) having a surface with a first stack structure (10) is provided, and a plurality of first channel vias (210) penetrating to the substrate (100) are formed in the first stack structure (10) , forming a filling layer (211) in each of the first channel through holes (210), the first stack structure (10) having at least one cutting region, and the first channel through holes (210) are located in the in the region other than the cutting region in the first stacked structure (10);在所述第一堆叠结构(10)表面覆盖中间层(40)，在与所述切割区域对应的所述中间层(40)中形成第一对位槽(510)；An intermediate layer (40) is covered on the surface of the first stacked structure (10), and a first alignment groove (510) is formed in the intermediate layer (40) corresponding to the cutting area;在所述中间层(40)上形成第二堆叠结构(60)，所述第二堆叠结构(60)对应于所述第一对位槽(510)的位置形成有第二对位槽(520)；A second stack structure (60) is formed on the intermediate layer (40), and a second alignment groove (520) is formed at a position of the second stack structure (60) corresponding to the first alignment groove (510). );基于所述第二对位槽(520)，采用套刻工艺形成顺序贯穿所述第二堆叠结构(60)和中间层(40)至所述填充层(211)的第二沟道通孔(220)，去除所述填充层(211)以使所述第二沟道通孔(220)与所述第一沟道通孔(210)连通，Based on the second alignment groove (520), an overlay process is used to form a second channel through hole ( 220), removing the filling layer (211) to make the second channel through hole (220) communicate with the first channel through hole (210),所述第一堆叠结构(10)包括沿远离所述衬底(100)的方向交替层叠的第一牺牲层(110)和第一隔离层(120)；The first stacked structure (10) comprises a first sacrificial layer (110) and a first isolation layer (120) alternately stacked in a direction away from the substrate (100);所述中间层(40)包括沿远离所述衬底(100)的方向交替层叠的第二牺牲层(410)和第二隔离层(420)；The intermediate layer (40) includes a second sacrificial layer (410) and a second isolation layer (420) alternately stacked in a direction away from the substrate (100);所述第二堆叠结构(60)包括沿远离所述衬底(100)的方向交替层叠的第三牺牲层(610)和第三隔离层(620)，The second stacked structure (60) includes a third sacrificial layer (610) and a third isolation layer (620) alternately stacked in a direction away from the substrate (100),所述第一对位槽(510)贯穿所述中间层(40)；The first alignment groove (510) runs through the intermediate layer (40);所述第一对位槽(510)贯穿至所述第一堆叠结构(10)中。The first alignment groove (510) penetrates into the first stack structure (10).2.根据权利要求1所述的制作方法，其特征在于，所述中间层(40)包括至少两组所述第二牺牲层(410)和所述第二隔离层(420)。2. The manufacturing method according to claim 1, wherein the intermediate layer (40) comprises at least two groups of the second sacrificial layer (410) and the second isolation layer (420).3.根据权利要求1所述的制作方法，其特征在于，采用光刻工艺在与所述切割区域对应的所述中间层(40)中形成所述第一对位槽(510)。3. The manufacturing method according to claim 1, characterized in that, the first alignment groove (510) is formed in the intermediate layer (40) corresponding to the cutting region by using a photolithography process.4.根据权利要求1所述的制作方法，其特征在于，形成所述第二沟道通孔(220)的步骤包括：4. The manufacturing method according to claim 1, wherein the step of forming the second channel via (220) comprises:在所述第二堆叠结构(60)表面覆盖硬掩膜(70)，所述硬掩膜(70)对应于所述第二对位槽(520)的位置形成第三对位槽；A hard mask (70) is covered on the surface of the second stack structure (60), and a third alignment groove is formed on the hard mask (70) corresponding to the position of the second alignment groove (520);采用光刻工艺在所述硬掩膜(70)上除所述第三对位槽之外的位置形成开口，通过所述开口对所述第二堆叠结构(60)进行刻蚀，以形成所述第二沟道通孔(220)，所述开口与所述第一沟道通孔(210)一一对应。A photolithography process is used to form openings on the hard mask (70) at positions other than the third alignment grooves, and the second stack structure (60) is etched through the openings to form the The second channel through holes (220) are in a one-to-one correspondence with the first channel through holes (210).5.一种存储器的制作方法，其特征在于，包括以下步骤：5. a preparation method of memory, is characterized in that, comprises the following steps:采用权利要求1至4中任一项所述的制作方法在衬底(100)上形成具有堆叠结构，所述堆叠结构中具有贯穿至所述衬底(100)的沟道孔(20)，所述堆叠结构包括沿远离所述衬底(100)的方向交替层叠的牺牲层和隔离层；A stacked structure is formed on the substrate (100) by using the manufacturing method according to any one of claims 1 to 4, and the stacked structure has a channel hole (20) penetrating to the substrate (100), The stacked structure includes alternately stacked sacrificial layers and isolation layers in a direction away from the substrate (100);在所述沟道孔(20)中形成存储结构；forming a memory structure in the channel hole (20);在所述堆叠结构中形成贯穿至所述衬底(100)的栅极隔槽，所述栅极隔槽位于相邻所述沟道孔(20)之间；forming gate spacers penetrating to the substrate (100) in the stacked structure, the gate spacers being located between adjacent channel holes (20);去除所述牺牲层，并在对应所述牺牲层的位置形成栅极层。The sacrificial layer is removed, and a gate layer is formed at a position corresponding to the sacrificial layer.6.根据权利要求5所述的制作方法，其特征在于，形成所述存储结构的步骤包括：6. The manufacturing method according to claim 5, wherein the step of forming the storage structure comprises:在所述沟道孔(20)的侧壁上顺序形成层叠的电荷阻挡层、电子捕获层、隧穿层和沟道层。A stacked charge blocking layer, an electron trapping layer, a tunneling layer and a channel layer are sequentially formed on the sidewall of the channel hole (20).7.根据权利要求5所述的制作方法，其特征在于，在所述堆叠结构的形成有第二对位槽(520)的切割区域形成贯穿至所述衬底(100)的所述栅极隔槽。7 . The manufacturing method according to claim 5 , wherein the gate electrode penetrating to the substrate ( 100 ) is formed in the cutting region of the stacked structure where the second alignment groove ( 520 ) is formed. 8 . Slot.8.一种存储器，其特征在于，包括具有双栅极堆叠结构的衬底(100)和存储结构(500)，所述双栅极堆叠结构包括沿远离所述衬底(100)方向顺序层叠的第一栅极堆叠结构(200)、中间栅极堆叠结构(300)和第二栅极堆叠结构(400)，所述第一栅极堆叠结构(200)中具有贯穿至所述衬底(100)的第一沟道通孔(210)，所述中间栅极堆叠结构(300)和所述第二栅极堆叠结构(400)中具有与所述第一沟道通孔(210)连通的第二沟道通孔(220)，所述存储结构位于连通的所述第一沟道通孔(210)与所述第二沟道通孔(220)中，所述中间栅极堆叠结构(300)远离所述衬底(100)的一侧具有第一对位槽(510)，所述第二栅极堆叠结构(400)中的部分填充于所述第一对位槽(510)中，所述第二栅极堆叠结构远离所述衬底(100)的一侧表面具有与所述第一对位槽(510)对应的第二对位槽(520)，8. A memory, characterized by comprising a substrate (100) having a double gate stack structure and a memory structure (500), the double gate stack structure comprising sequentially stacking in a direction away from the substrate (100) A first gate stack structure (200), an intermediate gate stack structure (300), and a second gate stack structure (400), wherein the first gate stack structure (200) has a penetration through the substrate ( 100) of the first channel through hole (210), the intermediate gate stack structure (300) and the second gate stack structure (400) have communication with the first channel through hole (210) the second channel through hole (220), the storage structure is located in the connected first channel through hole (210) and the second channel through hole (220), the intermediate gate stack structure (300) a side away from the substrate (100) has a first alignment groove (510), and a part of the second gate stack structure (400) is filled in the first alignment groove (510) wherein, a side surface of the second gate stack structure away from the substrate (100) has a second alignment groove (520) corresponding to the first alignment groove (510),所述第一栅极堆叠结构(200)包括交替层叠的第一隔离层(120)和第一栅极结构(130)，The first gate stack structure (200) includes alternately stacked first isolation layers (120) and first gate structures (130),所述中间栅极堆叠结构(300)包括交替层叠的第二隔离层(420)和第二栅极结构(430)，The intermediate gate stack structure (300) includes alternately stacked second isolation layers (420) and second gate structures (430),所述第二栅极堆叠结构(400)包括交替层叠的第三隔离层(620)和第三栅极结构(630)，The second gate stack structure (400) includes alternately stacked third isolation layers (620) and third gate structures (630),所述第一对位槽(510)贯穿所述中间栅极堆叠结构(300)；The first alignment groove (510) penetrates the intermediate gate stack structure (300);所述第一对位槽(510)贯穿至所述第一栅极堆叠结构(200)。The first alignment groove (510) penetrates to the first gate stack structure (200).

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