技术领域Technical field
本发明涉及电子元器件检测技术领域,尤其涉及一种NAND FLASH存储器并行测试及坏块回写方法。The invention relates to the technical field of electronic component detection, and in particular to a NAND FLASH memory parallel test and bad block write-back method.
背景技术Background technique
NAND FLASH属于非易失性存储器,具有掉电后数据不丢失的特点。和传统的NORFLASH相比,NAND FLASH具有容量大、性价比高、擦写次数多、存储寿命长等优点,但是NANDFLASH的缺点在于其存储阵列内部具有坏块,并且随着使用频率的增加坏块数量会随之增加。NAND FLASH is a non-volatile memory that does not lose data after power failure. Compared with traditional NORFLASH, NAND FLASH has the advantages of large capacity, high cost performance, high number of erasing and writing, and long storage life. However, the disadvantage of NAND FLASH is that there are bad blocks inside the storage array, and the number of bad blocks increases with the frequency of use. will increase accordingly.
普通存储器如SRAM、EPROM、NOR FLASH的测试逻辑为:将其所有存储阵列按照一定的规则写入数据,等待写入完成之后读出,对比读出的数据与写入的数据是否一致,出现不一致则判定存储器不合格。测试过程不需要进行跳转和多次判断,直接比对数据即可得出测试结论。NAND FLASH实际测试时,整个测试过程中需进行多次判断被测块的质量,每次需根据判断的结果来决定下一步的测试内容;并且,由于存储器的差异,坏块出现的地址不同,决定了测试图形向量的长度和内容并不完全相同,即同一型号不同存储器的测试图形未必相同。The test logic of ordinary memories such as SRAM, EPROM, and NOR FLASH is: write data to all storage arrays according to certain rules, wait for the writing to be completed, and then read out the data. Compare whether the read data is consistent with the written data. If there is any inconsistency, Then the memory is judged to be unqualified. The test process does not require jumps and multiple judgments. Test conclusions can be drawn by directly comparing the data. When NAND FLASH is actually tested, the quality of the tested block needs to be judged multiple times during the entire test process. Each time, the next test content needs to be determined based on the judgment results; and due to differences in memory, the addresses where bad blocks appear are different. This determines that the length and content of the test pattern vectors are not exactly the same, that is, the test patterns of different memories of the same model may not be the same.
因此不能使用统一的随机图形向量法对NAND FLASH进行测试,现有的测试技术只能单独对一个NAND FLASH进行测试,无法对多个NAND FLASH进行并行测试。但NAND FALSH容量一般为若干个GB,写入数据操作和擦除操作都需要等待一定的时间,随着容量的不断增加,单独对1个NAND FALSH进行测试的测试成本太高,同时会造成资源的极大浪费。Therefore, the unified random graphic vector method cannot be used to test NAND FLASH. The existing testing technology can only test one NAND FLASH individually and cannot test multiple NAND FLASH in parallel. However, the capacity of NAND FALSH is generally several GB, and writing data operations and erasing operations require a certain amount of time. As the capacity continues to increase, the cost of testing a NAND FALSH separately is too high, and at the same time it will consume resources. A huge waste.
发明内容Contents of the invention
为解决上述问题,本发明提出一种NAND FLASH存储器并行测试及坏块回写方法,解决现有技术中无法对多个NAND FLASH存储器进行并行测试的问题。In order to solve the above problems, the present invention proposes a method for parallel testing and bad block write-back of NAND FLASH memories to solve the problem in the prior art that multiple NAND FLASH memories cannot be tested in parallel.
本发明采用如下技术方案:The present invention adopts the following technical solutions:
一种NAND FLASH存储器并行测试及坏块回写方法,该方法包括:A method for parallel testing and bad block write-back of NAND FLASH memory, which method includes:
读取多个存储器ID并将存储器ID与预设ID进行比较,根据比较结果判断每个存储器是否初步合格;Read multiple memory IDs and compare the memory ID with the preset ID, and determine whether each memory is initially qualified based on the comparison results;
在存储器为初步合格的情况下,判断初步合格的存储器中每一个逻辑单元的第0块是否为非坏块;When the memory is preliminarily qualified, determine whether the 0th block of each logical unit in the preliminarily qualified memory is a non-bad block;
针对每一个逻辑单元的第0块为非坏块的存储器,分别确定每一个存储器中每一个逻辑单元的初始坏块数量;For a memory where the 0th block of each logical unit is a non-bad block, determine the initial number of bad blocks for each logical unit in each memory;
判断每一个第0块为非坏块的存储器是否为空片;Determine whether each memory whose 0th block is a non-bad block is an empty slice;
在每一个第0块为非坏块的存储器为空片的情况下,识别出测试过程中新产生的坏块,分别确定为空片的存储器中每一个逻辑单元的新产生的坏块数量并按照预定规则对新产生的坏块进行回写;In the case where each memory whose 0th block is a non-bad block is an empty slice, the newly generated bad blocks during the test process are identified, and the number of newly generated bad blocks in each logical unit of the memory that is an empty slice is determined and Write back newly generated bad blocks according to predetermined rules;
基于为空片的存储器中每一个逻辑单元的初始坏块数量和新产生的坏块数量判断对应存储器是否合格。Based on the initial number of bad blocks and the number of newly generated bad blocks in each logical unit of the empty memory, it is judged whether the corresponding memory is qualified.
优选的,根据比较结果判断每个存储器是否初步合格包括:若存储器ID与预设ID匹配,则ID匹配的存储器判定为初步合格;若存储器ID与预设ID不匹配,则ID不匹配的存储器判定为初步不合格。Preferably, judging whether each memory is preliminarily qualified according to the comparison result includes: if the memory ID matches the preset ID, then the memory with matching ID is determined to be preliminarily qualified; if the memory ID does not match the preset ID, then the memory with unmatched ID is determined to be preliminarily qualified. Determined as preliminary failure.
优选的,该方法还包括:读取匹配失效管脚的数据;将匹配失效管脚的数据与预设ID的数据不一致的存储器定位为初步不合格的存储器。Preferably, the method further includes: reading data matching the failed pin; and locating the memory whose data matching the failed pin is inconsistent with the data of the preset ID as a preliminary unqualified memory.
优选的,判断初步合格的存储器中每一个逻辑单元的第0块是否为非坏块包括:读取初步合格的存储器中每一个逻辑单元的第0块的数据;基于读取的数据验证第0块是否为空;对第0块为空的每一个存储器中每一个逻辑单元的第0块写入数据;读取所述写入数据,并判断写入的数据与读取的数据是否一致,若一致确定第0块为非坏块,否则确定第0块为坏块。Preferably, judging whether the 0th block of each logical unit in the preliminarily qualified memory is a non-bad block includes: reading the data of the 0th block of each logical unit in the preliminarily qualified memory; verifying the 0th block based on the read data Whether the block is empty; write data to the 0th block of each logical unit in each memory where the 0th block is empty; read the written data, and determine whether the written data is consistent with the read data, If the block 0 is unanimously determined to be a non-bad block, otherwise the block 0 is determined to be a bad block.
优选的,分别确定每一个存储器中每一个逻辑单元的初始坏块数量包括:读取每一个存储器中每一个逻辑单元中的预先标注的坏块字节;对读取到坏块字节的次数进行累加得到每一个存储器中每一个逻辑单元的坏块数量。Preferably, determining the initial number of bad blocks in each logical unit in each memory includes: reading pre-marked bad block bytes in each logical unit in each memory; counting the number of times the bad block bytes are read Accumulate to obtain the number of bad blocks for each logical unit in each memory.
优选的,判断每一个第0块为非坏块的存储器是否为空片包括:对每一个第0块为非坏块的存储器的所有逻辑单元进行所有块的全片读取,全片读取为对块从第0块遍历到第Z块;判断当前遍历的块是否为初始坏块;在当前遍历的块不是初始坏块的情况下,进行数据读取;在当前遍历的块是初始坏块的情况下,不进行数据读取,等待其他存储器完成当前遍历的块的数据读取后,同步进行下一个块的数据读取;若读取到存储器中所有逻辑单元的所有块的数据均为空,则所有块的数据均为空的存储器为空片;若读取到存储器中任意一个逻辑单元的任意一个块的数据为非空,则任意一个块的数据为非空的存储器为非空片。Preferably, determining whether each memory with block 0 being a non-bad block is an empty slice includes: performing a full-chip read of all blocks in all logical units of a memory with block 0 being a non-bad block. To traverse the blocks from block 0 to block Z; determine whether the currently traversed block is the initial bad block; when the currently traversed block is not the initial bad block, read the data; when the currently traversed block is the initial bad block In the case of blocks, no data is read, and the data of the next block is read synchronously after other memories have completed reading the data of the currently traversed block; if the data of all blocks of all logical units in the memory are read, is empty, then the data of all blocks are empty and the memory is an empty slice; if the data of any block of any logical unit in the memory is non-empty, then the data of any block is non-empty and the memory is non-empty. Empty piece.
优选的,识别出测试过程中新产生的坏块,分别确定为空片的存储器中每一个逻辑单元的新产生的坏块数量并按照预定规则对新产生的坏块进行回写包括:判断每一个存储器的每一个逻辑单元的每一块是否为初始坏块;在当前块是初始坏块的情况下,不进行识别操作,等待其他存储器完成当前块的识别操作后,同步进行下一个块的识别操作;对识别出的新产生的坏块的次数进行累加得到为空片的存储器中每一个逻辑单元的新产生的坏块数量;对识别出的新产生的坏块按照预定规则进行回写;其中,识别操作包括:在当前块不是初始坏块的情况下,进行数据写入和读取;判断所述写入数据与所述读取数据是否一致,若一致,则当前块为非坏块,否则当前块为新产生的坏块;对新产生的坏块进行数据擦除。Preferably, identifying newly generated bad blocks during the test process, determining the number of newly generated bad blocks for each logical unit in the memory that is an empty slice, and writing back the newly generated bad blocks according to predetermined rules includes: judging each Whether each block of each logical unit of a memory is an initial bad block; if the current block is an initial bad block, no identification operation is performed, and the next block is identified synchronously after waiting for other memories to complete the identification operation of the current block. Operation: Accumulate the number of identified newly generated bad blocks to obtain the number of newly generated bad blocks for each logical unit in the empty memory; write back the identified newly generated bad blocks according to predetermined rules; Wherein, the identification operation includes: writing and reading data when the current block is not an initial bad block; judging whether the written data is consistent with the read data. If they are consistent, the current block is a non-bad block. , otherwise the current block is a newly generated bad block; perform data erasure on the newly generated bad block.
优选的,写入数据的格式包括全0、棋盘格和反棋盘格,上一种格式的数据写入读取和擦除之后再进行下一种格式的数据的写入读取和擦除。Preferably, the formats for writing data include all 0s, checkerboard and reverse checkerboard. After the data in the previous format is written, read and erased, the data in the next format is written, read and erased.
优选的,该方法还包括:在所述上一种格式的数据写入读取和擦除之后,判断当前块内的数据是否为空,在当前块内的数据为空的情况下,进行下一种格式的数据的写入读取和擦除。Preferably, the method also includes: after writing, reading and erasing data in the previous format, judging whether the data in the current block is empty, and if the data in the current block is empty, proceed to the next step. A format of data is written, read and erased.
优选的,基于为空片的存储器中每一个逻辑单元的初始坏块数量和新产生的坏块数量判断存储器是否合格包括:若为空片的存储器中每一个逻辑单元的初始坏块的数量与新产生的坏块的数量之和均不超过预定数量,则判定存储器合格;若为空片的存储器中任意一个逻辑单元的初始坏块的数量与新产生的坏块的数量之和超过预定数量,则判定存储器不合格。Preferably, judging whether the memory is qualified based on the initial number of bad blocks of each logical unit in the memory that is an empty slice and the number of newly generated bad blocks includes: if the number of initial bad blocks of each logical unit in the memory that is an empty slice is equal to If the sum of the number of newly generated bad blocks does not exceed the predetermined number, the memory is judged to be qualified; if the sum of the number of initial bad blocks and the number of newly generated bad blocks in any logical unit in the empty memory exceeds the predetermined number , then the memory is judged to be unqualified.
本发明提供的NAND FLASH存储器并行测试及坏块回写方法,该方法先读取多个存储器ID判断每个存储器是否初步合格,在存储器为初步合格的情况下,判断初步合格的存储器中每一个逻辑单元的第0块是否为非坏块,在存储器第0块为非坏块的情况下,分别确定每一个存储器中每一个逻辑单元的初始坏块数量,在每一个第0块为非坏块的存储器为空片的情况下,识别出测试过程中新产生的坏块,按照预定规则对新产生的坏块进行回写,最后基于为空片的存储器中每一个逻辑单元的初始坏块数量和新产生的坏块数量判断存储器是否合格。本发明的NAND FLASH存储器并行测试及坏块回写方法能够实现多个NANDFLASH存储器的并行测试,能够有效识别出测试过程中新产生的坏块并进行回写,提升了测试效率,同时对预设的原有标志位进行了保护。The present invention provides a NAND FLASH memory parallel test and bad block write-back method. This method first reads multiple memory IDs to determine whether each memory is initially qualified. When the memory is initially qualified, it determines each of the initially qualified memories. Whether the 0th block of the logical unit is a non-bad block. If the 0th block of the memory is a non-bad block, determine the initial number of bad blocks for each logical unit in each memory. If each 0th block is a non-bad block, When the memory of the block is empty, identify the newly generated bad blocks during the test process, write back the newly generated bad blocks according to predetermined rules, and finally based on the initial bad blocks of each logical unit in the memory that is empty. The number and the number of newly generated bad blocks determine whether the memory is qualified. The NAND FLASH memory parallel testing and bad block write-back method of the present invention can realize parallel testing of multiple NAND FLASH memories, can effectively identify newly generated bad blocks during the test process and perform write-back, which improves test efficiency and at the same time presets The original flag bits have been protected.
附图说明Description of the drawings
所包括的附图用来提供对本发明实施例的进一步的理解,其构成了说明书的一部分,用于例示本发明的实施例,并与文字描述一起来阐释本发明的原理。显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。The accompanying drawings are included to provide a further understanding of the embodiments of the invention, and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.
图1是本发明NAND FLASH存储器并行测试及坏块回写方法的流程示意图。Figure 1 is a schematic flow chart of the NAND FLASH memory parallel testing and bad block writeback method of the present invention.
图2是本发明具体实施例中步骤一的流程示意图。Figure 2 is a schematic flow chart of step one in a specific embodiment of the present invention.
图3是本发明具体实施例中步骤二的流程示意图。Figure 3 is a schematic flow chart of step two in a specific embodiment of the present invention.
图4是本发明具体实施例中步骤三的流程示意图。Figure 4 is a schematic flowchart of step three in a specific embodiment of the present invention.
图5是本发明具体实施例中步骤四的流程示意图。Figure 5 is a schematic flowchart of step four in a specific embodiment of the present invention.
图6是本发明具体实施例中步骤五的流程示意图。Figure 6 is a schematic flowchart of step five in a specific embodiment of the present invention.
具体实施方式Detailed ways
需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。以下对至少一个示例性实施例的描述实际上仅仅是说明性的,决不作为对本发明及其应用或使用的任何限制。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application or uses. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.
需要注意的是,这里所使用的术语仅是为了描述具体实施方式,而非意图限制根据本申请的示例性实施方式。如在这里所使用的,除非上下文另外明确指出,否则单数形式也意图包括复数形式,此外,还应当理解的是,当在本说明书中使用术语“包含”和/或“包括”时,其指明存在特征、步骤、操作、器件、组件和/或它们的组合。It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular forms are also intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, it will be understood that when the terms "comprises" and/or "includes" are used in this specification, they indicate There are features, steps, operations, means, components and/or combinations thereof.
图1是本发明NAND FLASH存储器并行测试及坏块回写方法的流程示意图。参照图1,本发明提出一种NAND FLASH存储器并行测试及坏块回写方法,该方法包括:步骤一、读取多个存储器ID并将存储器ID与预设ID进行比较,根据比较结果判断每个存储器是否初步合格;步骤二、在存储器为初步合格的情况下,判断初步合格的存储器中每一个逻辑单元(LUN)的第0块是否为非坏块;步骤三、针对每一个LUN的第0块为非坏块的存储器,分别确定每一个存储器中每一个LUN的初始坏块数量;步骤四、判断每一个第0块为非坏块的存储器是否为空片;在每一个第0块为非坏块的存储器为空片的情况下,识别出测试过程中新产生的坏块,分别确定为空片的存储器中每一个LUN的新产生的坏块数量并按照预定规则对新产生的坏块进行回写;步骤六、基于为空片的存储器中每一个LUN的初始坏块数量和新产生的坏块数量判断对应存储器是否合格。Figure 1 is a schematic flow chart of the NAND FLASH memory parallel testing and bad block writeback method of the present invention. Referring to Figure 1, the present invention proposes a NAND FLASH memory parallel test and bad block write-back method. The method includes: Step 1: Read multiple memory IDs and compare the memory IDs with preset IDs, and determine each memory ID based on the comparison results. Whether the memory is preliminarily qualified; Step 2: When the memory is preliminarily qualified, determine whether the 0th block of each logical unit (LUN) in the preliminarily qualified memory is a non-bad block; Step 3. For each LUN, the 0th block For storage with block 0 as non-bad blocks, determine the initial number of bad blocks for each LUN in each storage respectively; Step 4: Determine whether each storage with block 0 as non-bad blocks is empty; in each block 0 When the storage with non-bad blocks is empty, identify the newly generated bad blocks during the test, determine the number of newly generated bad blocks for each LUN in the storage with empty blocks, and classify the newly generated bad blocks according to predetermined rules. The bad blocks are written back; Step 6: Determine whether the corresponding memory is qualified based on the initial number of bad blocks and the number of newly generated bad blocks of each LUN in the empty memory.
本发明步骤一中若存储器ID与预设ID匹配,则与预设ID匹配的存储器判定为初步合格;若存储器ID与预设ID不匹配,则与预设ID不匹配的存储器判定为初步不合格。通过读取匹配失效管脚的数据,然后将匹配失效管脚的数据与预设ID的数据不一致的存储器定位为初步不合格的存储器。In step one of the present invention, if the memory ID matches the preset ID, the memory that matches the preset ID is determined to be preliminarily qualified; if the memory ID does not match the preset ID, the memory that does not match the preset ID is determined to be preliminarily unqualified. qualified. By reading the data matching the failed pin, and then locating the memory whose data matching the failed pin is inconsistent with the data of the preset ID as a preliminary unqualified memory.
本发明步骤二中判断初步合格的存储器中每一个LUN的第0块是否为非坏块包括如下步骤:读取初步合格的存储器中每一个LUN的第0块的数据;基于读取的数据验证第0块是否为空;对第0块为空的每一个存储器中每一个LUN的第0块写入数据;读取所述写入数据,并判断写入的数据与读取的数据是否一致,若一致确定第0块为非坏块,否则确定第0块为坏块。In the second step of the present invention, judging whether the 0th block of each LUN in the preliminary qualified memory is a non-bad block includes the following steps: reading the data of the 0th block of each LUN in the preliminary qualified memory; verifying based on the read data Whether the 0th block is empty; write data to the 0th block of each LUN in each storage where the 0th block is empty; read the written data, and determine whether the written data is consistent with the read data , if the 0th block is unanimously determined to be a non-bad block, otherwise the 0th block is determined to be a bad block.
本发明步骤三中分别确定每一个存储器中每一个LUN的初始坏块数量包括如下步骤:读取每一个存储器中每一个LUN中的预先标注的坏块字节;对读取到坏块字节的次数进行累加得到每一个存储器中每一个LUN的坏块数量。In the third step of the present invention, determining the initial number of bad blocks for each LUN in each storage includes the following steps: reading the pre-marked bad block bytes in each LUN in each storage; Accumulate the number of times to obtain the number of bad blocks for each LUN in each storage.
本发明步骤四中判断每一个第0块为非坏块的存储器是否为空片包括如下步骤:对每一个第0块为非坏块的存储器的所有LUN进行所有块的全片读取,全片读取为对块从第0块遍历到第Z块;判断当前遍历的块是否为初始坏块;在当前遍历的块不是初始坏块的情况下,进行数据读取;在当前遍历的块是初始坏块的情况下,不进行数据读取,等待其他存储器完成当前遍历的块的数据读取后,同步进行下一个块的数据读取;若读取到存储器中所有LUN的所有块的数据均为空,则所有块的数据均为空的存储器为空片;若读取到存储器中任意一个LUN的任意一个块的数据为非空,则任意一个块的数据为非空的存储器为非空片。In the fourth step of the present invention, determining whether each memory block with the 0th block as a non-bad block is an empty slice includes the following steps: read the entire block of all LUNs of the memory with the 0th block as a non-bad block. Block reading is to traverse the blocks from block 0 to block Z; determine whether the currently traversed block is the initial bad block; when the currently traversed block is not the initial bad block, perform data reading; in the currently traversed block In the case of an initial bad block, no data reading is performed, and the data of the next block is read synchronously after other storages have completed reading the data of the currently traversed block; if the data of all blocks of all LUNs in the storage are read, If the data is all empty, then the data of all blocks is empty and the memory is an empty slice; if the data of any block of any LUN in the memory is read to be non-empty, then the data of any block is non-empty and the memory is Not an empty piece.
本发明步骤五中识别出测试过程中新产生的坏块,分别确定为空片的存储器中每一个LUN的新产生的坏块数量并按照预定规则对新产生的坏块进行回写包括:判断每一个存储器的每一个LUN的每一块是否为初始坏块;在当前块是初始坏块的情况下,不进行识别操作,等待其他存储器完成当前块的识别操作后,同步进行下一个块的识别操作;对识别出的新产生的坏块的次数进行累加得到为空片的存储器中每一个LUN的新产生的坏块数量;对识别出的新产生的坏块按照预定规则进行回写;其中,识别操作包括:在当前块不是初始坏块的情况下,进行数据写入和读取;判断所述写入数据与所述读取数据是否一致,若一致,则当前块为非坏块,否则当前块为新产生的坏块;对新产生的坏块进行数据擦除。In step five of the present invention, newly generated bad blocks are identified during the test process, the number of newly generated bad blocks for each LUN in the empty memory is determined, and the newly generated bad blocks are written back according to predetermined rules, including: Judgment Whether each block of each LUN of each storage is an initial bad block; if the current block is an initial bad block, no identification operation is performed, and the next block is identified synchronously after waiting for other storages to complete the identification operation of the current block. Operation; accumulate the number of newly generated bad blocks identified to obtain the number of newly generated bad blocks for each LUN in the empty memory; write back the identified newly generated bad blocks according to predetermined rules; where , the identification operation includes: writing and reading data when the current block is not the initial bad block; judging whether the written data is consistent with the read data, and if they are consistent, the current block is a non-bad block, Otherwise, the current block is a newly generated bad block; data will be erased on the newly generated bad block.
本发明步骤六中基于为空片的存储器中每一个LUN的初始坏块数量和新产生的坏块数量判断存储器是否合格包括如下步骤:若为空片的存储器中每一个LUN的初始坏块的数量与新产生的坏块的数量之和均不超过预定数量,则判定存储器合格;若为空片的存储器中任意一个LUN的初始坏块的数量与新产生的坏块的数量之和超过预定数量,则判定存储器不合格。In step six of the present invention, judging whether the memory is qualified based on the initial number of bad blocks and the number of newly generated bad blocks of each LUN in the empty memory includes the following steps: If the initial bad blocks of each LUN in the empty memory are If the sum of the number of initial bad blocks and the number of newly generated bad blocks does not exceed the predetermined number, the memory is judged to be qualified; if the sum of the number of initial bad blocks and the number of newly generated bad blocks of any LUN in the empty memory exceeds the predetermined number quantity, the memory is judged to be unqualified.
本发明上述步骤中的写入数据的格式包括全0、棋盘格和反棋盘格,上一种格式的数据写入读取和擦除之后再进行下一种格式的数据的写入读取和擦除。在所述上一种格式的数据写入读取和擦除之后,判断当前块内的数据是否为空,在当前块内的数据为空的情况下,进行下一种格式的数据的写入读取和擦除。The formats of writing data in the above steps of the present invention include all zeros, checkerboard and reverse checkerboard. After the data of the previous format is written, read and erased, the data of the next format is written, read and erased. Erase. After the data in the previous format is written, read and erased, it is determined whether the data in the current block is empty. If the data in the current block is empty, the data in the next format is written. Read and erase.
本发明的上述方法中数据读取操作通过块读取模块执行,数据写入操作通过块编程模块执行,数据擦除操作通过块擦除模块执行,坏块字节的读取通过字节随机读取模块执行,坏块的回写通过字节随机写入模块执行;确定初始坏块数量通过初始坏块累加模块执行;确定新产生的坏块数量通过新坏块累加模块执行;对坏块存储器片选信号的拉高操作通过坏块处理模块执行。In the above method of the present invention, the data reading operation is performed through the block reading module, the data writing operation is performed through the block programming module, the data erasing operation is performed through the block erasing module, and the bad block bytes are read through byte random reading. Fetch module is executed, and the write-back of bad blocks is executed by the byte random writing module; determining the initial number of bad blocks is executed by the initial bad block accumulation module; determining the number of newly generated bad blocks is executed by the new bad block accumulation module; the bad block memory is The chip select signal is pulled high through the bad block processing module.
为方便说明,给出两个NAND FLASH存储器并行测试及坏块回写的具体实施例。图2是本发明具体实施例中步骤一的流程示意图。步骤一、读取多个存储器ID并判断每个存储器是否初步合格。参照图2,读取多个存储器ID,若存储器ID与预设ID不匹配,则与预设ID不匹配的存储器判定为初步不合格。通过读取匹配失效管脚的数据,将匹配失效管脚的数据与预设ID的数据不一致的存储器定位为初步不合格的存储器。For convenience of explanation, a specific example of parallel testing and bad block writeback of two NAND FLASH memories is given. Figure 2 is a schematic flow chart of step one in a specific embodiment of the present invention. Step 1: Read multiple memory IDs and determine whether each memory is initially qualified. Referring to FIG. 2 , multiple memory IDs are read. If the memory ID does not match the preset ID, the memory that does not match the preset ID is determined to be initially unqualified. By reading the data matching the failed pin, the memory whose data matching the failed pin is inconsistent with the data of the preset ID is located as a preliminary unqualified memory.
图3是本发明具体实施例中步骤二的流程示意图。假设上述两个存储器均为初步合格,进行步骤二,判断两个初步合格的存储器中每一个LUN的第0块是否为非坏块。参照图3,通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,读取第0块的所有数据,若第0块的所有数据全为全高(FFH),则判定第0块为空,继续测试,若第0块的所有数据不全为FFH,则判定第0块为非空,终止测试。Figure 3 is a schematic flow chart of step two in a specific embodiment of the present invention. Assume that the above two memories are both preliminarily qualified. Go to step 2 to determine whether the 0th block of each LUN in the two preliminarily qualified memories is a non-bad block. Referring to Figure 3, through the block reading module, the five-byte entry address is addressed to the 0th address of block 0, page 0, of the first LUN in the two memories, and all the data of block 0 is read. If the If all the data in block 0 are full height (FFH), it is determined that block 0 is empty and the test continues. If all the data in block 0 is not all FFH, it is determined that block 0 is not empty and the test is terminated.
其中,对于第一个LUN的第0块为空的存储器,通过块编程模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,为第0块所有写入格式为全0的数据;通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,读取第0块的所有数据,若第0块的所有数据为全0,则通过块擦除模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,擦除第0块的所有数据;然后再通过块读取模块,五个字节入口地址寻址到两个存储器中每一个存储器的第一个LUN的第0块第0页第0个地址,读取第0块的所有数据,若第0块的所有数据全为FFH,则判定第0块为空,然后采用上述方式分别写入格式为棋盘格的数据和格式为反棋盘格的数据。然后对两个存储器中每一个存储器进行下一个LUN的第0块的测试。图3只示出了两个存储器中每一个存储器的第一个LUN的测试过程,其他LUN的测试过程与第一个LUN的测试过程相同。若测试过程中任意一种格式的数据的写入和读取不一致,则判定对应存储器的第0块为坏块,该坏块所属的存储器终止测试。通过读取失效管脚的数据,定位出失效存储器是第一存储器还是第二存储器,并终止失效存储器的测试。Among them, for the memory block 0 of the first LUN that is empty, through the block programming module, the five-byte entry address is addressed to the address 0 of page 0 of block 0 of the first LUN in the two memories. All data written in the format of all 0s for block 0; through the block reading module, the five-byte entry address is addressed to the 0th address of page 0 of block 0 of the first LUN in the two memories, read Get all the data in block 0. If all the data in block 0 is all 0, then through the block erase module, the five-byte entry address is addressed to block 0 and page 0 of the first LUN in the two memories. At the 0th address, erase all the data in the 0th block; then through the block reading module, the five-byte entry address is addressed to the 0th block and page 0 of the first LUN of each of the two memories. At the 0th address, read all the data in the 0th block. If all the data in the 0th block are FFH, then determine that the 0th block is empty, and then use the above method to write the data in the checkboard format and the reverse format respectively. Checkerboard data. Then block 0 of the next LUN is tested on each of the two memories. Figure 3 only shows the test process of the first LUN of each of the two memories. The test process of other LUNs is the same as the test process of the first LUN. If the writing and reading of data in any format are inconsistent during the test, the 0th block of the corresponding memory is determined to be a bad block, and the memory to which the bad block belongs terminates the test. By reading the data of the failed pin, it is determined whether the failed memory is the first memory or the second memory, and the test of the failed memory is terminated.
本发明中的写入数据的格式包括全0、棋盘格和反棋盘格,上一种格式的数据写入读取和擦除之后再进行下一种格式的数据的写入读取和擦除,这三种写入数据的格式顺序不作限定,可以互换。其中,数据的格式为全0即写入的数据都是0。在所述上一种格式的数据写入读取和擦除之后,判断当前块内的数据是否为空,在当前块内的数据为空的情况下,进行下一种格式的数据的写入读取和擦除。对存储器测试的故障覆盖率取决于写入数据的格式,使用全0,棋盘格,反棋盘格三种格式的数据分别进行遍历,可以覆盖固0,固1,地址译码故障,短路、开路等常见的存储器故障,在测试时间允许的范围最大程度的增加了测试故障覆盖率。The formats of writing data in the present invention include all zeros, checkerboard and reverse checkerboard. After the data of the previous format is written, read and erased, the data of the next format is written, read and erased. , the order of these three writing data formats is not limited and can be interchanged. Among them, the format of the data is all 0, that is, the written data is all 0. After the data in the previous format is written, read and erased, it is determined whether the data in the current block is empty. If the data in the current block is empty, the data in the next format is written. Read and erase. The fault coverage rate of the memory test depends on the format of the written data. Data in three formats: all 0, checkerboard, and reverse checkerboard are used to traverse respectively. It can cover fixed 0s, fixed 1s, address decoding faults, short circuits, and open circuits. For common memory faults, the test fault coverage is increased to the greatest extent within the allowable range of test time.
图4是本发明具体实施例中步骤三的流程示意图。参照图4,假设上述两个存储器每一个LUN的第0块均为非坏块,进行步骤三,确定这两个存储器中每一个LUN的初始坏块数量。由于NAND FLASH存储器内含有初始坏块,出厂时厂家会在每一块的标志位即该块的第0页第0个冗余字节标注出该块是否为坏块,以方便后续使用和测试;若该块标志位的数据为FFH,则为非初始坏块,若该块标志位的数据为00H,则为初始坏块。Figure 4 is a schematic flowchart of step three in a specific embodiment of the present invention. Referring to Figure 4, assuming that the 0th block of each LUN in the above two memories is a non-bad block, proceed to step three to determine the initial number of bad blocks in each LUN in the two memories. Since NAND FLASH memory contains initial bad blocks, when leaving the factory, the manufacturer will mark whether the block is a bad block in the flag bit of each block, that is, the 0th redundant byte on page 0 of the block, to facilitate subsequent use and testing; If the data in the block flag bit is FFH, it is a non-initial bad block. If the data in the block flag bit is 00H, it is an initial bad block.
通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个冗余地址,读取第0块第0页第0个冗余字节的数据,若数据为FFH,则继续通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第1块第0页第0个冗余地址,读取第1块第0页第0个冗余字节的数据,数据为FFH,然后按照上述方法依次进行第一个LUN的第2块至第X-1块的测试,直至通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第X块第0页第0个冗余地址,读取第X块第0页第0个冗余字节的数据,若数据为00H,则通过初始坏块累加模块,判断初始坏块标注的来源,若初始坏块来自于第一存储器,则第一存储器的初始坏块数量寄存器加1,即M1++,若初始坏块来自于第二存储器,则第二存储器的初始坏块数量寄存器加1,即M2++,然后按照上述方法依次进行第一个LUN的第X+1块至第Z-1块的测试,直至通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第Z块第0页第0个冗余地址,读取第Z块第0页第0个冗余字节的数据,数据为FFH,至此,完成了两个存储器第一个LUN的所有块的测试。然后再按上述方法确定下一个LUN的初始坏块数量。图4只示出了两个存储器中每一个存储器的第一个LUN的测试过程,其他LUN的测试过程与第一个LUN的测试过程相同。通过读取失效管脚的数据,定位出失效存储器是第一存储器还是第二存储器,并终止失效存储器的测试。其中,M1代表第一存储器的初始坏块数量;M1++代表第一存储器的初始坏块数量寄存器加1;M2代表第二存储器的初始坏块数量;M2++代表第二存储器的初始坏块数量寄存器加1;第Z块代表最后一个块。Through the byte random reading module, the five-byte entry address addresses the redundant address of block 0, page 0, and page 0 of the first LUN in the two memories, and reads block 0, page 0, and 0 For redundant byte data, if the data is FFH, it continues to pass through the byte random reading module, and the five-byte entry address is addressed to the 0th redundant block of block 1 of the first LUN in the two memories. At the remaining address, read the data of the 0th redundant byte on the 0th page of the 1st block. The data is FFH. Then follow the above method to test the 2nd block to the X-1th block of the first LUN until it passes. Byte random reading module, the five-byte entry address addresses the 0th redundant address on page 0 of block X of the first LUN in the two memories, and reads the 0th redundant address of page 0 of block For the remaining bytes of data, if the data is 00H, the initial bad block accumulation module is used to determine the source of the initial bad block label. If the initial bad block comes from the first memory, then the initial bad block number register of the first memory is incremented by 1. That is, M1++. If the initial bad block comes from the second storage, then the initial bad block number register of the second storage is incremented by 1, which is M2++, and then proceed from the X+1th block to the Z-1th block of the first LUN according to the above method. The block is tested until the byte random reading module is passed. The five-byte entry address is addressed to the 0th redundant address of the 0th page of the Zth block of the first LUN in the two memories. The Zth block is read. The data of the 0th redundant byte of page 0 is FFH. At this point, the test of all blocks of the first LUN of the two memories has been completed. Then determine the initial number of bad blocks for the next LUN according to the above method. Figure 4 only shows the test process of the first LUN of each of the two memories. The test process of other LUNs is the same as the test process of the first LUN. By reading the data of the failed pin, it is determined whether the failed memory is the first memory or the second memory, and the test of the failed memory is terminated. Among them, M1 represents the initial bad block number of the first memory; M1++ represents the initial bad block number register of the first memory plus 1; M2 represents the initial bad block number of the second memory; M2++ represents the initial bad block number register of the second memory plus 1; Block Z represents the last block.
图5是本发明具体实施例中步骤四的流程示意图。参照图5,步骤四中判断每一个第0块为非坏块的存储器是否为空片包括:通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个冗余地址,读取第0块第0页第0个冗余字节的数据,若数据为FFH,则通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,读取第0块的所有数据,判断第0块的所有数据全为FFH,然后通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第1块第0页第0个冗余地址,读取第1块第0页第0个冗余字节的数据,若数据为FFH,则通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第1块第0页第0个地址,读取第1块的所有数据,判断第1块的所有数据全为FFH,然后按照上述方法依次进行第一个LUN的第2块至第X-1块的测试,直至通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第X块第0页第0个冗余地址,读取第X块第0页第0个冗余字节的数据,若数据为00H,则通过坏块处理模块,判断坏块标注的来源,若坏块来自于第一存储器,将第一存储器的片选信号CE1拉高,直至检测到X+1块时对控制信号赋值;若坏块来自于第二存储器,将第二存储器的片选信号CE2拉高,直至检测到X+1块时对控制信号赋值;然后按照上述方法依次进行第一个LUN的第X+1块至第Y-1块的测试,直至通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第Y块第0页第0个冗余地址,读取第Y块第0页第0个冗余字节的数据,若数据为FFH,则通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第Y块第0页第0个地址,读取第Y块的所有数据,判断第Y块的所有数据不全为FFH,则包含所有数据不全为FFH的第Y块的存储器为非空片,终止测试,另一个存储器继续测试;按照上述方法依次进行第一个LUN的第Y+1块至第Z-1块的测试,直至通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第Z块第0页第0个冗余地址,读取第Z块第0页第0个冗余字节的数据,若数据为FFH,则通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第Z块第0页第0个地址,读取第Z块的所有数据,判断第Z块的所有数据全为FFH,至此,完成了两个存储器第一个LUN所有块的测试。然后按上述方法测试下一个LUN的每一个块是否为空。图5只示出了两个存储器中每一个存储器的第一个LUN的测试过程,其他LUN的测试过程与第一个LUN的测试过程相同。通过读取失效管脚的数据,定位出失效存储器是第一存储器还是第二存储器,并终止失效存储器的测试。Figure 5 is a schematic flowchart of step four in a specific embodiment of the present invention. Referring to Figure 5, in step 4, determining whether each memory block 0 is a non-bad block is an empty block includes: through the byte random reading module, the five-byte entry address is addressed to the first LUN of the two memories. At the 0th redundant address of block 0, page 0, read the data of the 0th redundant byte of block 0, page 0. If the data is FFH, use the block reading module, five-byte entry address Address to the 0th address on page 0 of block 0 of the first LUN in the two memories, read all the data in block 0, determine that all the data in block 0 is FFH, and then read it randomly by byte Module, the five-byte entry address addresses the 0th redundant address on page 0 of block 1 of the first LUN in the two memories, and reads the data of the 0th redundant byte of page 0 of block 1. , if the data is FFH, then through the block reading module, the five-byte entry address is addressed to the 0th address of block 1, page 0, of the first LUN in the two memories, and all the data of the first block is read. , determine that all the data in the first block is FFH, and then conduct the test from the second block to the X-1 block of the first LUN in sequence according to the above method, until the byte random reading module is passed, and the five-byte entry address is Address to the 0th redundant address on page 0 of block The bad block processing module determines the source of the bad block label. If the bad block comes from the first memory, it pulls the chip select signal CE1 of the first memory high until the X+1 block is detected and assigns a value to the control signal; if the bad block comes from In the second memory, pull the chip select signal CE2 of the second memory high until the control signal is assigned a value when the X+1 block is detected; then follow the above method to proceed from the X+1th block to the Y-th block of the first LUN 1 block test until passing the byte random reading module, the five-byte entry address is addressed to the 0th redundant address of page 0 of block Y of the first LUN in the two memories, and reads the block Y The data of the 0th redundant byte on page 0. If the data is FFH, then through the block reading module, the five-byte entry address is addressed to the Yth block page 0 of the first LUN in the two memories. 0 address, read all the data in the Yth block, judge that all the data in the Yth block are not all FFH, then the memory in the Yth block containing all data not all FFH is not empty, terminate the test, and continue the test on the other memory ; Follow the above method to test the Y+1 to Z-1 blocks of the first LUN in sequence until the byte random reading module is passed and the five-byte entry address is addressed to the first of the two memories. At the 0th redundant address on page 0 of block Z of the LUN, read the data of the 0th redundant byte on page 0 of block Z. If the data is FFH, use the block reading module with five byte entries. The address is addressed to the 0th address on page 0 of block Z of the first LUN in the two memories, reads all the data in block Z, and determines that all the data in block Z is FFH. At this point, two tasks are completed. Test of all blocks of the first LUN of storage. Then test whether each block of the next LUN is empty according to the above method. Figure 5 only shows the test process of the first LUN of each of the two memories. The test process of other LUNs is the same as the test process of the first LUN. By reading the data of the failed pin, it is determined whether the failed memory is the first memory or the second memory, and the test of the failed memory is terminated.
图6是本发明具体实施例中步骤五的流程示意图。参照图6,假设上述两个第0块为非坏块的存储器都为空片,进行步骤五,识别出测试过程中新产生的坏块,分别确定两个存储器中每一个LUN的新产生的坏块数量并按照预定规则对新产生的坏块进行回写。通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个冗余地址,读取第0块第0页第0个冗余字节的数据,若数据为FFH,则通过块编程模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,为第0块所有写入格式为全0的数据;通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,读取第0块的所有数据,若第0块的所有数据为全0,则通过块擦除模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,擦除第0块的所有数据;然后再通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第0块第0页第0个地址,读取第0块的所有数据,若第0块的所有数据全为FFH,则判定第0块为空,接着采用上述方式分别写入格式为棋盘格的数据和格式为反棋盘格的数据;然后按照上述方法依次进行第一个LUN的第1块至第X-1块的测试,直至通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第X块第0页第0个冗余地址,读取第X块第0页第0个冗余字节的数据,若数据为00H,则通过坏块处理模块,判断坏块标注的来源,若坏块来自于第一存储器,将第一存储器的片选信号CE1拉高,直至检测到X+1块时对控制信号赋值;若坏块来自于第二存储器,将第二存储器的片选信号CE2拉高,直至检测到X+1块时对控制信号赋值;然后按照上述方法依次进行第一个LUN的第X+1块至第Y-1块的测试,直至通过字节随机读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第Y块第0页第0个冗余地址,读取第Y块第0页第0个冗余字节的数据,若数据为FFH,则通过块编程模块,五个字节入口地址寻址到两个存储器中第一个LUN的第Y块第0页第0个地址,为第Y块所有写入格式为全0的数据;通过块读取模块,五个字节入口地址寻址到两个存储器中第一个LUN的第Y块第0页第0个地址,读取第Y块的所有数据,若第Y块的所有数据不为全0,则通过新坏块数量累加模块,判断新产生的坏块标注的来源,若新产生的坏块来自于第一存储器,则第一存储器的新产生的坏块数量寄存器加1,即N1++,若新产生的坏块来自于第二存储器,则第二存储器的新产生的坏块数量寄存器加1,即N2++;然后通过块擦除模块对失效的存储器的新产生的坏块进行擦除,再通过字节随机写入模块将此块的标志位回写成00H,最后将此块的片选信号CE拉高,直至检测到Y+1块时对控制信号赋值;然后按照上述方法依次进行第一个LUN的第Y+1块至第Z块的测试,至此,完成了两个存储器第一个LUN的所有块的测试。然后按上述方法进行下一个LUN测试。图6只示出了两个存储器中每一个存储器的第一个LUN的测试过程,其他LUN的测试过程与第一个LUN的测试过程相同。Figure 6 is a schematic flowchart of step five in a specific embodiment of the present invention. Referring to Figure 6, assuming that the above two memories with block 0 as non-bad blocks are empty slices, proceed to step 5 to identify the newly generated bad blocks during the test process and determine the newly generated bad blocks of each LUN in the two memories. The number of bad blocks is determined and newly generated bad blocks are written back according to predetermined rules. Through the byte random reading module, the five-byte entry address addresses the redundant address of block 0, page 0, and page 0 of the first LUN in the two memories, and reads block 0, page 0, and 0 For redundant byte data, if the data is FFH, through the block programming module, the five-byte entry address is addressed to the 0th address of block 0, page 0, of the first LUN in the two memories, which is the 0th address. All data written in the block are in the format of all 0s; through the block reading module, the five-byte entry address is addressed to the 0th address of block 0, page 0, of the first LUN in the two memories, and reads the 0th All data in the block, if all data in block 0 is all 0, then through the block erase module, the five-byte entry address is addressed to block 0, page 0, and 0 of the first LUN in the two memories. address, erase all data in block 0; then through the block reading module, the five-byte entry address is addressed to the 0th address of block 0, page 0, of the first LUN in the two memories, and read All data in block 0, if all data in block 0 are all FFH, then block 0 is determined to be empty, and then use the above method to write data in checkerboard format and data in reverse checkerboard format respectively; then follow the above method The above method sequentially tests the first block to the X-1 block of the first LUN until the five-byte entry address is addressed to the X-th block of the first LUN in the two memories through the byte random reading module. At the 0th redundant address on page 0 of block, read the data of the 0th redundant byte on page 0 of block If the block comes from the first memory, pull the chip select signal CE1 of the first memory high until the control signal is assigned a value when the X+1 block is detected; if the bad block comes from the second memory, set the chip select signal CE2 of the second memory Pull it high until the control signal is assigned a value when the The five-byte entry address addresses the 0th redundant address on page 0 of block Y in the first LUN of the two memories, and reads the data of the 0th redundant byte on page 0 of block Y. If If the data is FFH, then through the block programming module, the five-byte entry address is addressed to the 0th address of page 0 of the Yth block of the first LUN in the two memories. All writing formats for the Yth block are all 0s. data; through the block reading module, the five-byte entry address is addressed to the 0th address of page 0 of the Yth block of the first LUN in the two memories, and reads all the data of the Yth block. If the Yth If all the data of the block are not all 0, then the new bad block number accumulation module is used to determine the source of the newly generated bad block label. If the newly generated bad block comes from the first memory, then the newly generated bad block of the first memory The number register adds 1, that is, N1++. If the newly generated bad block comes from the second memory, the newly generated bad block quantity register of the second memory adds 1, that is, N2++; then the new bad block of the failed memory is updated through the block erase module. The generated bad block is erased, and then the flag bit of this block is written back to 00H through the byte random writing module. Finally, the chip select signal CE of this block is pulled high until the control signal is assigned a value when the Y+1 block is detected. ; Then follow the above method to sequentially test the Y+1 to Z blocks of the first LUN. At this point, the test of all blocks of the first LUN of the two memories has been completed. Then perform the next LUN test as described above. Figure 6 only shows the test process of the first LUN of each of the two memories. The test process of other LUNs is the same as the test process of the first LUN.
步骤六中基于为空片的存储器中每一个LUN的初始坏块数量和新产生的坏块数量判断对应存储器是否合格包括:若为空片的存储器中每一个LUN的M1+N1的和均不超过预定数量,则判定第一存储器合格;若为空片的存储器中任意一个LUN的初始坏块的数量M1与新产生的坏块的数量N1之和超过预定数量,则判定第一存储器不合格。若为空片的存储器中每一个LUN的M2+N2的和均不超过预定数量,则判定第二存储器合格;若为空片的存储器中任意一个LUN的初始坏块的数量M2与新产生的坏块的数量N2之和超过预定数量,则判定第二存储器不合格。In step 6, judging whether the corresponding memory is qualified based on the initial number of bad blocks and the number of newly generated bad blocks of each LUN in the empty memory includes: If the sum of M1+N1 of each LUN in the empty memory is not If the sum of the number of initial bad blocks M1 and the number of newly generated bad blocks N1 of any LUN in the empty memory exceeds the predetermined number, the first memory is judged to be unqualified. . If the sum of M2+N2 of each LUN in the empty memory does not exceed the predetermined number, the second memory is determined to be qualified; if the initial bad block number M2 of any LUN in the empty memory is different from the newly generated If the sum of the number N2 of bad blocks exceeds the predetermined number, the second memory is determined to be unqualified.
虽然上述实施例中描述了对两个存储器进行并行测试回写,但其仅仅是示例性的,并非用于限定本发明。具体地,上述方法同样适用于三个或者三个以上的存储器并行测试及坏块回写。Although the above embodiment describes performing parallel test writeback on two memories, this is only exemplary and is not intended to limit the present invention. Specifically, the above method is also applicable to three or more memories in parallel testing and bad block writeback.
从上述实施例可以看出,本发明上述的NAND FLASH存储器并行测试及坏块回写方法能够实现多个NAND FLASH存储器的并行测试,能够有效识别出测试过程中新产生的坏块并进行回写,提升了测试效率,同时对预设的原有标志位进行了保护。It can be seen from the above embodiments that the above-mentioned NAND FLASH memory parallel testing and bad block write-back method of the present invention can realize parallel testing of multiple NAND FLASH memories, and can effectively identify newly generated bad blocks during the test process and perform write-back , which improves test efficiency and protects the preset original flag bits.
此外,需要说明的是,使用“第一”、“第二”等词语来限定零部件,仅仅是为了便于对相应零部件进行区别,如没有另行声明,上述词语并没有特殊含义,因此不能理解为对本发明保护范围的限制。In addition, it should be noted that the use of words such as "first" and "second" to define parts is only to facilitate the distinction between corresponding parts. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood. To limit the scope of protection of the present invention.
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本领域的技术人员在本发明所揭露的技术范围内,可不经过创造性劳动想到的变化或替换,都应涵盖在本发明的保护范围内。因此,本发明的保护范围应该以权利要求书所限定的保护范围为准。The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the art may think of changes or modifications within the technical scope disclosed in the present invention without creative efforts. All substitutions shall be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope defined by the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910873960.1ACN112530508B (en) | 2019-09-17 | 2019-09-17 | NAND FLASH memory parallel test and bad block write-back method |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910873960.1ACN112530508B (en) | 2019-09-17 | 2019-09-17 | NAND FLASH memory parallel test and bad block write-back method |
| Publication Number | Publication Date |
|---|---|
| CN112530508A CN112530508A (en) | 2021-03-19 |
| CN112530508Btrue CN112530508B (en) | 2023-10-20 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910873960.1AActiveCN112530508B (en) | 2019-09-17 | 2019-09-17 | NAND FLASH memory parallel test and bad block write-back method |
| Country | Link |
|---|---|
| CN (1) | CN112530508B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299335B (en)* | 2021-05-24 | 2023-01-31 | 长江存储科技有限责任公司 | A test method, test system and test equipment for a storage device |
| CN113176970B (en)* | 2021-06-28 | 2021-10-22 | 中国核动力研究设计院 | System and method for managing bad blocks of nor flash based on FPGA |
| CN114220472B (en)* | 2021-12-15 | 2025-06-27 | 华进半导体封装先导技术研发中心有限公司 | A Nand Flash test method based on SOC universal test platform |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6477672B1 (en)* | 1998-09-21 | 2002-11-05 | Advantest Corporation | Memory testing apparatus |
| CN101727989A (en)* | 2008-10-16 | 2010-06-09 | 付建云 | NAND FLASH memory chip test system |
| CN106158047A (en)* | 2016-07-06 | 2016-11-23 | 深圳佰维存储科技股份有限公司 | A kind of NAND FLASH method of testing |
| CN106920576A (en)* | 2017-03-22 | 2017-07-04 | 惠州佰维存储科技有限公司 | A kind of method and system of inspection Nand Flash mass |
| CN106971757A (en)* | 2017-03-22 | 2017-07-21 | 惠州佰维存储科技有限公司 | A kind of method and system of inspection Nand Flash mass |
| CN107357696A (en)* | 2017-06-22 | 2017-11-17 | 上海斐讯数据通信技术有限公司 | A kind of bad block method of testing of nonvolatile storage and system |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8560922B2 (en)* | 2011-03-04 | 2013-10-15 | International Business Machines Corporation | Bad block management for flash memory |
| US10146604B2 (en)* | 2016-08-23 | 2018-12-04 | Oracle International Corporation | Bad block detection and predictive analytics in NAND flash storage devices |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6477672B1 (en)* | 1998-09-21 | 2002-11-05 | Advantest Corporation | Memory testing apparatus |
| CN101727989A (en)* | 2008-10-16 | 2010-06-09 | 付建云 | NAND FLASH memory chip test system |
| CN106158047A (en)* | 2016-07-06 | 2016-11-23 | 深圳佰维存储科技股份有限公司 | A kind of NAND FLASH method of testing |
| CN106920576A (en)* | 2017-03-22 | 2017-07-04 | 惠州佰维存储科技有限公司 | A kind of method and system of inspection Nand Flash mass |
| CN106971757A (en)* | 2017-03-22 | 2017-07-21 | 惠州佰维存储科技有限公司 | A kind of method and system of inspection Nand Flash mass |
| CN107357696A (en)* | 2017-06-22 | 2017-11-17 | 上海斐讯数据通信技术有限公司 | A kind of bad block method of testing of nonvolatile storage and system |
| Title |
|---|
| NAND FLASH测试设计及使用探讨;杨超;《电子世界》;全文* |
| RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory;Ruixiang Ma;《IEEE Access 》;全文* |
| Publication number | Publication date |
|---|---|
| CN112530508A (en) | 2021-03-19 |
| Publication | Publication Date | Title |
|---|---|---|
| CN112530508B (en) | NAND FLASH memory parallel test and bad block write-back method | |
| US7350119B1 (en) | Compressed encoding for repair | |
| JP5100663B2 (en) | Test apparatus and test method | |
| TWI425523B (en) | Hybrid flash memory storage device and method of controlling the same | |
| US20070170268A1 (en) | Memory cards, nonvolatile memories and methods for copy-back operations thereof | |
| CN105518799B (en) | Semiconductor storage | |
| TWI443512B (en) | Block management method, memory controller and memory stoarge apparatus | |
| US7697347B2 (en) | Non-volatile memory device and method of driving the same | |
| TWI545572B (en) | Memory cell programming method, memory control circuit unit and memory storage apparatus | |
| US8667348B2 (en) | Data writing method for non-volatile memory module and memory controller and memory storage apparatus using the same | |
| TW201539455A (en) | Data storing method, memory control circuit unit and memory storage apparatus | |
| CN106484316A (en) | Method for managing a memory device, memory device and controller | |
| CN109215713A (en) | The method of storage system and operation semiconductor memory system | |
| JP2012517068A (en) | Memory device, memory management device, and memory management method | |
| TW201324145A (en) | Data merging method for non-volatile memory and controller and storage apparatus using the same | |
| CN102592670B (en) | Data writing method, memory controller and memory storage device | |
| TW201724110A (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN102902626B (en) | Block management method, memory controller and memory storage device | |
| CN102866861B (en) | Flash memory storage system, flash memory controller and data writing method | |
| CN105843700B (en) | Controller | |
| TWI509615B (en) | Data storing method, and memory controller and memory storage apparatus using the same | |
| TWI616807B (en) | Data writing method and storage controller | |
| US7394688B2 (en) | Nonvolatile memory | |
| CN107783723A (en) | A kind of memory block treating method and apparatus | |
| TWI571881B (en) | Valid data merging method, memory controller and memory storage apparatus |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |