CN112511480A - Secondary FFT and IFFT transformation method and related product - Google Patents

Abstract

The embodiment of the application provides a secondary FFT and IFFT transformation method and a related product, wherein the method comprises the following steps: acquiring data subjected to secondary FFT and IFFT transformation, and determining the order stage of the first transformation of the data; determining corresponding address mapping according to the stage and the decomposed factor number; determining a stage access address according to the address mapping, performing first conversion on data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing second conversion operation with the same address on the output operation result to obtain a second FFT and IFFT conversion result. The technical scheme provided by the application has the advantage of low time delay.

Description

Secondary FFT and IFFT transformation method and related product

Technical Field

The present application relates to the field of communications processing technologies, and in particular, to a second FFT and IFFT transformation method and a related product.

Background

FFT (fast fourier transform) and IFFT (inverse fast fourier transform) need to be performed in many signal processing scenarios. In a signal processing scene, secondary FFT and IFFT transformation are needed, the requirement on time delay is extremely high, the time delay of the existing secondary FFT and IFFT transformation is high, and the resource consumption is large.

Disclosure of Invention

The embodiment of the application discloses a secondary FFT and IFFT transformation method and a related product, which can reduce the time delay of the secondary FFT and IFFT transformation, effectively reduce the resource consumption and improve the user experience.

In a first aspect, a method for OFDM transform in a 5G system is provided, the method comprising the steps of:

acquiring data subjected to secondary FFT and IFFT transformation, and determining the order stage of the first transformation of the data; determining corresponding address mapping according to the stage and the decomposed factor number;

determining a stage access address according to the address mapping, performing first conversion on data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing second conversion operation on the same address of the output operation result to obtain a second FFT and IFFT conversion result;

if the first transformation is: fast Fourier Transform (FFT), second FFT;

if the first transformation is: IFFT, second transform to FFT.

In a second aspect, a user equipment is provided, the user equipment comprising:

the acquisition unit is used for acquiring data of secondary FFT and IFFT;

a processing unit for determining an order stage of a first transformation of the data; determining corresponding address mapping according to the stage and the decomposed factor number; determining a stage access address according to the address mapping, performing first conversion on data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing second conversion with the same address on the output operation result to obtain a secondary FFT and IFFT conversion result;

if the first transformation is: fast Fourier Transform (FFT), second FFT;

if the first transformation is: IFFT, second transform to FFT.

In a third aspect, there is provided an electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps of the method of the first aspect.

In a fourth aspect, a computer-readable storage medium is provided, storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform the method of the first aspect.

In a fifth aspect, there is provided a computer program product, wherein the computer program product comprises a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps as described in the first aspect of an embodiment of the present application. The computer program product may be a software installation package.

In a sixth aspect, a chip system is provided, the chip system comprising at least one processor, a memory and an interface circuit, the memory, the transceiver and the at least one processor being interconnected by wires, the at least one memory having a computer program stored therein; the computer program, when executed by the processor, implements the method of the first aspect.

The technical scheme provided by the application obtains data of sub-FFT and IFFT, if the data is smaller than a preset transformation size, zero padding processing is carried out on the data to obtain processed data, and the order stage of Fast Fourier Transform (FFT) of the processed data is determined; determining corresponding address mapping according to the stage and the number of the decomposed factors; determining a stage access address according to the address mapping, performing operation on data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing the IFFT operation with the same address on the output operation result to obtain a secondary FFT and IFFT conversion result. The scheme of this application adopts the structure of same address to carry out reading and writing in of data, the effectual time delay that has reduced, and in actual test, it only can delay several clock beat, therefore it has the effect that reduces the time delay, in addition, according to the above-mentioned improvement address utilization that the number can be very big of mapping, improves the operating speed, reduces the operation resource, improves user experience degree.

Drawings

The drawings used in the embodiments of the present application are described below.

FIG. 1 is a system architecture diagram of an exemplary communication system;

fig. 2 is a schematic flow chart of a second FFT and IFFT transformation method provided in the present application;

FIG. 3 is a diagram of a hardware architecture of an FFT processor;

FIG. 4 is a schematic diagram of a method of quadratic transformation;

fig. 5 is a schematic structural diagram of a user equipment according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The embodiments of the present application will be described below with reference to the drawings.

The term "and/or" in this application is only one kind of association relationship describing the associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document indicates that the former and latter related objects are in an "or" relationship.

The "plurality" appearing in the embodiments of the present application means two or more. The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application. The term "connect" in the embodiments of the present application refers to various connection manners, such as direct connection or indirect connection, to implement communication between devices, which is not limited in this embodiment of the present application.

The technical solution of the embodiment of the present application may be applied to theexample communication system 100 shown in fig. 1, where theexample communication system 100 includes aterminal 110 and anetwork device 120, and theterminal 110 is communicatively connected to thenetwork device 120.

In baseband signal processing, it is often necessary to transform a signal in a time domain to a frequency domain, and then transform the signal to the time domain after the frequency domain processing is completed.

The FFT processor calculates the stages (orders) related to the decomposition factors thereof, the number of the decomposed factors determines the operation orders thereof, and the FFT _ size is the number of points to be transformed, fftidx _ max and fftgroup _ max which are the maximum value of the fixed count decomposed under a certain point number and each operation stage (operation order), and the value of the maximum value meets the requirement that the FFT _ size is fftidx _ max and fftgroup _ max 8.

Wherein, FFT _ size represents the size of FFT, fftidx _ max represents the index maximum value of FFT, ffgroup _ max represents the maximum value of FFT group.

Referring to fig. 2, fig. 2 provides a second FFT and IFFT transformation method, which is implemented in the communication system shown in fig. 1, and specifically, the method may be executed by a terminal in the communication system shown in fig. 1, but may also be executed by a network device in the communication system shown in fig. 1 in an alternative scheme, where the method includes the following steps:

step S201, acquiring data of secondary FFT and IFFT transformation;

one-time FFT (IFFT) operation flow:

the data is firstly input into 8 pieces of RAM, linear addresses are mapped to RAM BANK numbers and BANK addresses, after the data is input, operation is carried out under external operation enabling and configuration parameters (FFT _ size, IFFT or FFT operation identification), the linear addresses of the data required by the operation are converted into the RAM BANK numbers and the BANK addresses under the mapping by the above, 8 numbers are taken for carrying out 8-base operation, the operation result is multiplied by the rotation factor under the non-last stage, and the operation intermediate result is written back to the memory. When the operation is carried out to the last stage, the operation is carried out on the basis 2, the basis 4 or the basis 8 (according to the specific decomposition condition of each point), no twiddle factor function is existed when the operation is carried out to the last stage, and the result is written back to the cache. The RAM adopts a dual-port memory for simultaneous data input and output. The ROM table is used to store the 7-way spin factors required for the base 8 operation.

The secondary FFT conversion implementation process:

after the data is input, the first fft (ifft) operation is performed as described above;

reading data in a transform domain, processing and writing back the data in the same address, wherein the reading support first address is integral multiple of 8 and is continuous with 8 numbers, and the access address is subjected to address mapping once according to a formula 3;

performing an IFFT (FFT) operation on the written data at the same address;

reading the final result in 8 RAM, wherein the read support first address is integral multiple of 8, continuous 8 numbers, and the access address carries out continuous secondary address mapping, which is as follows: and y is f (x)), and mapping is carried out on y, and the linear address is mapped to the RAM BANK number and the BANK address, so as to obtain the final physical RAM number and address mapping.

Step S202, determining the order stage of the first transformation of the data; determining corresponding address mapping according to the stage and the decomposed factor number;

step S203, determining the stage access address according to the address mapping, performing a first transformation on the data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing a second transformation with the same address on the output operation result to obtain a second FFT and IFFT transformation result.

If the first transformation is: fast Fourier Transform (FFT), second FFT;

if the first transformation is: IFFT, second transform to FFT.

The technical scheme provided by the application obtains data of sub-FFT and IFFT, if the data is smaller than a preset transformation size, zero padding processing is carried out on the data to obtain processed data, and the order stage of Fast Fourier Transform (FFT) of the processed data is determined; determining corresponding address mapping according to the stage and the number of the decomposed factors; determining a stage access address according to the address mapping, performing operation on data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing the IFFT operation with the same address on the output operation result to obtain a secondary FFT and IFFT conversion result. The scheme of this application adopts the structure of same address to carry out reading and writing in of data, the effectual time delay that has reduced, and in actual test, it only can delay several clock beat, therefore it has the effect that reduces the time delay, in addition, according to the above-mentioned improvement address utilization that the number can be very big of mapping, improves the operating speed, reduces the operation resource, improves user experience degree.

In an optional scheme, the determining a corresponding address mapping according to the stage and the number of factors of the processed data decomposition; determining the stage access address according to the address mapping specifically comprises:

determining a fast Fourier transform group value fftgroup _ num, a fast Fourier transform index value fftedx _ num and a log2_ num according to the stage and the decomposed factor number;

if the stage is not the last stage, determining the stage access address according to fftgroup _ num, fftidx _ max and log2_ num.

fftgroup _ num may be specifically an fft group number, and fftidx _ num may be specifically an fft index number. The points are valued at each stage as follows:

2048 points:

1024 points:

512 points:

256 points:

128 points:

64 points are as follows:

32 points:

16 points are as follows:

the above points are decomposed as follows:

decomposition of 16 points

n＝2n₁+n₀ n₁＝0,1,...,7,n₀＝0,1,

k＝k₁+8k₀ k₁＝0,1,...,7,k₀＝0,1,

Decomposition of 32 points

n＝4n₁+n₀ n₁＝0,1,...,7,n₀＝0,1,2，3，

k＝k₁+8k₀ n₁＝0,1,...,7,k₀＝0,1,2,3

Decomposition of 64 points

n＝8n₁+n₀ n₁＝0,1,...,7,n₀＝0,1,...,7,

k＝k₁+8k₀ k₁＝0,1,...,7,k₀＝0,1,...,7,

Decomposition of 128 points

n＝16n₂+2n₁+n₀ n₂,n₁＝0,1,...,7,n₀＝0,1,

k＝k₂+8k₁+64k₀ k₂,k₁＝0,1,...,7,k₀＝0,1,

Decomposition of 256 points

n＝32n₂+4n₁+n₀ n₂,n₁＝0,1,...,7,n₀＝0,1,...,3,

k＝k₂+8k₁+64k₀ k₂,k₁＝0,1,...,7,k₀＝0,1,...,3,

Decomposition of 512 points

n＝64n₂+8n₁+n₀ n₂,n₁,n₀＝0,1,...,7,

k＝k₂+8k₁+64k₀ k₂,k₁,k₀＝0,1,...,7,

Decomposition of 1024 points

n＝128n₃+16n₂+2n₁+n₀ n₃,n₂,n₁＝0,1,...,7,n₀＝0,1,

k＝k₃+8k₂+64k₁+512k₀ k₃,k₂,k₁＝0,1,...,7,k₀＝0,1,

Decomposition of 2048 points

n＝256n₃+32n₂+4n₁+n₀ n₃,n₂,n₁＝0,1,...,7,n₀＝0,1,...,3,

k＝k₃+8k₂+64k₁+512k₀ k₃,k₂,k₁＝0,1,...,7,k₀＝0,1,...,3,

In an optional scheme, the determining the stage access address according to fftgroup _ max, fftidx _ num, and log2_ num specifically includes:

fft_addr0＝fftidx_num+fftgroup_base；

fft_addrx＝fft_addr(x-1)+fftidx_max*x；

wherein, the value of x is an integer of [ 1,7 ];

fftgroup_base＝fftgroup_num<<log2_num；

the fft _ addr0 indicates the first address to take the value of fft, addr indicates the address, and 0 indicates that the address number to take the value is 0 (initial value). fft _ addrx represents the number of addresses and can take any integer between [ 1,7 ].

The non-last stage address is generated as follows:

fftgroup_base＝fftgroup_num<<log2_num

fft_addr0＝fftidx_num+fftgroup_base；

fft_addr1＝fft_addr0+fftidx_max；

fft_addr2＝fft_addr1+fftidx_max*2；

fft_addr3＝fft_addr2+fftidx_max*3；

fft_addr4＝fft_addr3+fftidx_max*4；

fft_addr5＝fft_addr4+fftidx_max*5；

fft_addr6＝fft_addr5+fftidx_max*6；

fft_addr7＝fft_addr6+fftidx_max*7；

twiddle factor address: twf _ rom _ addr is fftidx _ num.

Where < < denotes a left shift.

The counters fftidx _ num and fftgroup _ num are cleared at the beginning of each stage,

at each stage, a counter fftidx _ num is counted in each clock cycle, and when fftidx _ max-1 is counted, the fftgroup _ num counter is incremented by 1, and when fftidx _ num and fftgroup _ num are counted to fftidx _ max-1 respectively.

In an optional scheme, the corresponding address mapping is determined according to the stage and the number of decomposed factors; determining the stage access address according to the address mapping specifically comprises:

determining fftgroup _ num according to the stage and the decomposed factor number, and if the stage is the last stage, determining fft _ addr0 according to the specific bit of the fftgroup _ num and the decomposed factor number; and determining the subsequent fft _ addr according to the fft _ addr0, wherein the value of x is an integer of [ 1,7 ].

In an optional scheme, the fft _ addr0 is determined according to the specific bit of the fftgroup _ num and the number of decomposed factors; determining the subsequent fft _ addr according to fft _ addr0 specifically includes:

if the number of factors decomposed is: 64. at least one of the first and second optical fibers 512,

fft_addrx＝fft_addr0+x。

in an alternative scheme, if the number of factors to be decomposed is 64, fft _ addr0 is fftgroup _ num [2:0] < < 3; wherein fftgroup _ num [2:0] represents the value of 3 bits selected from 0, 1 and 2 of fftgroup _ num; < represents a left shift, and 3 represents the number of shifted bits, that is, the value of 3 bits of fftgroup _ num, 0, 1, and 2, is shifted left by 3 bits.

If the number of factors to be decomposed is 512, fft _ addr0 is fftgroup _ num [5:0] < < 3; wherein fftgroup _ num [5:0] represents 5 bits of fftgroup _ num 1, 2, 3, 4, 5, < < represents left shift.

The method for realizing FFT secondary process at high speed same address, address mapping of first conversion operation, access address mapping of conversion domain, address mapping of second conversion operation and data access address mapping after second conversion (8 access addresses can be taken each time to realize high speed operation processing under (8/4/2 butterfly) same address, and the addresses have no conflict in 8 RAM), thus realizing that

Referring to fig. 3, fig. 3 is a schematic diagram of a hardware structure of a processor for FFT and IFFT in the quadratic transform in the present application, as shown in fig. 4, and fig. 4 is a schematic diagram of a method of quadratic transform in the present application.

It will be appreciated that the user equipment, in order to carry out the above-described functions, comprises corresponding hardware and/or software modules for performing the respective functions. The present application is capable of being implemented in hardware or a combination of hardware and computer software in conjunction with the exemplary algorithm steps described in connection with the embodiments disclosed herein. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, with the embodiment described in connection with the particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In this embodiment, the electronic device may be divided into functional modules according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module may be implemented in the form of hardware. It should be noted that the division of the modules in this embodiment is schematic, and is only a logical function division, and in actual implementation, there may be another division manner.

In the case of dividing the functional modules according to the respective functions, fig. 5 shows a schematic diagram of a user equipment, and as shown in fig. 5, the UE500 may include: an acquisition unit 501 and a processing unit 502.

Among other things, the processing unit 502 may be used to support the user equipment in performing the above-described steps S202, S203, etc., and/or other processes for the techniques described herein.

The acquisition unit 501 may be used to support the user equipment to perform the above-described steps S201, etc., and/or other processes for the techniques described herein.

It should be noted that all relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

The network device provided by the embodiment is configured to execute step S201 in the method shown in fig. 2, so that the same effect as that of the implementation method can be achieved.

In case of an integrated unit, the user equipment may comprise a processing module, a storage module and a communication module. The processing module may be configured to control and manage actions of the user equipment, and for example, may be configured to support the electronic equipment to perform the steps performed by the obtaining unit 501 and the processing unit 502. The memory module may be used to support the electronic device in executing stored program codes and data, etc. The communication module can be used for supporting the communication between the electronic equipment and other equipment.

The processing module may be a processor or a controller. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein. A processor may also be a combination of computing functions, e.g., a combination of one or more microprocessors, Digital Signal Processing (DSP) and a microprocessor, or the like. The storage module may be a memory. The communication module may specifically be a radio frequency circuit, a bluetooth chip, a Wi-Fi chip, or other devices that interact with other electronic devices.

It should be understood that the interface connection relationship between the modules illustrated in the embodiment of the present application is only an exemplary illustration, and does not form a structural limitation on the user equipment. In other embodiments of the present application, the user equipment may also adopt different interface connection manners or a combination of multiple interface connection manners in the above embodiments.

Referring to fig. 6, fig. 6 is an electronic device 60 provided in an embodiment of the present application, where the electronic device 60 includes aprocessor 601, amemory 602, and acommunication interface 603, and theprocessor 601, thememory 602, and thecommunication interface 603 are connected to each other through a bus.

Thememory 602 includes, but is not limited to, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a portable read-only memory (CD-ROM), and thememory 602 is used for related computer programs and data. Thecommunication interface 603 is used for receiving and transmitting data.

Theprocessor 601 may be one or more Central Processing Units (CPUs), and in the case that theprocessor 601 is one CPU, the CPU may be a single-core CPU or a multi-core CPU.

Processor 601 may include one or more processing units, such as: the processing unit may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), etc. Wherein the different processing units may be separate components or may be integrated in one or more processors. In some embodiments, the user equipment may also include one or more processing units. The controller can generate an operation control signal according to the instruction operation code and the time sequence signal to complete the control of instruction fetching and instruction execution. In other embodiments, a memory may also be provided in the processing unit for storing instructions and data. Illustratively, the memory in the processing unit may be a cache memory. The memory may hold instructions or data that have just been used or recycled by the processing unit. If the processing unit needs to reuse the instruction or data, it can be called directly from the memory. This avoids repeated accesses and reduces the latency of the processing unit, thereby improving the efficiency with which the user equipment processes data or executes instructions.

In some embodiments,processor 601 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit audio (I2S) interface, a Pulse Code Modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a Mobile Industry Processor Interface (MIPI), a general-purpose input/output (GPIO) interface, a SIM card interface, a USB interface, and/or the like. The USB interface is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface can be used for connecting a charger to charge the user equipment, and can also be used for transmitting data between the user equipment and peripheral equipment. The USB interface can also be used for connecting an earphone and playing audio through the earphone.

If the electronic device 60 is a terminal side device, such as a user device, theprocessor 601 in the electronic device 60 is configured to read the computer program code stored in thememory 602, and perform the following operations:

acquiring data of sub-FFT and IFFT, if the data is smaller than a preset transformation size, performing zero padding processing on the data to obtain processed data, and determining the order stage of the Fast Fourier Transform (FFT) of the processed data; determining corresponding address mapping according to the stage and the decomposed factor number;

determining a stage access address according to the address mapping, performing operation on data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing the IFFT operation with the same address on the output operation result to obtain a secondary FFT and IFFT conversion result.

All relevant contents of each scene related to the method embodiment may be referred to the function description of the corresponding function module, and are not described herein again.

If the electronic device 60 is a network device, such as a base station.

The embodiment of the present application further provides a chip system, where the chip system includes at least one processor, a memory and an interface circuit, where the memory, the transceiver and the at least one processor are interconnected by a line, and the at least one memory stores a computer program; the method flow shown in fig. 2 is implemented when the computer program is executed by the processor.

An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed on a network device, the method flow shown in fig. 2 is implemented.

An embodiment of the present application further provides a computer program product, and when the computer program product runs on a terminal, the method flow shown in fig. 2 is implemented.

Embodiments of the present application also provide a terminal including a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs including instructions for performing the steps in the method of the embodiment shown in fig. 2.

The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It will be appreciated that the electronic device, in order to carry out the functions described above, may comprise corresponding hardware structures and/or software templates for performing the respective functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software means for performing the steps of the various illustrated elements and algorithms described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the electronic device may be divided into the functional units according to the method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware or a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are presently preferred and that no acts or templates referred to are necessarily required by the application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of units is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a memory and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

Claims (10)

1. A method of quadratic FFT and IFFT transformation, the method comprising the steps of:

acquiring data subjected to secondary FFT and IFFT transformation, and determining the order stage of the first transformation of the data; determining corresponding address mapping according to the stage and the decomposed factor number;

determining a stage access address according to the address mapping, performing first conversion on data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing second conversion operation with the same address on the output operation result to obtain a second FFT and IFFT conversion result;

if the first transformation is: fast Fourier Transform (FFT), second FFT;

if the first transformation is: IFFT, second transform to FFT.

2. The method of claim 1 wherein the corresponding address mapping is determined according to the stage and the number of factors decomposed; determining the stage access address according to the address mapping specifically comprises:

determining a fast Fourier transform group value fftgroup _ num, a fast Fourier transform index value fftedx _ num and a log2_ num according to the stage and the decomposed factor number;

if the stage is not the last stage, determining the stage access address according to fftgroup _ num, fftidx _ max and log2_ num.

3. The method of claim 1, wherein determining the stage access address according to fftgroup _ max, fftidx _ num, fftidx _ max, and log2_ num specifically comprises:

fft_addr0＝fftidx_num+fftgroup_base；

fft_addrx＝fft_addr(x-1)+fftidx_max*x；

wherein, the value of x is an integer of [ 1,7 ];

fftgroup_base＝fftgroup_num<<log2_num。

4. the method of claim 1, wherein determining the corresponding address mapping according to the stage and the number of factors of decomposition; determining the stage access address according to the address mapping specifically comprises:

determining fftgroup _ num according to the stage and the decomposed factor number, and if the stage is the last stage, determining fft _ addr0 according to the specific bit of the fftgroup _ num and the decomposed factor number; and determining the subsequent fft _ addr according to the fft _ addr0, wherein the value of x is an integer of [ 1,7 ].

5. The method of claim 4, wherein the fft _ addr0 is determined according to the specific bits of the fftgroup _ num and the decomposed factor number; determining the subsequent fft _ addr according to fft _ addr0 specifically includes:

if the number of factors decomposed is: 64. at least one of the first and second optical fibers 512,

fft_addrx＝fft_addr0+x。

6. a User Equipment (UE), the UE comprising:

the acquisition unit is used for acquiring data of secondary FFT and IFFT;

a processing unit for determining an order stage of a first transformation of the data; determining corresponding address mapping according to the stage and the decomposed factor number; determining a stage access address according to the address mapping, performing first conversion on data of the access address to obtain an output operation result, writing the output operation result into the access address, and performing second conversion with the same address on the output operation result to obtain a secondary FFT and IFFT conversion result;

if the first transformation is: fast Fourier Transform (FFT), second FFT;

if the first transformation is: IFFT, second transform to FFT.

7. The user equipment of claim 6,

the processing unit is specifically configured to determine a fft group value fftgroup _ num, a fft index value fftidx _ max, and a log2_ num according to the stage and the decomposed factor number; if the stage is not the last stage, determining the stage access address according to fftgroup _ num, fftidx _ max and log2_ num.

8. An electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs including instructions for performing the steps of the method of any of claims 1-5.

9. A chip system, the chip system comprising at least one processor, a memory and an interface circuit, the memory, the transceiver and the at least one processor being interconnected by a line, the at least one memory having a computer program stored therein; the computer program, when executed by the processor, implements the method of any one of claims 1-5.

10. A computer-readable storage medium, in which a computer program is stored which, when run on a user equipment, performs the method of any one of claims 1-5.

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