CN112509932A - System-level packaging method and electronic equipment - Google Patents
System-level packaging method and electronic equipmentDownload PDFInfo
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- CN112509932A CN112509932ACN202011482023.2ACN202011482023ACN112509932ACN 112509932 ACN112509932 ACN 112509932ACN 202011482023 ACN202011482023 ACN 202011482023ACN 112509932 ACN112509932 ACN 112509932A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Translated fromChinese
Description
Technical Field
The present invention relates to the field of packaging technologies, and in particular, to a system-level packaging method and an electronic device.
Background
With the continuous development of integrated circuit technology, electronic products are increasingly developing toward miniaturization, intellectualization, high performance and high reliability. The integrated circuit package not only directly affects the performance of the integrated circuit, the electronic module and even the complete machine, but also restricts the miniaturization, low cost and reliability of the whole electronic system.
In substrate type packaging, for example, SIP (System In a Package System In Package) has the characteristics of high flexibility, high integration level, relatively low cost, small area, high frequency, high speed and short production period, and the SIP packaging technology can be widely applied to the fields of industrial application and internet of things, and also has a very wide market In the fields of mobile phones, smart watches, smart bracelets, smart glasses and the like. By applying the SIP system miniaturization design, the system design can be simplified and the equipment miniaturization can be met in a multi-element integration mode. The advantages of portability, wireless performance and instantaneity of the product can be increased without changing the appearance. But the existing SIP structure occupies a large area.
Disclosure of Invention
In view of this, the present invention provides a system in package method and an electronic device, which effectively solve the problem of large occupied area of the system in package structure in the prior art, and optimize the size of the system in package structure.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a system-in-package method, comprising:
providing a substrate base plate;
mounting a plurality of first passive devices and at least one chip on one side of the substrate, wherein the first passive devices comprise external terminals on one side deviating from the substrate;
forming a molding layer covering the first passive device and the at least one chip;
forming a hollow-out at a position of the plastic packaging layer corresponding to at least one first passive device;
and stacking a second passive device at the hollow-out part, wherein the second passive device is connected with the first passive device through the external terminal.
Optionally, before forming a molding layer covering the first passive device and the chip, the method further includes:
arranging a shielding protective film on one side of at least one first passive device, which is far away from the substrate base plate;
and removing the shielding protective film to remove the part of the plastic packaging layer corresponding to at least one first passive device to form the hollow part.
Optionally, the material of the shielding protection film includes at least one of ETFE and PET.
Optionally, forming a hollow at a position of the plastic package layer corresponding to at least one of the first passive devices includes:
and forming a hollow part at the position of the plastic packaging layer corresponding to at least one first passive device by adopting an etching process.
Optionally, mounting a plurality of first passive devices and at least one chip on one side of the substrate base plate, includes:
mounting a plurality of first passive devices on one side of the substrate base plate, wherein the first passive devices comprise external terminals on one side deviating from the substrate base plate;
mounting a chip on one side of the substrate base plate, which is provided with the first passive device;
and connecting the chip with the substrate base plate through a bonding wire.
Optionally, one or more of the chips includes a first sub-chip to an nth sub-chip, where N is an integer equal to or greater than 2; wherein a chip is mounted on one side of the substrate base plate, comprising:
sequentially stacking and mounting the first sub-chip to the Nth sub-chip on one side of the substrate base plate;
and respectively connecting the first sub-chip to the Nth sub-chip with the substrate base plate through bonding wires.
Optionally, the plurality of first passive devices are disposed around the at least one chip.
Optionally, the substrate base plate is a circuit board.
Correspondingly, the invention also provides electronic equipment which comprises the system-in-package structure prepared by the system-in-package method.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a system-level packaging method and electronic equipment, which comprise the following steps: providing a substrate base plate; mounting a plurality of first passive devices and at least one chip on one side of the substrate, wherein the first passive devices comprise external terminals on one side deviating from the substrate; forming a molding layer covering the first passive device and the at least one chip; forming a hollow-out at a position of the plastic packaging layer corresponding to at least one first passive device; and stacking a second passive device at the hollow-out part, wherein the second passive device is connected with the first passive device through the external terminal.
According to the technical scheme provided by the invention, the first passive device and the second passive device are stacked to realize packaging, so that the problem that the first passive device and the second passive device occupy a large area due to being spread and mounted on the substrate is avoided, the problem that the system-in-package structure occupies a large area in the prior art is further effectively solved, and the size of the system-in-package structure is optimized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a system-level packaging method according to an embodiment of the present invention;
FIGS. 2-6 are schematic views of the respective steps in FIG. 1;
FIG. 7 is a schematic diagram of an intermediate process of a system-in-package structure according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a system-in-package structure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described In the background art, for example, the SIP (System In a Package System In Package) In the substrate type Package has the characteristics of high flexibility, high integration level, relatively low cost, small area, high frequency, high speed, and short production period, and the SIP packaging technology can be widely applied to the fields of industrial application and internet of things, and also has a very wide market In the fields of mobile phones, smart watches, smart bracelets, smart glasses, and the like. By applying the SIP system miniaturization design, the system design can be simplified and the equipment miniaturization can be met in a multi-element integration mode. The advantages of portability, wireless performance and instantaneity of the product can be increased without changing the appearance. But the existing SIP structure occupies a large area.
Based on this, the embodiment of the invention provides a system-in-package method, a system-in-package structure and electronic equipment, which effectively solve the problem that the system-in-package structure in the prior art occupies a large area and optimize the size of the system-in-package structure.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 8.
Referring to fig. 1, a flowchart of a system-level packaging method according to an embodiment of the present invention is shown, where the method includes:
s1, providing a substrate base plate.
S2, mounting a plurality of first passive devices and at least one chip on one side of the substrate base plate, wherein the first passive devices comprise external terminals deviating from one side of the substrate base plate.
And S3, forming a plastic package layer covering the first passive device and the at least one chip.
And S4, forming a hollow at the position of the plastic packaging layer corresponding to at least one first passive device.
S5, stacking a second passive device at the hollow-out position, wherein the second passive device is connected with the first passive device through the external terminal.
It should be noted that, after the molding layer covering the first passive device and the chip is formed, a hollow portion needs to be formed at a position, corresponding to at least one first passive device, of the molding layer, so that the molding layer exposes the at least one passive device, and a second passive device is conveniently stacked on the first passive device, and finally a stacked connection structure of the first passive device and the second passive device in the vertical direction is formed.
It can be understood that, in the technical scheme provided by the embodiment of the present invention, the first passive device and the second passive device are stacked to realize packaging, so that the problem of large occupied area caused by the fact that the first passive device and the second passive device are spread and mounted on the substrate in the horizontal direction is avoided, the problem of large occupied area of the system-in-package structure in the prior art is further effectively solved, and the size of the system-in-package structure is optimized.
The system-in-package method provided by the embodiment of the invention is described in more detail below with reference to fig. 2 to 6, and fig. 2 to 6 are schematic structural diagrams corresponding to steps in fig. 1.
As shown in fig. 2, corresponding to step S1, asubstrate 100 is provided.
In an embodiment of the present invention, the substrate provided by the present invention may be a circuit board. The surface of one side of the substrate base plate is used for mounting components, and the surface of the other side of the substrate base plate can be provided with external pins and the like, which is not limited in the invention.
As shown in fig. 3, corresponding to step S2, a plurality of firstpassive devices 210 and at least onechip 220 are mounted on one side of thesubstrate 100, wherein the firstpassive devices 210 includeexternal terminals 211 facing away from thesubstrate 100.
The first passive device provided by the present invention may be a resistor, a capacitor, an inductor, etc., and the first passive device needs to be specifically designed and selected according to practical applications, which is not specifically limited by the present invention. When the first passive device provided by the embodiment of the invention is mounted with the substrate base plate, the first passive device can be directly mounted at the pad pin on the side of the substrate base plate, so that the first passive device is electrically connected with the circuit of the substrate base plate.
The side of the external terminal, which is far away from the substrate base plate, provided by the embodiment of the invention is also provided with a welding metal layer, wherein the external terminal can be a copper column, and the side of the copper column, which is far away from the substrate base plate, can also be electroplated with the welding metal layer so as to facilitate the subsequent stacking welding of a second passive device. Wherein the solder metal layer may be a tin metal layer. In addition, the external terminal provided in the embodiment of the present invention may be a single terminal, or may be a combination of multiple terminals, which needs to be specifically designed according to the type of the first passive device, and the present invention is not particularly limited.
In an embodiment of the present invention, when the chip and the substrate are mounted, the chip may be mounted on the side of the substrate by means of an adhesive, and then the chip and the circuit of the substrate are electrically connected by means of a wire bonding, such as a bonding wire, and the present invention is not limited in particular. The first passive device provided by the embodiment of the invention can be arranged in a mode of surrounding the chip, and the first passive device is specifically designed according to actual application.
The first passive device and the mounting sequence of the chip and the substrate are not particularly limited, and need to be specifically selected according to actual application. Optionally, mounting a plurality of first passive devices and at least one chip on one side of the substrate base plate, includes: and mounting a plurality of first passive devices on one side of the substrate base plate, wherein the first passive devices comprise external terminals deviating from one side of the substrate base plate. And mounting a chip on one side of the substrate base plate, which is provided with the first passive device. And connecting the chip with the substrate base plate through a bonding wire.
In an embodiment of the present invention, the one or more chips provided by the present invention include a first sub-chip to an nth sub-chip, where N is an integer equal to or greater than 2; wherein a chip is mounted on one side of the substrate base plate, comprising: sequentially stacking and mounting the first sub-chip to the Nth sub-chip on one side of the substrate base plate; and respectively connecting the first sub-chip to the Nth sub-chip with the substrate base plate through bonding wires. The multiple sub-chips are stacked, so that the occupied area of the chips can be reduced, and the occupied area of the system-in-package structure is further reduced. As shown in fig. 3, thechip 220 provided in the embodiment of the present invention may include afirst sub-chip 221 and asecond sub-chip 222, where thefirst sub-chip 221 and thesecond sub-chip 222 are stacked, and both thefirst sub-chip 221 and thesecond sub-chip 222 are connected to thesubstrate 100 through abonding wire 223.
As shown in fig. 4, corresponding to step S3, amolding layer 300 is formed to cover the firstpassive device 210 and thechip 220.
In an embodiment of the invention, the molding layer provided by the invention includes at least one of silicon dioxide and epoxy resin. Furthermore, the plastic package layer provided by the invention also comprises some trace elements, so as to achieve the purpose of improving the sealing effect of the plastic package layer, and the type of the trace elements is not particularly limited in the invention.
As shown in fig. 5, corresponding to step S4, a hollow is formed at a position of themolding layer 300 corresponding to at least one of the firstpassive devices 210.
In the embodiment of the invention, the part of the plastic packaging layer corresponding to at least one first passive device needs to be removed to form a hollow, and the hollow is a reserved space for stacking a second passive device. Optionally, when the first passive device provided in the embodiment of the present invention is located at an edge of the system in package structure, the hollow portion may further extend to an outer side of the edge, so as to facilitate stacking of the second passive device. The plurality of first passive devices provided in the embodiment of the present invention may be disposed around the at least one chip, which is not limited in this respect.
The embodiment of the present invention can form a hollow in a manner of etching a plastic package layer, that is, forming a hollow at a position of the plastic package layer corresponding to at least one first passive device, including: and forming a hollow at a position of the plastic packaging layer corresponding to at least one first passive device by adopting an etching process. Or before forming a molding layer covering the first passive device and the chip, the method further comprises: arranging a shielding protective film on one side of at least one first passive device, which is far away from the substrate base plate; and removing the shielding protective film to remove the part of the plastic packaging layer corresponding to at least one first passive device to form the hollow part. Referring to fig. 7, in the embodiment of the invention, before forming theplastic package layer 300, the surface of the firstpassive device 210 on the side away from thesubstrate 100 is covered by the shieldingprotective film 310, and the shieldingprotective film 310 is reserved with a handle-removing structure, and then after forming theplastic package layer 300, the shieldingprotective film 310 is removed by the reserved handle-removing structure, and meanwhile, the plastic package part on the shieldingprotective film 310 is removed to form a hollow part.
In an embodiment of the invention, a material of the shielding protection film provided by the invention includes at least one of ETFE and PET.
As shown in fig. 6, corresponding to step S5, a secondpassive device 400 is stacked at the hollow, and the secondpassive device 400 is connected to the firstpassive device 210 through theexternal connection terminal 211.
The second passive device provided by the invention can be a resistor, a capacitor, an inductor and the like, and the second passive device needs to be specifically designed and selected according to practical application, and the invention is not particularly limited. Therefore, the first passive device and the second passive device are stacked to realize packaging, and the problem that the first passive device and the second passive device are spread on the substrate and are pasted on the substrate to cause large occupied area is avoided.
Based on the same inventive concept, an embodiment of the present invention further provides a system in package structure, which is manufactured by using the method provided in any one of the embodiments, wherein the system in package structure includes:
abase substrate 100.
A plurality of firstpassive devices 210 and at least onechip 220 are mounted on one side of thesubstrate 100, wherein the firstpassive devices 210 includeexternal terminals 211 facing away from thesubstrate 100.
Themolding compound layer 300 is located on a side of thechip 220 away from thesubstrate base plate 100, themolding compound layer 300 covers the at least onechip 220, and a position of themolding compound layer 300 corresponding to the at least one firstpassive device 210 is hollowed out.
A secondpassive device 400 is stacked at the hollow portion, and the secondpassive device 400 is connected to the firstpassive device 210 through theexternal terminal 211.
In an embodiment of the present invention, the substrate provided in the present invention may be a circuit board, and the circuit board may specifically be a printed circuit board, and the present invention is not limited in particular.
It can be understood that the plastic package layer provided by the invention covers the surface of the substrate with the first passive device and the exposed surface of one side of the chip, and the position of the plastic package layer corresponding to at least one first passive device is also provided with a hollow part to reserve a space for the subsequent stacking of the second passive devices. According to the technical scheme provided by the embodiment of the invention, the first passive device and the second passive device are stacked to realize packaging, so that the problem that the first passive device and the second passive device occupy a larger area due to being spread and mounted on the substrate is avoided, the problem that the system-level packaging structure occupies a larger area in the prior art is further effectively solved, and the size of the system-level packaging structure is optimized.
The first passive device provided by the present invention may be a resistor, a capacitor, an inductor, etc., and the first passive device needs to be specifically designed and selected according to practical applications, which is not specifically limited by the present invention. When the first passive device provided by the embodiment of the invention is mounted with the substrate base plate, the first passive device can be directly mounted at the pad pin on the side of the substrate base plate, so that the first passive device is electrically connected with the circuit of the substrate base plate.
The second passive device provided by the invention can be a resistor, a capacitor, an inductor, and the like, and the second passive device needs to be specifically designed and selected according to practical application, and the invention is not particularly limited. Therefore, the first passive device and the second passive device are stacked to realize packaging, and the problem that the first passive device and the second passive device are spread on the substrate and are pasted on the substrate to cause large occupied area is avoided.
Optionally, a welding metal layer is further disposed on a side of the external terminal, which is away from the substrate base plate, where the external terminal may be a copper pillar, and a welding metal layer may be further electroplated on a side of the copper pillar, which is away from the substrate base plate, so as to facilitate subsequent stacking and welding of a second passive device. Wherein the solder metal layer may be a tin metal layer. In addition, the external terminal provided in the embodiment of the present invention may be a single terminal, or may be a combination of multiple terminals, which needs to be specifically designed according to the type of the first passive device, and the present invention is not particularly limited.
In an embodiment of the present invention, when the chip and the substrate are mounted, the chip may be mounted on the side of the substrate through an adhesive, and then the chip and the circuit of the substrate are electrically connected in a wire bonding manner such as a bonding wire, which is not limited in the present invention. The first passive device provided by the embodiment of the invention can be arranged in a mode of surrounding the chip, and the first passive device is specifically designed according to actual application.
One or more chips provided by the invention can be in a single sub-chip structure; or, one or more chips provided by the embodiment of the present invention may further include a plurality of sub-chips, that is, the chip provided by the present invention includes a first sub-chip to an nth sub-chip, where N is an integer equal to or greater than 2; in the direction from the substrate base plate to the chip, the first sub chip to the Nth sub chip are sequentially stacked and attached to one side of the substrate base plate; the first sub-chip to the Nth sub-chip are respectively connected with the substrate through bonding wires, wherein the plurality of sub-chips are stacked to reduce the occupied area of the chip, and further reduce the occupied area of the system-in-package structure. As shown in fig. 8, thechip 220 provided in the embodiment of the present invention may include afirst sub-chip 221 and asecond sub-chip 222, where thefirst sub-chip 221 and thesecond sub-chip 222 are stacked, and both thefirst sub-chip 221 and thesecond sub-chip 222 are connected to thesubstrate 100 through abonding wire 223.
In any of the above embodiments of the present invention, the molding layer provided by the present invention includes at least one of silicon dioxide and epoxy resin. Furthermore, the plastic package layer provided by the invention also comprises some trace elements, so as to achieve the purpose of improving the sealing effect of the plastic package layer, and the type of the trace elements is not particularly limited in the invention.
Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, where the electronic device includes a system-in-package structure prepared according to the system-in-package method provided in any of the above embodiments.
The embodiment of the invention provides a system-level packaging method, a system-level packaging structure and electronic equipment, wherein the system-level packaging method comprises the following steps: providing a substrate base plate; mounting a plurality of first passive devices and at least one chip on one side of the substrate, wherein the first passive devices comprise external terminals on one side deviating from the substrate; forming a molding layer covering the first passive device and the at least one chip; forming a hollow-out at a position of the plastic packaging layer corresponding to at least one first passive device; and stacking a second passive device at the hollow-out part, wherein the second passive device is connected with the first passive device through the external terminal.
As can be seen from the above, in the technical scheme provided by the embodiment of the present invention, the first passive device and the second passive device are stacked to realize packaging, so that the problem of large occupied area caused by the fact that the first passive device and the second passive device are spread and mounted on the substrate is avoided, the problem of large occupied area of the system-in-package structure in the prior art is effectively solved, and the size of the system-in-package structure is optimized.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
Translated fromChinesePriority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011482023.2ACN112509932A (en) | 2020-12-15 | 2020-12-15 | System-level packaging method and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011482023.2ACN112509932A (en) | 2020-12-15 | 2020-12-15 | System-level packaging method and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115276586A (en)* | 2022-09-29 | 2022-11-01 | 南京融芯微电子有限公司 | Chebyshev response band elimination filter with electrostatic protection capability and packaging structure |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6117797A (en)* | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
| US20070181990A1 (en)* | 2006-02-03 | 2007-08-09 | Siliconware Precision Industries Co., Ltd. | Stacked semiconductor structure and fabrication method thereof |
| US20080088011A1 (en)* | 2006-10-12 | 2008-04-17 | Siliconware Precision Industries Co., Ltd. | Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof |
| KR20080058598A (en)* | 2006-12-22 | 2008-06-26 | 엘지이노텍 주식회사 | Component mounting module and passive element mounting method in the module |
| KR20080087195A (en)* | 2007-03-26 | 2008-10-01 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| CN102074559A (en)* | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | SiP (Session Initiation Protocol) system integrated-level IC (Integrated Circuit) chip packaging part and manufacturing method thereof |
| CN102157402A (en)* | 2011-03-23 | 2011-08-17 | 南通富士通微电子股份有限公司 | System-in-package method |
| CN105552065A (en)* | 2016-02-01 | 2016-05-04 | 中国电子科技集团公司第三十八研究所 | System-level package structure of T/R assembly control module and package method of system-level package structure |
| CN111009475A (en)* | 2019-11-22 | 2020-04-14 | 青岛歌尔智能传感器有限公司 | Packaging structure and packaging method of optical module |
| CN214068715U (en)* | 2020-12-15 | 2021-08-27 | 上海艾为电子技术股份有限公司 | System-in-package structure and electronic equipment |
- 2020
- 2020-12-15CNCN202011482023.2Apatent/CN112509932A/enactivePending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6117797A (en)* | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Attachment method for heat sinks and devices involving removal of misplaced encapsulant |
| US20070181990A1 (en)* | 2006-02-03 | 2007-08-09 | Siliconware Precision Industries Co., Ltd. | Stacked semiconductor structure and fabrication method thereof |
| US20080088011A1 (en)* | 2006-10-12 | 2008-04-17 | Siliconware Precision Industries Co., Ltd. | Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof |
| KR20080058598A (en)* | 2006-12-22 | 2008-06-26 | 엘지이노텍 주식회사 | Component mounting module and passive element mounting method in the module |
| KR20080087195A (en)* | 2007-03-26 | 2008-10-01 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| CN102074559A (en)* | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | SiP (Session Initiation Protocol) system integrated-level IC (Integrated Circuit) chip packaging part and manufacturing method thereof |
| CN102157402A (en)* | 2011-03-23 | 2011-08-17 | 南通富士通微电子股份有限公司 | System-in-package method |
| CN105552065A (en)* | 2016-02-01 | 2016-05-04 | 中国电子科技集团公司第三十八研究所 | System-level package structure of T/R assembly control module and package method of system-level package structure |
| CN111009475A (en)* | 2019-11-22 | 2020-04-14 | 青岛歌尔智能传感器有限公司 | Packaging structure and packaging method of optical module |
| CN214068715U (en)* | 2020-12-15 | 2021-08-27 | 上海艾为电子技术股份有限公司 | System-in-package structure and electronic equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115276586A (en)* | 2022-09-29 | 2022-11-01 | 南京融芯微电子有限公司 | Chebyshev response band elimination filter with electrostatic protection capability and packaging structure |
| CN115276586B (en)* | 2022-09-29 | 2022-12-30 | 南京融芯微电子有限公司 | Chebyshev response band elimination filter with electrostatic protection capability and packaging structure |
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