CN112364584A - Static time sequence analysis method based on distribution - Google Patents
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Abstract
Description
Technical Field
The invention relates to the technical field of Electronic Design Automation (EDA), in particular to a static time sequence analysis method based on distribution.
Background
In the design of an existing integrated circuit, timing sequence check is required to be performed on the design at each different stage to ensure that the designed circuit can meet the predetermined timing sequence requirement. Static Timing Analysis (STA) does not depend on excitation, and can quickly and accurately measure the circuit timing to measure the performance of the circuit.
Static timing analysis uses an exhaustive analysis method. It extracts all timing paths in the whole circuit, constructs a timing diagram, calculates the delay propagation of signals on the paths, and finds out the error violating the timing constraint.
The timing diagram mainly comprises logic nodes, connection relations and main input and output ports of the timing path. Wherein the logic node is a logic unit in design; the connection relation is the input and output relation of a logic unit in design; the primary input-output port is the designed input-output port.
With the increasing design scale of integrated circuits, the timing diagram of the whole circuit is very complex, some nodes on the timing path are also very numerous, and it takes a long time to perform static timing analysis on the whole circuit.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a static time sequence analysis method based on distribution, which is used for dividing the time sequence diagram of a circuit and then regrouping the time sequence diagram, and performing static time sequence analysis on all the time sequence diagrams in parallel, so that the time for performing static time sequence analysis on the whole circuit is shortened.
In order to achieve the above object, the present invention provides a static timing analysis method based on distributed mode, which includes the following steps:
establishing a timing diagram of the circuit and grouping;
searching a time sequence diagram to be split in each group of time sequence diagrams, and splitting the time sequence diagram into a plurality of time sequence subgraphs;
regrouping all the split timing charts;
reading design data required in a timing diagram of the new packet;
and carrying out static time sequence analysis on each group of time sequence diagrams of the new group in parallel.
Further, the step of searching the time sequence diagram to be split in each group of time sequence diagrams and splitting the time sequence diagram into a plurality of time sequence subgraphs further comprises the step of reserving nodes on the original time sequence diagram before and after the splitting point.
Further, the step of reserving the nodes in the original timing diagram before and after the split point further includes selecting the number of nodes reserved before the split point and the number of nodes reserved after the split point.
And further, judging whether the time sequence diagram is split or not according to the reserved number of nodes and the characteristics of the time sequence diagram.
Further, the step of determining whether to split the timing diagram according to the number of retained nodes and the characteristics of the timing diagram further includes splitting the timing diagram when the timing diagram satisfies the following characteristics:
each node in the time sequence subgraph only has one child node and at most only has one father node in the original time sequence graph;
if the root node of the time sequence subgraph has a father node in the original time sequence graph, the father node at least has two child nodes in the original time sequence graph;
if a leaf node of the time sequence subgraph has a child node in the original time sequence graph, the child node at least has two child nodes or at least has two father nodes in the original time sequence graph;
the total node number Q in the time sequence subgraph meets the following conditions:
Q≥（M+N）+R，
wherein, M is the number of nodes needing to be reserved before the selected splitting point, N is the number of nodes needing to be reserved after the splitting point, and R is an increment value additionally set by the minimum total number of nodes of the adjustment subgraph.
Further, the method also comprises the following steps of,
selecting splitting points of each subgraph, wherein the number S of the splitting points meets the following requirements:
1≤S≤（Q/(M+N+R）），
q is the total node number in the time sequence subgraph, M is the node number needing to be reserved before the selected split point, N is the node number needing to be reserved after the split point, and R is an increment value additionally set by the minimum total node number of the adjustment subgraph;
the number of nodes of each split time sequence subgraph is less than the total number of nodes of the original time sequence subgraph, and the difference of the number of nodes between the time sequence subgraphs is not more than 1.
Further, the step of performing the static timing analysis on each group of timing diagrams of the new group in parallel further includes counting data information of the timing diagrams in the current group, and reading and storing design data related to the current group.
Further, the step of performing a static timing analysis on each set of timing diagrams of the new packet in parallel further comprises,
transmitting the dependence between the split time sequence subgraphs according to design constraints;
directly analyzing the undisassembled time sequence diagram;
all timing diagrams were subjected to static timing analysis in parallel.
To achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the distributed static time sequence analysis method.
To achieve the above object, the present invention further provides a computer-readable storage medium having stored thereon a computer program which, when running, performs the steps of the distributed-based static timing analysis method as described above.
The static time sequence analysis method based on the distribution, the electronic equipment and the computer readable storage medium have the following beneficial effects:
1) dividing a timing diagram of a circuit into a plurality of groups; for each group of time sequence diagrams meeting the splitting condition, splitting the time sequence diagrams into a plurality of time sequence subgraphs according to a certain method; after splitting, the circuit timing diagrams need to be grouped again, and load balance among processes (or threads) is ensured when each newly established group is subjected to parallel timing analysis; each group of timing diagrams only needs to read part of design data required by timing analysis of the group of timing diagrams, including Netlist, Liberty, Spef, Sdc and the like; static timing analysis was performed on all timing diagrams in parallel. Because each group of timing diagrams only need to read part of design data required by the timing analysis, the time of static timing analysis is greatly saved.
2) After the time sequence diagram is split, the efficiency of parallel computation of the time sequence diagram is greatly improved compared with that before the time sequence diagram is split.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a distributed based static timing analysis method according to the present invention;
FIG. 2 is a schematic diagram of a top layer structure of a circuit after being grouped according to an embodiment of the invention;
FIG. 3 is a diagram illustrating a complete timing sequence for the setup in Group3 according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of screening long path subgraphs and marking split points in Group3 according to the embodiment of the invention;
FIG. 5 is a timing diagram for splitting by split point in Group3 according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a split version of Group3 according to an embodiment of the present invention;
FIG. 7 is a timing diagram for the new Group3 after a regrouping according to an embodiment of the invention;
FIG. 8 is a schematic diagram illustrating dependency relationships between timing graph subgraphs in an original Group3 according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a parallel timing analysis of each set of timing diagrams according to an embodiment of the invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a distributed static timing analysis method according to the present invention, and the distributed static timing analysis method according to the present invention will be described in detail with reference to fig. 1.
First, instep 101, a timing diagram of the entire circuit is established and grouped. In this step, there are many ways to group, but each group must have a complete timing diagram.
In this embodiment, there are various ways to establish the circuit timing diagrams and the groupings. For example, a timing diagram may be created by geometric partitioning, and the timing diagram is grouped according to the partitioned geometric blocks, where each group is a complete timing diagram.
Instep 102, a plurality of processes (or threads) are started, and a timing diagram to be split is found for each group of timing diagrams, and the timing diagram is split into a plurality of timing subgraphs. In this step, some timing charts are very complicated and long in timing path, and it takes a long time to analyze the timing charts. And the time sequence diagrams are screened out and are split into a plurality of time sequence subgraphs to perform time sequence analysis in parallel, so that the time for time sequence analysis can be shortened.
Preferably, some nodes are reserved before and after the split point.
In this embodiment, when one timing graph is split into multiple timing graphs, in order to ensure that the results of timing analysis before and after splitting are as consistent as possible, the multiple split timing subgraphs need to respectively keep some nodes on the original timing graphs before and after the split point. However, the sum of the nodes of the timing graph after the splitting is increased relative to the total number of nodes of the original timing graph.
Preferably, the number M (M ∈ Z) of nodes that need to be reserved before the selected splitting point can be manually set by the user, and the number N (N ∈ Z) of nodes that need to be reserved after the selected splitting point can be manually set by the user.
Preferably, whether the timing chart needs to be split can be judged according to the number of reserved nodes and the characteristics of the timing chart; splitting a timing chart into a plurality of timing subgraphs; the operations may be performed in parallel for each set of timing diagrams.
In this embodiment, all sub-graphs satisfying the following conditions are found on the timing chart: 1. each node in the subgraph has only one child node and at most one father node in the original time sequence graph; 2. if the root node of the subgraph has a father node in the original time sequence graph, the father node at least has two child nodes in the original time sequence graph; 3. if a leaf node of the subgraph has a child node P in the original time sequence graph, the child node P at least has two child nodes or at least has two father nodes in the original time sequence graph; 4. the total number of nodes Q and M, N in the subgraph is Q ≧ M + N) + R, where R (R ∈ Z) is an increment value additionally set to adjust the minimum total number of nodes of the subgraph, different values can be set for the timing diagrams of different features, and the user can set manually. If there are no subgraphs in the timing diagram that satisfy the above conditions, the timing diagram does not need to be split.
In this embodiment, a splitting point is selected for each sub-graph of the timing diagram that needs to be split. The number S of the splitting points satisfies 1 ≦ S ≦ (Q/(M + N + R)), and S ∈ Z. The location of the split point should be chosen based on the value of M, N. Meanwhile, after the subgraphs are split, the number of nodes owned by each time sequence subgraph needs to be ensured to be smaller than the total number of nodes of the original time sequence subgraph, and the difference of the number of nodes between the time sequence subgraphs is not larger than 1.
In this embodiment, the timing diagram is split according to the split node. Each split time sequence subgraph needs to extend M nodes forward or N nodes backward at the split point. Thus, only a timing diagram with a relatively small timing path exists in each set of timing diagrams.
Instep 103, after splitting, all timing diagrams of the circuit are regrouped.
Preferably, when grouping, the total number of nodes in each group of timing diagrams and the number of nodes on the longest path need to be counted, so that when analyzing each group of timing diagrams in parallel, the load among processes (or threads) is balanced.
In this embodiment, when regrouping, load balancing between processes (or threads) is mainly considered, so that optimal grouping needs to be performed according to the total number of nodes in the timing chart in each group and the number of nodes on the longest path.
Instep 104, a plurality of processes (or threads) are started, and design data required for timing analysis, including Netlist, Liberty, Spef, Sdc, etc., is read for each set of timing diagrams of the new packet.
Preferably, only a part of information required by each group is read when analyzing the Netlist, Liberty, Spef and Sdc files; storing the data of each group separately; the operations may be performed in parallel for each set of timing diagrams.
In this embodiment, for each newly grouped timing diagram, it is not necessary to read complete design data, but only read design data required in the timing diagram of the current group, and the method includes the following steps: 1) and counting Cell, Instance, Net and other information of Netlist in the current time sequence diagram. 2) When analyzing the Liberty, Spef and Sdc files, only the information related to the Cell, Instance and Net in the current group is read and stored. Thus, each set of timing diagrams has all the data needed for static timing analysis.
Instep 105, multiple processes (or threads) are started and a static timing analysis is performed in parallel for each set of timing diagrams of the new packet.
Preferably, for the time sequence subgraphs after the split, the dependency between the subgraphs is passed through Sdc setting; for the timing diagram which is not split, the analysis can be directly carried out; all timing diagrams can be subjected to static timing analysis in parallel.
In this embodiment, a static timing analysis of the split timing diagram is performed. Because of the dependency relationship among the multiple time sequence subgraphs in the split time sequence chart, after the time sequence subgraph analysis before the split point is completed, the analysis result is set to the input end of the time sequence subgraph after the split point in the form of an Sdc command (for example, set _ input _ transition).
In this embodiment, a static timing analysis is directly performed on an undisassembled timing chart.
In this embodiment, the split timing chart and the non-split timing chart may be submitted to the task scheduler at the same time, and when the dependency relationship is satisfied, the task scheduler is handed to the process (or the thread) to perform the static timing analysis.
The static timing analysis method based on distributed method of the present invention is further described with reference to an embodiment.
(1) And establishing a timing chart of the whole circuit, and grouping the timing charts of the circuit.
Fig. 2 is a schematic diagram of a circuit top layer structure after being grouped according to an embodiment of the invention, and fig. 2 is a schematic diagram of a certain circuit top layer structure. The circuit has 8 blocks, which are Block1-Block 8. Then, the circuit diagram is divided into 4 groups. For each group, a complete timing diagram needs to be built.
(2) Starting a plurality of processes (or threads), finding out a time sequence diagram needing to be split according to each group of time sequence diagrams, and splitting the time sequence diagram into a plurality of time sequence subgraphs.
Since the processing method is the same for each Group, only Group3 in the upper right corner of fig. 2 is illustrated separately in this step.
Fig. 3 is a diagram illustrating a complete timing sequence established in Group3 according to an embodiment of the present invention, and fig. 3 is a diagram illustrating a complete timing sequence established inGroup 3. The timing chart can be divided into 3 small timing charts according to the connection relationship between the nodes.
The first timing diagram is a path formed by 4 nodes from thenode 1 to thenode 4; the second timing diagram is a tree of 32 nodes from node 5 tonode 36; the third timing diagram is a path of 12 nodes fromnode 37 tonode 48.
Setting the number of nodes to be reserved before the splitting point
Number of nodes to be reserved after splitting a point
. Setting an incremental value for adjusting the total node number
When the timing diagram is a path is
When the timing diagram is a tree, it is
。
Fig. 4 is a schematic diagram of screening long-path subgraphs and marking split points in Group3 according to the embodiment of the invention, as shown in fig. 4, the long-path subgraphs screened for the three timing diagrams are shown in a dashed box.
For the first timing diagram, the selected sub-graph is itself. However, total number of subgraph nodes
For the second timing diagram, two subgraphs are selected. The first is a path composed of 4 nodes from thenode 11 to thenode 14, and the other is a path composed of 4 nodes from thenode 24 to thenode 27. The total number of nodes of the two subgraphs satisfies
Therefore, the method meets the splitting condition and can be split. Number of split points in two subgraphs
. And combining the values of M and N, and selecting thenode 13 and thenode 26 as splitting points.
For the third timing diagram, the selected subgraph is itself, again according to the selection rule. At this time, the total number of subgraph nodes
And the splitting condition is met. Number of splitting points
. And combining the values of M and N to select two splitting points, namely anode 41 and anode 44.
FIG. 5 is a timing diagram illustrating splitting by split point in Group3 according to an embodiment of the present invention.
Fig. 6 is a timing diagram after splitting in Group3 according to an embodiment of the present invention, and as shown in fig. 5 and fig. 6, the timing diagram after splitting by a split point is shown. Thus, the timing chart in Group3 becomes a 7-hour timing chart.
(3) After splitting, all timing diagrams of the circuit are regrouped.
Fig. 7 is a timing diagram of the new Group3 after regrouping according to an embodiment of the invention, and is a timing diagram of the Group3 after regrouping, as shown in fig. 7. It can be seen that there are only 3 timing diagrams in the new Group3 after the regrouping.
(4) Multiple processes (or threads) are started, and design data required for timing analysis, including Netlist, Liberty, Spef, Sdc, etc., is read for each set of timing diagrams.
Since the processing method of each Group is the same, in this step, it is also only described as Group3 alone.
In the new Group3, firstly, statistics is performed on the Instance, Cell and Net information corresponding to 27 nodes in Netlist in fig. 7; then, analyzing the Liberty file, and only reading the information of the cells; next, the Spef file is parsed, and only the information on the nets is read; finally, the Sdc file is analyzed, and only the settings related to the Instance, the Cell and the Net are read. The information is saved.
(5) Multiple processes (or threads) are started and a static timing analysis is performed in parallel for each set of timing diagrams.
Static timing analysis can be performed in parallel on the 3 timing diagrams in the new Group3 in fig. 7. However, for the split time sequence subgraphs, the dependency relationship between the time sequence subgraphs also needs to be considered during static time sequence analysis. The dependency of the time sequence diagram is set by Sdc.
Fig. 8 is a schematic diagram of the dependency relationships between the timing graph subgraphs in the original Group3 according to the embodiment of the present invention, and as shown in fig. 8, the dependency relationships between 7 timing graphs in the original Group3 are shown. Next, the timing diagram of the new Group3 is analyzed. For the new Group 3-timing diagram 1, static timing analysis can be directly performed; for the new Group 3-timing diagram 2, since it does not depend on any other timing diagram nodes, the static timing analysis can be directly performed; for the new Group 3-sequence diagram 3, it is necessary to wait for Timing information ofnodes 42 in other new groups to be calculated, and then set the Sdc command (e.g., set _ input _ transmission) to thenodes 42 in the new Group 3-sequence diagram 3, so as to continue the static Timing analysis.
Fig. 9 is a schematic diagram of performing parallel timing analysis on each group of timing diagrams according to an embodiment of the invention, and fig. 9 is a schematic diagram of a flow of performing parallel timing analysis on each group of timing diagrams. Parallel analysis is possible because each group has all the data needed for static timing analysis. Finally, the time sequence analysis reports obtained by each group are combined to form a complete report. Thus, a static timing analysis of the entire circuit is completed.
The invention provides a static time sequence analysis method based on distribution, which can greatly improve the efficiency of parallel computation of a time sequence chart after the time sequence chart is split compared with that before the time sequence chart is split, and the split time sequence chart needs to meet certain conditions. A static time sequence analysis method based on distribution. Dividing a timing diagram of a circuit into a plurality of groups; for each group of time sequence diagrams meeting the splitting condition, splitting the time sequence diagrams into a plurality of time sequence subgraphs according to a certain method; after splitting, the circuit timing diagrams need to be grouped again, and load balance among processes (or threads) is ensured when each newly established group is subjected to parallel timing analysis; each group of timing diagrams only needs to read part of design data required by timing analysis of the group of timing diagrams, including Netlist, Liberty, Spef, Sdc and the like; static timing analysis was performed on all timing diagrams in parallel.
In an embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the distributed static timing analysis method.
In an embodiment of the present invention, there is also provided a computer readable storage medium having stored thereon a computer program which when run performs the steps of the distributed based static timing analysis method as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A static time sequence analysis method based on distribution is characterized by comprising the following steps:
establishing a timing diagram of the circuit and grouping;
searching a time sequence diagram to be split in each group of time sequence diagrams, and splitting the time sequence diagram into a plurality of time sequence subgraphs;
regrouping all the split timing charts;
reading design data required in a timing diagram of the new packet;
and carrying out static time sequence analysis on each group of time sequence diagrams of the new group in parallel.
2. The distributed static timing analysis method according to claim 1, wherein the step of finding the timing graph to be split in each group of timing graphs and splitting the timing graph into a plurality of timing subgraphs further comprises reserving nodes on the original timing graph before and after the split point.
3. The distributed static timing analysis method according to claim 2, wherein the step of reserving nodes on the original timing graph before and after the split point further comprises selecting the number of nodes reserved before the split point and the number of nodes reserved after the split point.
4. The distributed static timing analysis method according to claim 3, wherein whether the timing graph is split is determined according to the number of nodes retained and the characteristics of the timing graph.
5. The distributed static timing analysis method according to claim 4, wherein the step of determining whether to split the timing graph according to the number of retained nodes and the characteristics of the timing graph further comprises splitting the timing graph when the timing graph satisfies the following characteristics:
each node in the time sequence subgraph only has one child node and at most only has one father node in the original time sequence graph;
if the root node of the time sequence subgraph has a father node in the original time sequence graph, the father node at least has two child nodes in the original time sequence graph;
if a leaf node of the time sequence subgraph has a child node in the original time sequence graph, the child node at least has two child nodes or at least has two father nodes in the original time sequence graph;
the total node number Q in the time sequence subgraph meets the following conditions:
Q≥（M+N）+R，
wherein, M is the number of nodes needing to be reserved before the selected splitting point, N is the number of nodes needing to be reserved after the splitting point, and R is an increment value additionally set by the minimum total number of nodes of the adjustment subgraph.
6. The distributed static timing analysis based method of claim 5, further comprising,
selecting splitting points of each subgraph, wherein the number S of the splitting points meets the following requirements:
1≤S≤（Q/(M+N+R）），
q is the total node number in the time sequence subgraph, M is the node number needing to be reserved before the selected split point, N is the node number needing to be reserved after the split point, and R is an increment value additionally set by the minimum total node number of the adjustment subgraph;
the number of nodes of each split time sequence subgraph is less than the total number of nodes of the original time sequence subgraph, and the difference of the number of nodes between the time sequence subgraphs is not more than 1.
7. The distributed static timing analysis method according to claim 1, wherein the step of performing static timing analysis on each group of timing charts of the new group in parallel further comprises counting data information of the timing charts in the current group, and reading and saving design data related to the current group.
8. The distributed static timing analysis-based method of claim 1 wherein said step of performing static timing analysis on each set of timing graphs for a new group in parallel further comprises,
transmitting the dependence between the split time sequence subgraphs according to design constraints;
directly analyzing the undisassembled time sequence diagram;
all timing diagrams were subjected to static timing analysis in parallel.
9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the distributed static timing analysis method according to any one of claims 1 to 8.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program executes the steps of the distributed static timing analysis method according to any of claims 1 to 8.
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