CN112309858A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a gate structure is formed on the substrate, and the gate structure crosses the fin part and covers part of the top and part of the side wall of the fin part; forming a first source-drain doping layer in the fin parts on two sides of the grid structure; forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source drain doping layer or a second source drain doping layer positioned below the first source drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed out of the protective layer or the second source-drain doping layer positioned below the first source-drain doping layer; forming an interlayer dielectric layer covering the second source drain doping layer on the protection layer; and forming a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer. The embodiment of the invention is beneficial to reducing the contact resistance of the source-drain doping layer and the contact hole plug.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the gradual development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. In order to adapt to the reduction of process nodes, the channel length of the MOSFET field effect transistor is correspondingly and continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage pinch-off (ping off) channel is increased, and the sub-threshold leakage (SCE) phenomenon, namely, the so-called short-channel effect (SCE) is easier to occur.

Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFETs to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.

Disclosure of Invention

The embodiment of the invention provides a semiconductor structure and a forming method thereof, which can reduce the contact resistance of a source-drain doping layer and a contact hole plug.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a gate structure is formed on the substrate, and the gate structure stretches across the fin part and covers part of the top and part of the side wall of the fin part; forming a first source-drain doping layer in the fin parts on two sides of the grid structure; forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source drain doping layer or a second source drain doping layer positioned below the first source drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed out of the protective layer or the second source-drain doping layer positioned below the first source-drain doping layer; forming an interlayer dielectric layer on the protective layer, wherein the interlayer dielectric layer covers the second source drain doping layer; and forming a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer.

Optionally, the step of forming the first source-drain doping layer includes: etching the fin parts on two sides of the grid structure, and forming grooves in the fin parts on two sides of the grid structure; and forming the first source drain doping layer in the groove, wherein the top of the first source drain doping layer is higher than the top of the fin part.

Optionally, the number of the second source-drain doping layers is one, and the step of forming the second source-drain doping layers includes: forming a protective layer exposing the top of the first source-drain doping layer on the substrate exposed by the gate structure, wherein the top of the protective layer is higher than the top of the fin portion and lower than the top of the first source-drain doping layer; and forming the epitaxial layer on the first source-drain doping layer exposed out of the protective layer by adopting an epitaxial process, and forming the second source-drain doping layer by in-situ self-doping ions in the process of forming the epitaxial layer.

Optionally, the material of the protective layer is a dielectric material.

Optionally, the protective layer and the interlayer dielectric layer are made of the same material.

Optionally, the step of forming the contact hole plug includes: etching the interlayer dielectric layer and the protective layer to form a contact hole exposing the first source drain doping layer and the second source drain doping layer; and forming a contact hole plug for filling the contact hole.

Optionally, the groove is sigma shaped.

Optionally, the first source-drain doping layer or the second source-drain doping layer has a diamond structure in an extending direction perpendicular to the fin portion.

Optionally, after forming the contact hole and before forming the contact hole plug, the method further includes: and forming silicide layers on the surfaces of the first source-drain doping layer and the second source-drain doping layer exposed from the contact hole.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the fin part protrudes out of the substrate; the grid electrode structure stretches across the fin part and covers part of the top and part of the side wall of the fin part; the first source drain doping layer is positioned in the fin parts on two sides of the grid structure; the protective layer is positioned on the substrate, is at the same layer with the first source-drain doping layer and exposes the top of the first source-drain doping layer; at least one second source-drain doping layer located on the first source-drain doping layer exposed out of the protection layer; the interlayer dielectric layer is positioned on the protective layer and covers the second source drain doping layer; and the contact hole plug is positioned in the interlayer dielectric layer and the protective layer and surrounds the first source-drain doping layer and the second source-drain doping layer.

Optionally, the top of the first source-drain doping layer is higher than the top of the fin portion; the number of the second source-drain doped layers is one; the top of the protective layer is higher than the top of the fin part and lower than the top of the first source drain doping layer; the second source-drain doping layer comprises an epitaxial layer which is positioned on the first source-drain doping layer exposed out of the protective layer and is doped with ions.

Optionally, the material of the protective layer is a dielectric material.

Optionally, the protective layer and the interlayer dielectric layer are made of the same material.

Optionally, the material of the protective layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride.

Optionally, the semiconductor structure further includes: and the silicide layers are positioned between the first source drain doping layer and the contact hole plug and between the second source drain doping layer and the contact hole plug.

Optionally, in the normal direction of the substrate surface, the distance between the top of the protection layer and the top of the first source-drain doping layer is 1 nm to 3 nm.

Optionally, in the normal direction of the substrate surface, the top of the second source-drain doping layer is lower than the top of the gate structure, and the distance between the top of the second source-drain doping layer and the top of the gate structure is 100 to 500 angstroms.

Optionally, the first source-drain doping layer or the second source-drain doping layer has a diamond structure in an extending direction perpendicular to the fin portion.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the embodiment of the invention, at least one second source-drain doping layer is formed on the first source-drain doping layer after the first source-drain doping layer, that is, the source-drain doping layer formed in the embodiment of the invention is of a laminated structure, and compared with the scheme that the source-drain doping layer is not of a laminated structure, the embodiment of the invention is easy to increase the surface area of the source-drain doping layer by adjusting the size and the profile morphology of the first source-drain doping layer and the second source-drain doping layer, so that when a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer is formed subsequently, the contact area of the contact hole plug and the first source-drain doping layer and the second source-drain doping layer is increased, and the contact resistance of the source-drain doping layer and the contact hole plug is further reduced.

In addition, the embodiment of the invention increases the contact surface of the source-drain doping layer along the direction vertical to the substrate (longitudinal direction), and is beneficial to preventing the problem that the adjacent source-drain doping layers are easy to generate short circuit (merge) due to the overlarge transverse size of the source-drain doping layer compared with the scheme of increasing the surface of the source-drain doping layer along the direction vertical to the fin portion (transverse direction).

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

FIGS. 2 to 13 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 14 and 15 are schematic structural diagrams of an embodiment of a semiconductor structure of the present invention.

Detailed Description

The devices formed at present still have the problem of poor performance. The semiconductor structure is now combined to analyze the cause of poor device performance.

Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.

The semiconductor structure includes: asubstrate 1; afin portion 2 protruding from thesubstrate 1; a gate structure (not shown) crossing thefin 2 and covering a portion of the top and a portion of the sidewalls of thefin 2; the source-drain doping layer 3 is positioned in thefin parts 2 at two sides of the grid structure; the interlayer dielectric layer 4 is positioned on thesubstrate 1 and covers the source-drain doping layer 3; and thecontact hole plug 5 is positioned in the interlayer dielectric layer 4 and surrounds the source-drain doping layer 3.

In the semiconductor structure, thecontact hole plug 5 surrounds the source-drain doping layer 3, so that the contact area between thecontact hole plug 5 and the source-drain doping layer 3 is increased.

However, as the critical dimension of the device is further reduced, the dimension of the source-drain doping layer 3 is also continuously reduced, and the surface area of the source-drain doping layer 3 is also reduced, which results in that the contact area between thecontact hole plug 5 and the source-drain doping layer 3 is also smaller, and the contact resistance between thecontact hole plug 5 and the source-drain doping layer 3 is difficult to meet the process requirements.

In the prior art, the size of the source-drain dopedlayer 3 is increased, so that the surface area of the source-drain dopedlayer 3 is increased, and the contact area between thecontact hole plug 5 and the source-drain dopedlayer 3 is increased to reduce the contact resistance.

However, increasing the size of the source and drain dopedlayers 3 also increases the size of the source and drain dopedlayers 3 along the direction (lateral direction) perpendicular to the extending direction of thefin 2. Along with the reduction of the critical dimension of the device, the distance between theadjacent fin parts 2 is also reduced continuously, the transverse dimension of the source-drain doping layer 3 is large, and the problem that the distance between the adjacent source-drain doping layers 3 is too short-circuited easily is caused.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a gate structure is formed on the substrate, and the gate structure stretches across the fin part and covers part of the top and part of the side wall of the fin part; forming a first source-drain doping layer in the fin parts on two sides of the grid structure; forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source drain doping layer or a second source drain doping layer positioned below the first source drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed out of the protective layer or the second source-drain doping layer positioned below the first source-drain doping layer; forming an interlayer dielectric layer on the protective layer, wherein the interlayer dielectric layer covers the second source drain doping layer; and forming a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer.

In the embodiment of the invention, at least one second source-drain doping layer is formed on the first source-drain doping layer after the first source-drain doping layer, that is, the source-drain doping layer formed in the embodiment of the invention is of a laminated structure, and compared with the scheme that the source-drain doping layer is not of a laminated structure, the embodiment of the invention is easy to increase the surface area of the source-drain doping layer by adjusting the size and the profile morphology of the first source-drain doping layer and the second source-drain doping layer, so that when a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer is formed subsequently, the contact area of the contact hole plug and the first source-drain doping layer and the second source-drain doping layer is increased, and the contact resistance of the source-drain doping layer and the contact hole plug is further reduced.

In addition, the embodiment of the invention increases the contact surface of the source-drain doping layer along the direction vertical to the substrate (longitudinal direction), and is beneficial to preventing the problem that the adjacent source-drain doping layers are easy to generate short circuit due to the overlarge transverse dimension of the source-drain doping layer compared with the scheme of increasing the surface of the source-drain doping layer along the direction vertical to the fin portion (transverse direction).

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 2 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 2 and 3, fig. 2 is a cross-sectional view along a vertical fin extending direction, fig. 3 is a cross-sectional view along a fin extending direction, a base (not labeled) is provided, the base includes asubstrate 100 and a fin 110 protruding from thesubstrate 100, agate structure 135 is formed on the base, and thegate structure 135 crosses over thefin 110 and covers a portion of a top and a portion of a sidewall of thefin 110.

Thesubstrate 100 provides a process platform for subsequently forming semiconductor structures.

In this embodiment, thesubstrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

Thefin 110 is used to provide a conductive channel for the field effect transistor during operation.

Thefin 110 is the same material as thesubstrate 100. In this embodiment, thefin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

In this embodiment, after thesubstrate 100 and thefin portion 110 are formed, the method further includes: anisolation layer 120 is formed on thesubstrate 100 where thefins 110 are exposed, and theisolation layer 120 covers a portion of sidewalls of thefins 110.

Theisolation layer 120 serves as an isolation structure of the semiconductor structure, and is used for isolating adjacent devices. In this embodiment, the material of theisolation layer 120 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride, silicon oxynitride, or other insulating materials.

In this embodiment, thegate structure 135 is a dummy gate structure (dummy gate), and thegate structure 135 occupies a space for forming a metal gate structure subsequently.

In this embodiment, thegate structure 135 is a single layer structure, and thegate structure 135 includes a gate layer. The material of the gate layer can be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon. In this embodiment, the gate layer is made of polysilicon.

In other embodiments, the gate structure may also be a stacked structure, and the gate structure respectively includes a gate oxide layer and a gate layer on the gate oxide layer. In this embodiment, the material of the gate oxide layer may be silicon oxide or silicon oxynitride.

In this embodiment, the step of forming thegate structure 135 includes: forming a gate material layer (not shown) crossing thefins 110 and covering the top and sidewalls of thefins 110; forming a patternedgate mask layer 121 on the gate material layer; and patterning the gate material layer by using thegate mask layer 121 as a mask to form thegate structure 135.

In this embodiment, after thegate structure 135 is formed, thegate mask layer 121 is retained, and thegate mask layer 121 can protect the top of thegate structure 135 in a subsequent process. In this embodiment, thegate mask layer 121 is made of silicon nitride.

In this embodiment, after forming thegate structure 135, the forming method further includes: asidewall spacer 122 is formed on the sidewall of thegate structure 135.

The sidewall spacers 122 are used to protect the sidewalls of thegate structures 135, and thesidewall spacers 122 are also used to define a formation region of a subsequent first source-drain doping layer.

The material of thesidewall 122 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, boron nitride, and boron carbonitride, and thesidewall 122 may have a single-layer structure or a stacked structure. In this embodiment, thesidewall 122 has a single-layer structure, and the material of thesidewall 122 is silicon nitride.

It should be noted that, for convenience of illustration and description, thegate structure 135, thegate mask layer 121, and thesidewalls 122 are only illustrated in a cross-sectional view along the extending direction of thefin 110 in the embodiment.

Referring to fig. 4 to 7, fig. 4 and 6 are cross-sectional views along a direction perpendicular to an extending direction of the fin, and fig. 5 and 7 are cross-sectional views along the extending direction of the fin, wherein first source/drain doping layers 130 are formed in thefin 110 on both sides of the gate structure 135 (as shown in fig. 6).

The first source-drain doping layer 130 is used for providing a process foundation for the subsequent formation of a second source-drain doping layer, and the first source-drain doping layer 130 and the subsequent second source-drain doping layer form a source-drain doping layer of the semiconductor structure.

When an NMOS transistor is formed, the first source-drain dopedlayer 130 comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the first source-drain dopedlayer 130 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.

In this embodiment, the step of forming the first source-drain doping layer 130 includes: as shown in fig. 4 and 5, thefin portions 110 on two sides of thegate structure 135 are etched, and agroove 145 is formed in thefin portions 110 on two sides of thegate structure 135; as shown in fig. 6 and 7, the first source-drain doping layer 130 is formed in therecess 145, and a top of the first source-drain doping layer 130 is higher than a top of thefin 110.

In this embodiment, therecess 145 is sigma shaped. In other embodiments, the recess may also be bowl-shaped or rectangular.

In this embodiment, the top of the first source-drain doping layer 130 is higher than the top of thefin portion 110, so as to provide a process basis for subsequently forming a protection layer exposing the top of the first source-drain doping layer 130 and covering thefin portion 110, and further, a second source-drain doping layer can be subsequently formed on the first source-drain doping layer 130 exposed by the protection layer.

In this embodiment, an epitaxial layer is formed in thegroove 145 by an epitaxial process, and the first source-drain doping layer 130 is formed by in-situ self-doping ions in the process of forming the epitaxial layer. Wherein the epitaxial layer is used as the stress layer.

In this embodiment, the first source-drain doping layer 130 has a sigma-shaped structure, that is, the first source-drain doping layer 130 has a diamond structure along an extending direction perpendicular to thefin portion 110. In other embodiments, the shape of the first source-drain doped layer may also be mushroom-shaped, inverted bowl-shaped, or other shapes.

Referring to fig. 8 to 10, at least one second source-drain doping layer 160 is formed on the first source-drain doping layer 130 (as shown in fig. 10), and the step of forming the second source-drain doping layer 160 includes: forming aprotection layer 150 on thesubstrate 100 and exposing the first source-drain doping layer 130 or the second source-drain doping layer 160 below; a second source-drain doping layer 160 is formed on the first source-drain doping layer 130 exposed by theprotection layer 150 or the second source-drain doping layer 160 located below.

In this embodiment, after the first source-drain doping layer 130 is formed, at least one second source-drain doping layer 160 is further formed on the first source-drain doping layer 130, that is, the source-drain doping layer formed in this embodiment is of a stacked structure, and compared with a scheme that the source-drain doping layer is not of a stacked structure, in this embodiment, the surface area of the source-drain doping layer is made larger by adjusting the size and the profile morphology of the first source-drain doping layer 130 and the second source-drain doping layer 160, so that when a contact hole plug surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160 is formed subsequently, the contact area between the contact hole plug and the first source-drain doping layer 130 and the second source-drain doping layer 160 is increased, and further, the contact resistance between the source-drain doping layer and the contact hole plug.

In addition, in the embodiment, the contact surface of the source/drain doping layer is increased in the direction (longitudinal direction) perpendicular to thesubstrate 100, and compared with the scheme of increasing the surface of the source/drain doping layer in the direction (transverse direction) perpendicular to the fin portion, the method is favorable for preventing the problem that short circuit (merge) is easy to occur between adjacent source/drain doping layers due to the fact that the transverse dimension of the source/drain doping layer is too large.

In this embodiment, the second source-drain doping layer 160 and the first source-drain doping layer 130 are made of the same material.

When an NMOS transistor is formed, the second source-drain dopedlayer 160 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions, or Sb ions; when a PMOS transistor is formed, the second source-drain doping layer 160 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.

In this embodiment, the number of the second source-drain doping layers 160 is one. In other embodiments, the number of the second source-drain doped layers is not limited to one.

It should be noted that, in this embodiment, the top of the second source-drain doping layer 160 is lower than the top of thegate structure 135, so as to provide a process foundation for forming an interlayer dielectric layer on thesubstrate 100 exposed by thegate structure 135 and forming a contact hole plug surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160.

In the normal direction of the surface of thesubstrate 100, the distance between the top of the second source-drain doping layer 160 and the top of thegate structure 135 should not be too small or too large. If the distance is too small, the height of the top of the second source-drain doping layer 160 is correspondingly larger, and the relative area between the second source-drain doping layer 160 and thegate structure 135 is correspondingly larger, which easily increases the parasitic capacitance between the source-drain doping layer and thegate structure 135, and also easily increases the difficulty of forming an interlayer dielectric layer on thesubstrate 100 exposed by thegate structure 135 and forming a contact hole plug surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160; if the distance is too large, the height of the top of the second source-drain dopedlayer 160 is correspondingly small, which easily results in an insignificant effect of increasing the contact surface of the source-drain doped layer. For this reason, in this embodiment, in the normal direction of the surface of thesubstrate 100, the distance between the top of the second source-drain doping layer 160 and the top of thegate structure 135 is 100 to 500 angstroms.

Specifically, in this embodiment, the step of forming the second source-drain doping layer 160 includes:

as shown in fig. 8 and 9, a protection layer 150 (shown in fig. 9) exposing the top of the first source/drain doping layer 130 is formed on thesubstrate 100 exposed by the gate structure 135 (shown in fig. 7), and the top of theprotection layer 150 is higher than the top of thefin 110 and lower than the top of the first source/drain doping layer 130. Specifically, theprotective layer 150 is formed on theisolation layer 120.

The forming of the second source/drain doping layer generally includes an epitaxial process, and theprotection layer 150 is used to play a role of a mask in the subsequent step of forming the second source/drain doping layer, so as to protect a portion of the sidewall of the first source/drain doping layer 130 and prevent epitaxial growth on the entire surface of the first source/drain doping layer 130.

Moreover, the top of theprotection layer 150 is higher than the top of thefin 110, so as to prevent epitaxial growth based on thefin 110 when forming the second source-drain doping layer 160 in the subsequent process.

In this embodiment, the material of theprotection layer 150 is a dielectric material. By selecting the dielectric material, the influence of theprotective layer 150 on the performance of the semiconductor structure can be reduced, and theprotective layer 150 does not need to be removed subsequently, thereby simplifying the process steps and improving the process compatibility.

The material of theprotective layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the material of theprotection layer 150 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming theprotective layer 150.

It should be noted that, along the normal direction of the surface of thesubstrate 100, the distance between the top of theprotection layer 150 and the top of the first source-drain doping layer 130 is not too small or too large. If the distance is too small, the height of the first source-drain doping layer 130 exposed by theprotection layer 150 is correspondingly too small, and when a second source-drain doping layer is formed on the first source-drain doping layer 130 exposed by theprotection layer 150, the volume of the second source-drain doping layer is correspondingly too small, so that the effect of increasing the surface area of the source-drain doping layer is not obvious, and the second source-drain doping layer is formed by an epitaxial process generally, so that the process difficulty of the epitaxial process is increased easily when the height of the first source-drain doping layer 130 exposed by theprotection layer 150 is too small; if the distance is too large, the risk that theprotective layer 150 exposes thefin portion 110 is easily increased, and a second source-drain doped layer is easily formed on the side wall of the first source-drain dopedlayer 130, so that the lateral dimension of the source-drain doped layer is too large, and the risk that a short circuit problem occurs between adjacent source-drain doped layers is also easily increased. For this reason, in this embodiment, in the normal direction of the surface of thesubstrate 100, the distance between the top of theprotection layer 150 and the top of the first source-drain doping layer 130 is 1 nm to 3 nm.

In this embodiment, the step of forming theprotection layer 150 includes: as shown in fig. 8, aninitial protection layer 140 covering the first source-drain doping layer 130 is formed on the substrate; as shown in fig. 9, a portion of theinitial protection layer 140 is removed, and theinitial protection layer 140 is left as theprotection layer 150.

In this embodiment, theinitial protection layer 140 is formed by a Flowable Chemical Vapor Deposition (FCVD) process. By selecting the flowable chemical vapor deposition process, the filling capacity of theinitial protection layer 140 material is improved, so that the probability of generating defects such as voids (void) in theinitial protection layer 140 is reduced, and the formation quality of theprotection layer 150 is correspondingly improved.

In this embodiment, in the step of forming theinitial protection layer 140, theinitial protection layer 140 further covers the top of thegate structure 135. Therefore, in this embodiment, before removing a part of the thickness of theinitial protection layer 140, the method further includes: theinitial protection layer 140 above the top of thegate mask layer 122 is removed by a planarization process.

Through the planarization process, the top surface flatness of theinitial protection layer 140 is improved, and accordingly, the top surface flatness of theprotection layer 150 is advantageously improved. Specifically, in this embodiment, the planarization process is performed by using a Chemical-Mechanical Polishing (CMP) process.

In this embodiment, a dry etching process is used to remove a portion of the thickness of theinitial protection layer 140.

The dry etching process is easy to realize anisotropic etching, has good process controllability, and is beneficial to accurately etching theinitial protection layer 140, so that the height of theprotection layer 150 meets the process requirements.

In this embodiment, taking the number of the second source-drain doping layers 160 as one example, only oneprotection layer 150 is correspondingly formed. In other embodiments, when the number of the second source-drain doping layers is greater than or equal to two, a plurality of protection layers may be correspondingly formed.

As shown in fig. 10, an epitaxial process is used to form the epitaxial layer on the first source/drain doping layer 130 exposed by theprotection layer 150, and the second source/drain doping layer 160 is formed by in-situ self-doping ions in the process of forming the epitaxial layer.

Specifically, the epitaxial layer serves as the stress layer to provide a compressive stress or tensile stress effect for the channel region.

By adopting the epitaxial process, the second source-drain doping layer 160 material with higher purity can be obtained, and the formation quality of the second source-drain doping layer 160 can be further improved.

In this embodiment, after the second source-drain doping layer 160 is formed by an epitaxial process, the second source-drain doping layer 160 also has a diamond structure along the extending direction perpendicular to thefin 110. In other embodiments, the shape of the second source-drain doping layer may also be mushroom-shaped, inverted bowl-shaped, or other shapes.

In this embodiment, the second source-drain doping layer 160 and the first source-drain doping layer 130 are both diamond-shaped along the extending direction perpendicular to thefin portion 110, which is beneficial to further increase the surface area of the formed source-drain doping layer.

Referring to fig. 11, aninterlayer dielectric layer 170 is formed on theprotection layer 150, and theinterlayer dielectric layer 170 covers the second source-drain doping layer 160.

After theinterlayer dielectric layer 170 is formed, theinterlayer dielectric layer 170 and theprotection layer 150 form a dielectric layer for isolating adjacent devices, and theinterlayer dielectric layer 170 and theprotection layer 150 also provide a process platform for forming a contact hole plug surrounding the second source-drain doping layer 160 and the first source-drain doping layer 130.

Accordingly, the material of theinterlayer dielectric layer 170 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

In this embodiment, the material of theinterlayer dielectric layer 170 is the same as that of theprotective layer 150, and the material of theinterlayer dielectric layer 170 is silicon oxide, which is beneficial to improving process compatibility.

Referring to fig. 12 to 13, contact hole plugs 190 (shown in fig. 13) surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160 are formed in theinterlayer dielectric layer 170 and theprotective layer 150.

The contact hole plugs 190 are used to electrically connect the source-drain doped layers with other interconnect structures or external circuitry.

In this embodiment, the surface area of the source-drain doping layer formed by the first source-drain doping layer 130 and the second source-drain doping layer 160 is large, so that when thecontact hole plug 190 surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160 is formed, the contact area between thecontact hole plug 190 and the first source-drain doping layer 130 and the contact area between thecontact hole plug 190 and the second source-drain doping layer 160 are increased, and further, the contact resistance between the source-drain doping layer and thecontact hole plug 190 is reduced.

In this embodiment, thecontact plug 190 is made of tungsten. In other embodiments, the material of the contact hole plug may also be other conductive materials such as cobalt.

In this embodiment, the step of forming thecontact hole plug 190 includes:

as shown in fig. 12, theinterlayer dielectric layer 170 and theprotection layer 150 are etched to form acontact hole 200 exposing the first source-drain doping layer 130 and the second source-drain doping layer 160.

Thecontact hole 200 provides a spatial location for the subsequent formation of a contact hole plug. Thecontact hole 200 exposes the first sourcedrain dopant layer 130 and the second sourcedrain dopant layer 160, thereby providing for subsequent contact hole plugs to surround the first sourcedrain dopant layer 130 and the second sourcedrain dopant layer 160.

In this embodiment, theinterlayer dielectric layer 170 and theprotective layer 150 are etched by a dry etching process.

As shown in fig. 13, acontact hole plug 190 filling thecontact hole 200 is formed.

Specifically, a conductive layer (not shown) is formed to fill thecontact hole 200 and cover the top of theinterlayer dielectric layer 170; and removing the conductive layer higher than the top of theinterlayer dielectric layer 170, and using the residual conductive layer as thecontact hole plug 190.

In this embodiment, the conductive layer is formed by a chemical vapor deposition process.

In this embodiment, a chemical mechanical polishing process is used to remove the conductive layer higher than the top of theinterlayer dielectric layer 170, so as to improve the flatness of the top surface of thecontact hole plug 190.

In this embodiment, referring to fig. 12 in combination, after forming thecontact hole 200 and before forming thecontact hole plug 190, the method further includes: and forming asilicide layer 180 on the surfaces of the first source-drain doping layer 130 and the second source-drain doping layer 160 exposed from thecontact hole 200.

After the contact hole plug filling thecontact hole 200 is formed subsequently, thesilicide layer 180 is located between the first source-drain doping layer 130 and the contact hole plug, and between the second source-drain doping layer 160 and the contact hole plug, and thesilicide layer 180 is used for reducing contact resistance between the contact hole plug and the first source-drain doping layer 130 and the second source-drain doping layer 160, improving adhesiveness between the contact hole plug and the first source-drain doping layer 130 and the second source-drain doping layer 160, and further improving contact performance between the contact hole plug and the source-drain doping layer.

The material of thesilicide layer 180 may be TiSi, NiSi, CoSi, or the like. In this embodiment, the material of thesilicide layer 180 is TiSi.

It should be further noted that, in this embodiment, thegate structure 135 is a dummy gate structure, and therefore, after the forming theinterlayer dielectric layer 170 and before the forming thecontact hole 200, the forming method further includes: removing thegate mask layer 121 and thegate structure 135, and forming a gate opening (not shown) in theinterlayer dielectric layer 170; a metal gate structure (not shown) is formed in the gate opening.

The gate opening provides a spatial location for forming a metal gate structure.

The metal gate structure is used for controlling the on and off of the conducting channel when the field effect transistor works.

A metal gate structure crosses thefin 110 and covers a portion of the top and a portion of the sidewalls of thefin 110. The metal gate structure includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) on the gate dielectric layer.

The gate dielectric layer is used to electrically isolate the metal gate structure from thefin 110. In this embodiment, the gate dielectric layer is made of a high-k dielectric material. Specifically, the material of the gate dielectric layer is HfO₂. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al₂O₃And the like.

The gate electrode layer is used to electrically connect the metal gate structure to other interconnect structures or external circuitry. In this embodiment, the gate electrode layer is made of a magnesium-tungsten alloy. In other embodiments, the gate electrode layer may be made of W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.

The detailed description of the steps related to forming the metal gate structure is omitted here for brevity.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 14 to 15, fig. 14 is a cross-sectional view taken along a direction perpendicular to a direction in which the fin extends, and fig. 15 is a cross-sectional view taken along the direction in which the fin extends, illustrating a schematic structural view of an embodiment of a semiconductor structure according to the present invention.

The semiconductor structure includes: asubstrate 300; afin 310 protruding from thesubstrate 300; agate structure 400 crossing thefin 310 and covering a portion of the top and a portion of the sidewall of thefin 310; the first source-drain doping layer 330 is located in thefin portions 310 on two sides of thegate structure 400; theprotective layer 350 is located on thesubstrate 300, is at the same layer as the first source-drain doping layer 330, and exposes the top of the first source-drain doping layer 330; at least one second source-drain doping layer 360 located on the first source-drain doping layer 330 exposed by theprotection layer 350; aninterlayer dielectric layer 370, located on theprotection layer 350 and covering the second source draindoping layer 360; and acontact hole plug 390 positioned in theinterlayer dielectric layer 370 and theprotection layer 350 and surrounding the first source draindoping layer 330 and the second source draindoping layer 360.

In this embodiment, the semiconductor structure includes at least one second source-drain doping layer 360 on the first source-drain doping layer 330 exposed by theprotection layer 350, that is, the source-drain doping layer of the semiconductor structure provided in this embodiment is a stacked structure, and compared with a scheme in which the source-drain doping layer is not a stacked structure, the embodiment is easy to increase the surface area of the source-drain doping layer by adjusting the size and the profile morphology of the first source-drain doping layer 330 and the second source-drain doping layer 360, thereby being beneficial to increasing the contact area between thecontact hole plug 390 and the first source-drain doping layer 330 and the second source-drain doping layer 360, and further being beneficial to reducing the contact resistance between the source-drain doping layer and thecontact hole plug 390.

In addition, in the embodiment, the contact surface of the source and drain doping layer is increased in the direction (longitudinal direction) perpendicular to thesubstrate 300, and compared with the scheme that the surface of the source and drain doping layer is increased in the direction (transverse direction) perpendicular to the fin portion, the problem that short circuit is easy to occur between adjacent source and drain doping layers due to the fact that the transverse dimension of the source and drain doping layer is too large is favorably solved.

Thesubstrate 300 provides a process platform for the formation of semiconductor structures. In this embodiment, thesubstrate 300 is a silicon substrate.

Fin 310 is used to provide a conductive channel for the operation of a field effect transistor. In this embodiment, the material of thefin 310 is silicon.

In this embodiment, the semiconductor structure further includes: anisolation layer 320 is disposed on thesubstrate 300 where thefin 310 is exposed, and theisolation layer 320 covers a portion of the sidewall of thefin 310.

Theisolation layer 320 serves as an isolation structure of the semiconductor structure, and is used for isolating adjacent devices. In this embodiment, theisolation layer 320 is made of silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride, silicon oxynitride, or other insulating materials.

Thegate structure 400 is used to control the on and off of the conductive channel when the field effect transistor is operating.

In this embodiment, thegate structure 400 is a metal gate structure. Thegate structure 400 includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) on the gate dielectric layer.

The gate dielectric layer is used to electrically isolate thegate structure 400 from thefin 310. In this embodiment, the gate dielectric layer is made of a high-k dielectric material. Specifically, the material of the gate dielectric layer is HfO₂。

The gate electrode layer is used to enable electrical connection of thegate structure 400 to other interconnect structures or external circuitry. In this embodiment, the gate electrode layer is made of a magnesium-tungsten alloy.

In other embodiments, the gate structure may not be a metal gate structure, and the gate structure may include a gate oxide layer and a gate layer on the gate oxide layer. In this embodiment, the material of the gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the gate electrode layer may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon.

In this embodiment, the semiconductor structure further includes: and asidewall spacer 322 on a sidewall of thegate structure 400. The sidewall spacers 322 are used to protect the sidewalls of thegate structure 400, and thesidewall spacers 322 are also used to define a formation region of the first source-drain doping layer 330.

Theside wall 322 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, boron nitride, and boron carbonitride, and theside wall 322 may have a single-layer structure or a stacked-layer structure. In this embodiment, thesidewall spacers 322 have a single-layer structure, and the material of thesidewall spacers 322 is silicon nitride.

It should be noted that, in this embodiment, for convenience of illustration and description, only thegate structure 400 and thesidewall spacers 322 are illustrated in fig. 15.

The first source-drain doping layer 330 is used for providing a process foundation for forming the second source-drain doping layer 360, and the first source-drain doping layer 330 and the second source-drain doping layer 360 form a source-drain doping layer of the semiconductor structure.

When an NMOS transistor is formed, the first source-drain dopedlayer 330 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions, or Sb ions; when a PMOS transistor is formed, the first source-drain dopedlayer 330 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.

In this embodiment, the first source-drain doping layer 330 has a sigma-shaped structure, that is, the first source-drain doping layer 330 has a diamond structure along an extending direction perpendicular to thefin portion 310. In other embodiments, the shape of the first source-drain doped layer may also be mushroom-shaped, inverted bowl-shaped, or other shapes.

In this embodiment, the top of the first source-drain doping layer 330 is higher than the top of thefin portion 310, so as to provide a process foundation for forming theprotection layer 350, and further enable the second source-drain doping layer 360 to be located on the first source-drain doping layer 330 exposed from theprotection layer 350.

In this embodiment, the top of theprotection layer 350 is higher than the top of thefin portion 310 and lower than the top of the first source draindoping layer 330.

The forming step of the second source/drain doping layer 360 generally includes an epitaxial process, and theprotection layer 350 is used to play a role of a mask in the forming step of the second source/drain doping layer 360, so as to protect a part of the sidewall of the first source/drain doping layer 330 and prevent epitaxial growth on the entire surface of the first source/drain doping layer 330.

In this embodiment, the top of theprotection layer 350 is higher than the top of thefin portion 310, so as to prevent the epitaxial growth based on thefin portion 310 in the step of forming the second source draindoping layer 360.

In this embodiment, the material of theprotection layer 350 is a dielectric material. By selecting a dielectric material, the influence of theprotective layer 350 on the performance of the semiconductor structure can be reduced, and theprotective layer 350 can be remained in the semiconductor structure, thereby facilitating the simplification of process steps and the improvement of process compatibility.

The material of theprotection layer 350 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the material of theprotection layer 350 is the same as that of theinterlayer dielectric layer 370, which is beneficial to improving process compatibility.

Specifically, the material of theprotection layer 350 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming theprotective layer 350.

It should be noted that, along the normal direction of the surface of thesubstrate 300, the distance between the top of theprotection layer 350 and the top of the first source-drain doping layer 330 is not too small or too large. If the distance is too small, the height of the first source-drain doping layer 330 exposed by theprotection layer 350 is correspondingly too small, and the volume of the second source-drain doping layer 360 is also too small, so that the effect of increasing the surface area of the source-drain doping layer is not obvious easily, and the forming difficulty of the second source-drain doping layer 360 is increased easily; if the distance is too large, the risk that thefin portion 310 is exposed by theprotection layer 350 is easily increased, and the second source-drain doping layer 360 is easily formed on the sidewall of the first source-drain doping layer 330, so that the lateral dimension of the source-drain doping layer is easily too large. For this reason, in this embodiment, in the normal direction of the surface of thesubstrate 300, the distance between the top of theprotection layer 350 and the top of the first source-drain doping layer 330 is 1 nm to 3 nm.

In this embodiment, taking the number of the second source-drain dopedlayers 360 as one example, the number of the layers of theprotection layer 350 is only one. In other embodiments, when the number of the second source-drain doping layers is greater than or equal to two, the semiconductor structure may include a plurality of the protection layers.

The material of the second source draindoping layer 360 is the same as that of the first source draindoping layer 330.

The second source/drain doping layer 360 includes an epitaxial layer doped with ions and located on the first source/drain doping layer 330 exposed by theprotection layer 350.

When an NMOS transistor is formed, the second source-drain dopedlayer 360 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions, or Sb ions; when a PMOS transistor is formed, the second source-drain dopedlayer 360 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.

Wherein the epitaxial layer is used as the stress layer.

In this embodiment, the number of the second source-drain dopedlayers 360 is one. In other embodiments, the number of the second source-drain doped layers is not limited to one.

It should be noted that in this embodiment, the top of the second source-drain doping layer 360 is lower than the top of thegate structure 400, so as to provide a process basis for forming theinterlayer dielectric layer 370 and thecontact hole plug 390.

It should be further noted that, along the normal direction of the surface of thesubstrate 300, the distance between the top of the second source-drain doping layer 360 and the top of thegate structure 400 is not too small or too large. If the distance is too small, the height of the top of the second source-drain doping layer 360 is correspondingly larger, and the relative area between the second source-drain doping layer 360 and thegate structure 400 is correspondingly larger, so that the parasitic capacitance between the source-drain doping layer and thegate structure 400 is easily increased, and the forming difficulty of thecontact hole plug 390 is also easily increased; if the distance is too large, the height of the top of the second source-drain dopedlayer 360 is correspondingly small, which easily results in an insignificant effect of increasing the contact surface of the source-drain doped layer. Therefore, in this embodiment, in the normal direction of the surface of thesubstrate 300, the distance between the top of the second source-drain doping layer 360 and the top of thegate structure 400 is 100 to 500 angstroms.

In this embodiment, the second source-drain dopedlayer 360 also has a diamond structure along the extending direction perpendicular to thefin 310. In other embodiments, the second source-drain doped layer may also have other shapes such as a mushroom shape, an inverted bowl shape, and the like.

In this embodiment, the second source-drain doping layer 360 and the first source-drain doping layer 330 are both diamond-shaped along the extending direction perpendicular to thefin portion 310, which is beneficial to further increase the surface area of the source-drain doping layer.

Theinterlayer dielectric layer 370 and theprotection layer 350 constitute a dielectric layer for isolating adjacent devices, and theinterlayer dielectric layer 370 and theprotection layer 350 also provide a process platform for forming thecontact hole plug 390.

Accordingly, the material of theinterlayer dielectric layer 370 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

In this embodiment, the material of theinterlayer dielectric layer 370 is the same as that of theprotection layer 350, and the material of theinterlayer dielectric layer 370 is silicon oxide, which is beneficial to improving process compatibility.

The contact hole plugs 390 are used to electrically connect the source and drain doped layers to other interconnect structures or external circuitry. In this embodiment, thecontact plug 390 is made of tungsten. In other embodiments, the material of the contact hole plug may also be other conductive materials such as cobalt.

In this embodiment, the semiconductor structure further includes: andsilicide layers 380 located between the first source-drain doping layer 330 and thecontact hole plug 390 and between the second source-drain doping layer 360 and thecontact hole plug 390.

Thesilicide layer 380 is used for reducing contact resistance between thecontact hole plug 390 and the first source-drain doping layer 330 and the second source-drain doping layer 360, improving adhesiveness between thecontact hole plug 390 and the first source-drain doping layer 330 and the second source-drain doping layer 360, and further improving contact performance between thecontact hole plug 390 and the source-drain doping layer.

The material of thesilicide layer 380 may be TiSi, NiSi, CoSi, or the like. In this embodiment, the material of thesilicide layer 380 is TiSi.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

Translated fromChinese

1.一种半导体结构的形成方法，其特征在于，包括：1. A method for forming a semiconductor structure, comprising:提供基底，所述基底包括衬底以及凸出于所述衬底的鳍部，所述基底上形成有栅极结构，所述栅极结构横跨所述鳍部且覆盖所述鳍部的部分顶部和部分侧壁；A base is provided, the base includes a substrate and a fin protruding from the substrate, a gate structure is formed on the base, the gate structure spans the fin and covers a portion of the fin top and part of the side walls;在所述栅极结构两侧的鳍部中形成第一源漏掺杂层；forming a first source-drain doped layer in the fins on both sides of the gate structure;在所述第一源漏掺杂层上形成至少一层第二源漏掺杂层，形成所述第二源漏掺杂层的步骤包括：形成位于衬底上且露出第一源漏掺杂层或位于下方第二源漏掺杂层的保护层；在保护层露出的第一源漏掺杂层或位于下方第二源漏掺杂层上形成第二源漏掺杂层；At least one second source-drain doped layer is formed on the first source-drain doped layer, and the step of forming the second source-drain doped layer includes: forming a first source-drain doped layer on the substrate and exposing the first source-drain doped layer layer or a protective layer located on the lower second source and drain doped layer; a second source and drain doped layer is formed on the first source and drain doped layer exposed by the protective layer or on the lower second source and drain doped layer;在所述保护层上形成层间介质层，所述层间介质层覆盖所述第二源漏掺杂层；forming an interlayer dielectric layer on the protective layer, the interlayer dielectric layer covering the second source-drain doped layer;在所述层间介质层和保护层中形成包围所述第一源漏掺杂层和第二源漏掺杂层的接触孔插塞。Contact hole plugs surrounding the first source-drain doped layer and the second source-drain doped layer are formed in the interlayer dielectric layer and the protective layer.2.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述第一源漏掺杂层的步骤包括：刻蚀所述栅极结构两侧的鳍部，在所述栅极结构两侧的鳍部中形成凹槽；在所述凹槽中形成所述第一源漏掺杂层，所述第一源漏掺杂层的顶部高于所述鳍部的顶部。2 . The method for forming a semiconductor structure according to claim 1 , wherein the step of forming the first source-drain doped layer comprises: etching the fins on both sides of the gate structure, and at the gate structure. 3 . A groove is formed in the fins on both sides of the pole structure; the first source and drain doped layer is formed in the groove, and the top of the first source and drain doped layer is higher than the top of the fin.3.如权利要求2所述的半导体结构的形成方法，其特征在于，所述第二源漏掺杂层的数量为一个，形成所述第二源漏掺杂层的步骤包括：在所述栅极结构露出的衬底上形成露出所述第一源漏掺杂层顶部的保护层，所述保护层的顶部高于所述鳍部的顶部且低于所述第一源漏掺杂层的顶部；3 . The method for forming a semiconductor structure according to claim 2 , wherein the number of the second source and drain doped layers is one, and the step of forming the second source and drain doped layers comprises: in the A protective layer exposing the top of the first source and drain doped layer is formed on the substrate exposed by the gate structure, and the top of the protective layer is higher than the top of the fin and lower than the first source and drain doped layer the top of;采用外延工艺，在所述保护层露出的所述第一源漏掺杂层上形成所述外延层，且在形成所述外延层的过程中原位自掺杂离子形成所述第二源漏掺杂层。Using an epitaxial process, the epitaxial layer is formed on the first source-drain doped layer exposed by the protective layer, and the second source-drain doped layer is formed by in-situ self-doping ions during the formation of the epitaxial layer. Miscellaneous layers.4.如权利要求1所述的半导体结构的形成方法，其特征在于，所述保护层的材料为介电材料。4 . The method for forming a semiconductor structure according to claim 1 , wherein the protective layer is made of a dielectric material. 5 .5.如权利要求1所述的半导体结构的形成方法，其特征在于，所述保护层与所述层间介质层的材料相同。5 . The method for forming a semiconductor structure according to claim 1 , wherein the protective layer is made of the same material as the interlayer dielectric layer. 6 .6.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述接触孔插塞的步骤包括：刻蚀所述层间介质层和保护层，形成露出所述第一源漏掺杂层和第二源漏掺杂层的接触孔；形成填充所述接触孔内的接触孔插塞。6 . The method for forming a semiconductor structure according to claim 1 , wherein the step of forming the contact hole plug comprises: etching the interlayer dielectric layer and the protective layer to expose the first source and drain. 7 . contact holes of the doped layer and the second source-drain doped layer; forming contact hole plugs filling the contact holes.7.如权利要求2所述的半导体结构的形成方法，其特征在于，所述凹槽为西格玛形。7. The method for forming a semiconductor structure according to claim 2, wherein the groove is in a sigma shape.8.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一源漏掺杂层或第二源漏掺杂层在沿垂直于鳍部的延伸方向为菱形结构。8 . The method for forming a semiconductor structure according to claim 1 , wherein the first source-drain doped layer or the second source-drain doped layer has a diamond-shaped structure along an extending direction perpendicular to the fin. 9 .9.如权利要求6所述的半导体结构的形成方法，其特征在于，形成所述接触孔后，形成所述接触孔插塞之前，还包括：在所述接触孔露出的第一源漏掺杂层和第二源漏掺杂层表面形成硅化物层。9 . The method for forming a semiconductor structure according to claim 6 , wherein after forming the contact hole and before forming the contact hole plug, the method further comprises: doping the first source and drain exposed in the contact hole. 10 . A silicide layer is formed on the surface of the impurity layer and the second source and drain impurity layer.10.一种半导体结构，其特征在于，包括：10. A semiconductor structure, characterized in that it comprises:衬底；substrate;鳍部，凸出于所述衬底；fins, protruding from the substrate;栅极结构，横跨所述鳍部且覆盖所述鳍部的部分顶部和部分侧壁；a gate structure spanning the fin and covering part of the top and part of the sidewall of the fin;第一源漏掺杂层，位于所述栅极结构两侧的鳍部中；a first source-drain doped layer, located in the fins on both sides of the gate structure;保护层，位于所述衬底上、与第一源漏掺杂层同层且露出所述第一源漏掺杂层顶部；a protective layer, located on the substrate, in the same layer as the first source-drain doped layer and exposing the top of the first source-drain doped layer;位于所述保护层露出的第一源漏掺杂层上的至少一层第二源漏掺杂层；at least one second source and drain doped layer located on the first source and drain doped layer exposed by the protective layer;层间介质层，位于所述保护层上且覆盖所述第二源漏掺杂层；an interlayer dielectric layer located on the protective layer and covering the second source-drain doped layer;接触孔插塞，位于所述层间介质层和保护层中且包围所述第一源漏掺杂层和第二源漏掺杂层。A contact hole plug is located in the interlayer dielectric layer and the protective layer and surrounds the first source-drain doped layer and the second source-drain doped layer.11.如权利要求10所述的半导体结构，其特征在于，所述第一源漏掺杂层的顶部高于所述鳍部的顶部；11. The semiconductor structure of claim 10, wherein a top of the first source-drain doped layer is higher than a top of the fin;所述第二源漏掺杂层的数量为一个；The number of the second source and drain doped layers is one;所述保护层的顶部高于所述鳍部的顶部且低于所述第一源漏掺杂层的顶部；The top of the protective layer is higher than the top of the fin and lower than the top of the first source-drain doped layer;所述第二源漏掺杂层包括位于保护层露出的第一源漏掺杂层上、掺杂有离子的外延层。The second source-drain doped layer includes an epitaxial layer doped with ions on the first source-drain doped layer exposed from the protective layer.12.如权利要求10所述的半导体结构，其特征在于，所述保护层的材料为介电材料。12. The semiconductor structure of claim 10, wherein the protective layer is made of a dielectric material.13.如权利要求10所述的半导体结构，其特征在于，所述保护层与所述层间介质层的材料相同。13. The semiconductor structure of claim 10, wherein the protective layer is made of the same material as the interlayer dielectric layer.14.如权利要求10所述的半导体结构，其特征在于，所述保护层的材料包括氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅或碳氮氧化硅。14. The semiconductor structure of claim 10, wherein a material of the protective layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or silicon oxycarbonitride.15.如权利要求10所述的半导体结构，其特征在于，所述半导体结构还包括：硅化物层，位于所述第一源漏掺杂层与所述接触孔插塞之间、以及所述第二源漏掺杂层与所述接触孔插塞之间。15. The semiconductor structure of claim 10, further comprising: a silicide layer between the first source-drain doped layer and the contact hole plug, and the between the second source-drain doped layer and the contact hole plug.16.如权利要求11所述的半导体结构，其特征在于，沿所述衬底表面的法线方向上，所述保护层顶部与所述第一源漏掺杂层顶部之间的距离为1纳米至3纳米。16 . The semiconductor structure of claim 11 , wherein, along the normal direction of the substrate surface, the distance between the top of the protective layer and the top of the first source-drain doped layer is 1 . nanometer to 3 nanometers.17.如权利要求10所述的半导体结构，其特征在于，沿所述衬底表面的法线方向上，所述第二源漏掺杂层顶部低于所述栅极结构的顶部，且所述第二源漏掺杂层顶部与所述栅极结构顶部之间的距离为100埃米至500埃米。17 . The semiconductor structure of claim 10 , wherein, along the normal direction of the substrate surface, the top of the second source-drain doped layer is lower than the top of the gate structure, and the The distance between the top of the second source-drain doping layer and the top of the gate structure is 100 angstroms to 500 angstroms.18.如权利要求10所述的半导体结构，其特征在于，所述第一源漏掺杂层或第二源漏掺杂层在沿垂直于鳍部的延伸方向为菱形结构。18 . The semiconductor structure of claim 10 , wherein the first source-drain doped layer or the second source-drain doped layer has a diamond-shaped structure along an extending direction perpendicular to the fin portion. 19 .

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