CN112305794A - Display panel - Google Patents

Abstract

The invention discloses a display panel, which comprises a display area and a peripheral area, wherein the peripheral area is arranged on at least one side of the display area, and the display panel comprises a substrate, a first conducting layer, a second conducting layer and a third conducting layer. The first conductive layer, the second conductive layer and the third conductive layer are arranged on the substrate, the first conductive layer comprises a first wire, the second conductive layer comprises a second wire, and the third conductive layer comprises a third wire. The first routing line, the second routing line and the third routing line are arranged in the peripheral area. The first trace, the second trace, and the third trace are electrically insulated from each other. At least two of the first routing lines, the second routing lines and the third routing lines are partially overlapped in the peripheral area.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel with a narrow bezel design.

Background

The display panel is composed of two substrates, a plurality of film layers arranged between the two substrates and various electronic components, so as to achieve the function of displaying pictures. Because the display panel has the characteristics of being light and thin, low in power consumption, and free from radiation pollution, the display panel has been widely applied to various portable or wearable electronic products, such as notebook computers (notebook), smart phones (smart phones), watches, and vehicle displays, to provide more convenient information transmission and display.

In the non-display area of the conventional display panel, due to the limitation of the manufacturing process, the reduction of the width of the lower frame of the display panel is limited. Therefore, how to effectively continue to reduce the width of the lower frame of the display panel to meet the design of the narrow frame of the display panel is a technical problem to be solved at present.

Disclosure of Invention

The invention aims to solve the technical problem that in the prior art, the lower frame of a display panel cannot be further reduced due to the limit of a manufacturing process.

In order to solve the above technical problem, the present invention provides a display panel, which includes a display area and a peripheral area, wherein the peripheral area is disposed on at least one side of the display area, and the display panel includes a substrate, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is arranged on the substrate and comprises a first routing line arranged in the peripheral area. The second conductive layer is arranged on the substrate and comprises a second routing line arranged in the peripheral area. The third conductive layer is disposed on the substrate and includes a third trace disposed in the peripheral region. The first wire, the second wire and the third wire are electrically insulated from each other, and at least two of the first wire, the second wire and the third wire are partially overlapped in the peripheral region.

In order to solve the above technical problem, the present invention provides a display panel, which includes a display area and a peripheral area, wherein the peripheral area is disposed on at least one side of the display area, and the display panel includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first conductive layer is arranged on the substrate and comprises a first routing line arranged in the peripheral area. The second conductive layer is arranged on the substrate and comprises a second routing line arranged in the peripheral area. The third conductive layer is disposed on the substrate and includes a third trace disposed in the peripheral region. The fourth conducting layer is arranged on the substrate and comprises a fourth routing line arranged in the peripheral area. The first wire, the second wire, the third wire and the fourth wire are electrically insulated from each other, and at least two of the first wire, the second wire, the third wire and the fourth wire are partially overlapped in the peripheral region.

In the display panel of the invention, the routing lines arranged in the peripheral area and used for electrically connecting the data lines can be formed by three or four different conductive layers, and because the routing lines belong to different layers, the adjacent routing lines can be partially overlapped with each other in the peripheral area to reduce the area occupied by the routing lines, thereby reducing the width of the lower frame of the display panel.

Drawings

Fig. 1 is a schematic top view of a display panel according to a first embodiment of the invention.

Fig. 2 is a partially enlarged schematic view of a peripheral region of a display panel according to a first embodiment of the invention.

FIG. 3 is a schematic cross-sectional view of the wire-changing structure along the cutting lines A-A 'and B-B' in FIG. 2.

Fig. 4 is a partially enlarged schematic view of a peripheral region of a display panel according to a second embodiment of the invention.

Fig. 5 is a partially enlarged schematic view of a peripheral region of a display panel according to a third embodiment of the invention.

FIG. 6 is a cross-sectional view of the wire-changing structure along the tangent lines A-A ', B-B ' and C-C ' in FIG. 5.

Fig. 7 is a partially enlarged schematic view of a peripheral region of a display panel according to a fourth embodiment of the invention.

Fig. 8 is a partially enlarged schematic view of a peripheral region of a display panel according to a fifth embodiment of the invention.

Wherein the reference numerals are as follows:

10 display panel

100 substrate

102 scan line

104 data line

1051-1056, 134, 136 wire

106 driving circuit chip

108 first joining region

110 second bonding area

112 first conductive layer

114 second conductive layer

116 third conductive layer

118. 120, 140 trade line structure

122 first insulating layer

124 second insulating layer

126 third insulating layer

128 first transparent conductive layer

1301. 1302, 1303 bridge electrode

138 fourth conductive layer

142 fourth insulating layer

BP1 first conductive connection pad

BP2 second conductive connection pad

BP3 third conductive connection pad

D1 first direction

D2 second direction

Third direction D3

D4 fourth direction

DR display area

DS1, DS2, DS distance

PR peripheral zone

First part of R1

Second part of R2

Re, 132, 133 region

SP sub-pixel

SW switch element

Ta and Tb wiring

Ta1 first trace

Ta1_1, Ta2_1, Ta3_1 and Ta4_1 parts

Ta2 second trace

Ta3 third trace

Ta4 fourth trace

TH1_1, TH1_2 first connection hole

TH2_1 and TH2_2 second connecting holes

TH3_1 and TH3_2 third connecting holes

TP1 and TP2 test contact pads

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, preferred embodiments of the present invention are specifically described below, and the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the drawings are simplified schematic diagrams, and therefore, only the components and combinations related to the present invention are shown to provide a clearer description of the basic architecture or implementation method of the present invention, and the actual components and layout may be more complicated. In addition, for convenience of description, the components shown in the drawings are not necessarily drawn to scale, and the actual implementation numbers, shapes and sizes may be adjusted according to design requirements.

Referring to fig. 1 to 3, fig. 1 is a top view of a display panel according to a first embodiment of the invention, fig. 2 is a partially enlarged view of a peripheral region of the display panel according to the first embodiment of the invention, and fig. 3 is a cross-sectional view of the line-changing structure in fig. 2. As shown in fig. 1, thedisplay panel 10 of the present embodiment is a liquid crystal display panel, but not limited thereto. Thedisplay panel 10 of the present invention may be any other suitable type of display panel. As shown in fig. 1, thedisplay panel 10 includes asubstrate 100. Thesubstrate 100 has a display region DR and a peripheral region PR disposed at least one side outside the display region DR. In the present embodiment, the peripheral region PR surrounds the display region DR, but is not limited thereto. Thesubstrate 100 may be a hard substrate such as a glass substrate, a plastic substrate, a quartz substrate, or a sapphire substrate, and may also be a flexible substrate including a Polyimide (PI) material or a polyethylene terephthalate (PET) material, for example, but not limited thereto. Thedisplay panel 10 includes a plurality ofscan lines 102 and a plurality ofdata lines 104, thescan lines 102 may extend along a first direction D1, thedata lines 104 may extend along a second direction D2 and are not parallel to the first direction D1, and thescan lines 102 and thedata lines 104 alternately define a plurality of sub-pixels SP, but not limited thereto. The first direction D1 and the second direction D2 are perpendicular, but not limited thereto.

Thedisplay panel 10 of the embodiment includes a driving circuit chip (IC) 106 disposed on thesubstrate 100 in the peripheral region PR. In addition, thedisplay panel 10 further includes a plurality of first conductive connection pads BP1, a plurality of second conductive connection pads BP2, and a plurality of third conductive connection pads BP3 disposed on thesubstrate 100 and located in the peripheral region PR. Thesubstrate 100 has afirst bonding region 108 and asecond bonding region 110 disposed in the peripheral region PR, thefirst bonding region 108 may be disposed between the display region DR and thesecond bonding region 110 in the second direction D2, the drivingcircuit chip 106, the first conductive connection pad BP1 and the second conductive connection pad BP2 may be disposed in thefirst bonding region 108, and the third conductive connection pad BP3 may be disposed in thesecond bonding region 110. Thedisplay panel 10 further includes a plurality of traces Ta and a plurality of traces Tb disposed in the peripheral region PR, and a conductive line (e.g., the data line 104) in the display region DR may be electrically connected to the traces Ta and may extend to thefirst bonding region 108 in the peripheral region PR through the traces Ta, so that thedata line 104 is electrically connected to the first conductive connecting pad BP 1. The design of the trace Ta will be described in detail below. In addition, the first conductive pad BP1 and the second conductive pad BP2 can be electrically connected to thedriving circuit chip 106, the second conductive pad BP2 can be electrically connected to the third conductive pad BP3 by the trace Tb, and the third conductive pad BP3 can be electrically connected to a flexible circuit board (not shown).

In the present embodiment, the drivingcircuit chip 106 may include a source driving circuit, and the drivingcircuit chip 106 may be disposed on thesubstrate 100 in a chip form or in an sog (system on glass) manner, but not limited thereto. In an embodiment in which thedriving circuit chip 106 is a chip and disposed on thesubstrate 100, the drivingcircuit chip 106 may include a plurality of pads, and at least some of the pads are respectively located corresponding to and electrically connected to the first conductive connection pad BP1 and the second conductive connection pad BP 2. In an alternative embodiment, the drivingcircuit chip 106 may be disposed on a flexible or rigid circuit board in a chip form and then electrically connected to the plurality of conductive pads on thesubstrate 100. In the present embodiment, the first conductive bonding pad BP1 may be, for example, an IC output bonding pad, and the second conductive bonding pad BP2 may be, for example, an IC input bonding pad, but not limited thereto. For example, the flexible circuit board can provide signals to thedriving circuit chip 106 through the third conductive pad BP3, the trace Tb, and the second conductive pad BP 2. On the other hand, the drivingcircuit chip 106 can transmit the image gray scale signal to thedata line 104 through the first conductive connection pad BP1 and the trace Ta, but not limited thereto.

Referring to fig. 2, fig. 2 is an enlarged view of the region Re in fig. 1, wherein six conductive lines 1051-1056 are disposed along the second direction D2 extending from the display region DR to the peripheral region PR and are disposed side by side along the first direction D1. The conductive lines 1051-1056 may be, for example, a plurality ofdata lines 104, and may be electrically connected to the sub-pixels SP corresponding to different colors, respectively, but not limited thereto. On the other hand, in fig. 2, the two first routing lines Ta1, the two second routing lines Ta2, and the two third routing lines Ta3 are also disposed in the peripheral region PR, and the arrangement of the first routing lines Ta1, the second routing lines Ta2, and the third routing lines Ta3 along the first direction D1 may be, but is not limited to, one first routing line Ta1, one second routing line Ta2, one third routing line Ta3, and one first routing line Ta1 … in sequence. Thewires 1051 and 1054 are electrically connected to a first trace Ta1, thewires 1052 and 1055 are electrically connected to a second trace Ta2, and thewires 1053 and 1056 are electrically connected to a third trace Ta3, but not limited thereto. Thewires 1051 and 1056 are electrically insulated from each other, and the first trace Ta1, the second trace Ta2 and the third trace Ta3 are electrically insulated from each other. In addition, the first trace Ta1, the second trace Ta2, and the third trace Ta3 may be electrically connected to thedriving circuit chip 106 in fig. 1.

In this embodiment, thedisplay panel 10 may include a firstconductive layer 112, a secondconductive layer 114 and a thirdconductive layer 116, wherein the firstconductive layer 112 may include one or more first traces Ta1, the secondconductive layer 114 may include one or more second traces Ta2 andwires 1051 and 1056 (e.g., the data line 104), and the thirdconductive layer 116 may include one or more third traces Ta3, but not limited thereto. In other embodiments, the conductive lines 1051-1056 can also be formed by the firstconductive layer 112, the thirdconductive layer 116, or other conductive layers. In the present embodiment, the secondconductive layer 114 may be disposed on the firstconductive layer 112 and the thirdconductive layer 116 may be disposed on the secondconductive layer 114 in a third direction D3 perpendicular to the surface of thesubstrate 100, but not limited thereto.

In the embodiment, since theconductive lines 1051 and 1054 and the first trace Ta1 belong to different conductive layers, and theconductive lines 1053 and 1056 and the third trace Ta3 also belong to different conductive layers, thedisplay panel 10 may include one or more line switching structures disposed in the peripheral region PR, and the conductive lines may be electrically connected to the first trace Ta1 or the third trace Ta3 in the peripheral region PR through the line switching structures. As shown in fig. 2, theconductive wires 1051 and 1054 can be respectively electrically connected to the corresponding first traces Ta1 through the wire-changingstructure 118, and theconductive wires 1053 and 1056 can be respectively electrically connected to the corresponding third traces Ta3 through the wire-changingstructure 120. Theline changing structures 118, 120 are used to electrically connect different conductive layers, the detailed features of which are described in more detail below. In addition, since theconductive lines 1052 and 1055 and the second trace Ta2 of the present embodiment are formed by the same conductive layer, theconductive lines 1052 and 1055 can be electrically connected to the corresponding second trace Ta2 without the need of a line-changing structure, but not limited thereto. In some embodiments, theconductive wires 1052 and 1055 can also be electrically connected to the corresponding second trace Ta2 by a wire-changing structure.

Since the first routing line Ta1, the second routing line Ta2, and the third routing line Ta3 all belong to different layers, at least two of the first routing line Ta1, the second routing line Ta2, and the third routing line Ta3 may partially overlap in the peripheral region PR. Taking the first routing line Ta1, the second routing line Ta2, and the third routing line Ta3 electrically connected to thewires 1051 and 1053 in fig. 2 as an example, the second routing line Ta2 and the third routing line Ta3 may be bent and extend to the first routing line Ta1 toward the first routing line Ta1, and continue to extend along the first routing line Ta1 below, so that the second routing line Ta2 and the third routing line Ta3 may partially overlap with the first routing line Ta1 to reduce the area occupied by the routing lines in the peripheral region PR. A portion Ta1_1 of the first trace Ta1, a portion Ta2_1 of the second trace Ta2, and a portion Ta3_1 of the third trace Ta3 extend in parallel and overlap with each other, a portion Ta1_1 of the first trace Ta1, a portion Ta2_1 of the second trace Ta2, and a portion Ta3_1 of the third trace Ta3 may extend along a fourth direction D4, and the fourth direction D4 may be nonparallel to the first direction D1 and the second direction D2. The portion Ta1_1 of the first trace Ta1, the portion Ta2_1 of the second trace Ta2, and the portion Ta3_1 of the third trace Ta3 may also be referred to as oblique wiring portions. In addition, the first trace Ta1, the second trace Ta2, and the third trace Ta3 of theelectrical connection wire 1054 and 1056 may also have the same features as above, and are not described again.

As shown in fig. 2, in the present embodiment, the minimum distance between two adjacent traces formed by the same conductive layer may be a distance P1 (also referred to as a pitch). Taking the first trace Ta1 electrically connected to thewire 1051 and the first trace Ta1 electrically connected to thewire 1054 as an example, the distance P1 between the portion Ta1_1 of the two adjacent first traces Ta1 may include the width of one first trace Ta1 and the distance between two adjacent first traces Ta1 (not including the width of the first trace Ta 1), and the distance P1 may be the shortest distance allowed by the process technology. In some embodiments, the traces are formed by only two conductive layers and are arranged alternately, in other words, thewires 1051 and 1053 can be electrically connected to the first trace Ta1 formed by the firstconductive layer 112, and thewires 1052 and 1054 can be electrically connected to the second trace Ta2 formed by the secondconductive layer 114. In this case, the distance between the first trace Ta1 of theelectrical connection wire 1051 and the oblique wiring portion of the second trace Ta2 of theelectrical connection wire 1054 is at least 1.5 times the distance P1. In the present embodiment, the area occupied by the traces in the peripheral region PR can be reduced by using the trace layout method. For example, compared to the embodiment in which the trace is formed by only two conductive layers alternately, the distance P1 can be reduced to 1 time P1 in this embodiment, and the distance DS1 (shown in fig. 1) from the edge of the display region DR to the edge of the drivingcircuit chip 106 can be reduced by about 34%. In addition, in the present embodiment, the two adjacent portions Ta2_1 of the second trace Ta2 of theelectrical connection wire 1052 and the second trace Ta2 of theelectrical connection wire 1055 may have the same characteristics as above, and the two adjacent portions Ta3_1 of the third trace Ta3 of theelectrical connection wire 1053 and the third trace Ta3 of theelectrical connection wire 1056 may also have the same characteristics as above. By reducing the distance DS1, the width of the bottom frame of thedisplay panel 10 can be further reduced.

As shown in fig. 3, the firstconductive layer 112 is disposed on thesubstrate 100, a first insulatinglayer 122 is disposed on the firstconductive layer 112, and the first insulatinglayer 122 may be, for example, a gate insulating layer, but not limited thereto. The secondconductive layer 114 is disposed on the first insulatinglayer 122, and a second insulatinglayer 124 is disposed on the secondconductive layer 114. The thirdconductive layer 116 is disposed on the second insulatinglayer 124, a thirdinsulating layer 126 is disposed on the thirdconductive layer 116, and a first transparentconductive layer 128 is disposed on the third insulatinglayer 126. Theline changing structure 118 may include a contact pad of the firstconductive layer 112, a contact pad of the secondconductive layer 114, at least two first connection holes TH1_1 and TH1_2 corresponding to the contact pads, and abridge electrode 1301. The contact pad of the secondconductive layer 114 may be located at one end of thewire 1051 or thewire 1054, and the contact pad of the firstconductive layer 112 may be located at one end of the first trace Ta 1. A first connection hole TH1_1 is disposed in the second and third insulatinglayers 124 and 126 between thebridge electrode 1301 and the secondconductive layer 114 and exposes a portion of the contact pad of the secondconductive layer 114, and another first connection hole TH1_2 is disposed in the first, second and third insulatinglayers 122, 124 and 126 between thebridge electrode 1301 and the firstconductive layer 112 and exposes a portion of the contact pad of the firstconductive layer 112. Thebridge electrode 1301 is filled in the first connection holes TH1_1 and TH1_2 and contacts the contact pads of the firstconductive layer 112 and the secondconductive layer 114 exposed by the first connection holes TH1_1 and TH1_2, that is, the firstconductive layer 112 and the secondconductive layer 114 are electrically connected to each other through thebridge electrode 1301.

In addition, theline changing structure 120 may include a contact pad of the secondconductive layer 114, a contact pad of the thirdconductive layer 116, at least two second connection holes TH2_1 and TH2_2 corresponding to the contact pads, and abridge electrode 1302. The contact pad of the secondconductive layer 114 may be located at one end of thewire 1053 or thewire 1056, and the contact pad of the thirdconductive layer 116 may be located at one end of the third trace Ta 3. A second connection hole TH2_1 is disposed in the second insulatinglayer 124 and the third insulatinglayer 126 between thebridge electrode 1302 and the secondconductive layer 114 and exposes a portion of the contact pad of the secondconductive layer 114, and another second connection hole TH2_2 is disposed in the third insulatinglayer 126 between thebridge electrode 1302 and the thirdconductive layer 116 and exposes a portion of the contact pad of the thirdconductive layer 116. Thebridge electrode 1302 is filled in the second connection holes TH2_1 and TH2_2 and contacts the contact pad of the secondconductive layer 114 and the contact pad of the thirdconductive layer 116 exposed by the second connection holes TH2_1 and TH2_2, that is, the secondconductive layer 114 and the thirdconductive layer 116 are electrically connected to each other through thebridge electrode 1302.

In the present embodiment, the firstconductive layer 112, the secondconductive layer 114 and the thirdconductive layer 116 may be metal layers, for example. The first insulatinglayer 122, the second insulatinglayer 124, and the third insulatinglayer 126 may be, for example, silicon oxide, silicon nitride, or silicon oxynitride, but not limited thereto. The first transparentconductive layer 128 may include a transparent conductive material such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or Aluminum Zinc Oxide (AZO), but is not limited thereto. In addition, thedisplay panel 10 may further include a fourth insulating layer and a second transparent conductive layer, the fourth insulating layer may be disposed on the first transparentconductive layer 128, and the second transparent conductive layer may be disposed on the fourth insulating layer. In the present embodiment, the first transparentconductive layer 128 may include a plurality of common electrodes, and the second transparent conductive layer may include a plurality of pixel electrodes, but not limited thereto. In other embodiments, the first transparentconductive layer 128 may include a plurality of pixel electrodes, and the second transparent conductive layer may include a plurality of common electrodes.

Referring to fig. 1 again, the peripheral region PR of thedisplay panel 10 may include a first portion R1 and a second portion R2 respectively disposed on two opposite sides of the display region DR in the second direction D2. Thedisplay panel 10 may further include a plurality of test contact pads TP1, TP2 and a plurality of switching elements SW, the test contact pads TP1, TP2 may be disposed in aregion 132 of the first portion R1, the drivingcircuit chip 106 may be disposed in thefirst bonding region 108 of the first portion R1, and the switching elements SW may be disposed in aregion 133 of the second portion R2. In other words, the switching element SW is disposed between the upper edge of thesubstrate 100 and the upper edge of the display region DR, and the test contact pads TP1, TP2 and the drivingcircuit chip 106 are disposed between the lower edge of thesubstrate 100 and the lower edge of the display region DR, but not limited thereto. One end of the switching element SW may be electrically connected to the test contact pad TP1 through theconductive line 134, and thedata line 104 may extend from the upper edge of the display region DR to theregion 133 of the second portion R2 of the peripheral region PR and be electrically connected to the other end of the switching element SW. Accordingly, a test signal may be input from the test contact pad TP1 and transmitted to the correspondingdata line 104 and the sub-pixel SP through the switching element SW. In other words, thedata line 104 of the present embodiment may extend beyond two opposite edges (upper edge and lower edge) of the display region DR along the second direction D2 into the peripheral region PR, such that one end of thedata line 104 is electrically connected to the first conductive pad BP1 and the other end is electrically connected to the switch element SW. On the other hand, thescan line 102 can be electrically connected to the test contact pad TP2 through aconducting wire 136. Accordingly, a test signal may be input from the test contact pad TP2 and transmitted to thecorresponding scan line 102 and sub-pixel SP. Therefore, whether thedisplay panel 10 is abnormal or not can be tested through the test contact pads TP1 and TP 2.

In some embodiments, the switching element SW for testing is disposed in the first portion R1 of the peripheral region PR and between the first conductive connection pad BP1 and the second conductive connection pad BP2, and since the drivingcircuit chip 106 is electrically connected to the first conductive connection pad BP1 and the second conductive connection pad BP2, the distance DS2 required by the side of the drivingcircuit chip 106 is larger. However, in the present embodiment, the switch element SW for testing is disposed in the second portion R2 of the peripheral region PR, so that the distance between the first conductive pad BP1 and the second conductive pad BP2 can be reduced, and the distance DS2 required by the side of the drivingcircuit chip 106 can be reduced to reduce the width of the lower frame of thedisplay panel 10. For example, the distance DS2 occupied by the drivingcircuit chip 106 can be reduced by about 0.3 mm (micrometer), but not limited thereto.

For example, in some embodiments, the switching element SW for testing is disposed in the first portion R1 of the peripheral region PR, and the traces are formed by only two conductive layers alternately. At this time, the width of the lower frame of thedisplay panel 10 may be represented by a distance DS in fig. 1, which may be about 4 mm, and wherein the distance DS1 from the edge of the display region DR to the edge of the drivingcircuit chip 106 may be about 2.15 mm. According to the design of the present embodiment, the distance DS1 can be reduced by about 34% and the distance DS2 can be reduced by about 0.3 mm, in other words, the distance DS of the lower frame of thedisplay panel 10 of the present embodiment can be reduced to 4.00-2.15 × 34% -0.30 — 2.97 mm, but not limited thereto. In some embodiments, the design of forming the trace with three metal layers may be adopted instead of the design of moving up the switch element SW for test, and the distance DS between the lower frames of thedisplay panel 10 may be reduced to 4.00-2.15 × 34% to 3.27 mm, but not limited thereto.

The display panel of the present invention is not limited to the above embodiments. While other embodiments and variations of the present invention will be described below, the same components will be denoted by the same reference numerals and the repeated description thereof will not be repeated in order to simplify the description and to highlight the differences between the embodiments and variations.

Please refer to fig. 4, which is a partially enlarged view of a peripheral region of a display panel according to a second embodiment of the present invention, and fig. 4 is an enlarged view of a region Re in fig. 1. Unlike the first embodiment, the third trace Ta3 of the present embodiment does not bend and extend toward the first trace Ta1, but extends downward from thewire changing structure 120 along the second direction D2, and after bending, extends in parallel to the portion Ta2_1 of the second trace Ta2 (and/or the portion Ta1_1 of the first trace Ta 1), so that the third trace Ta3 of theelectrical connection wire 1053 is disposed between the second trace Ta2 of theelectrical connection wire 1052 and the first trace Ta1 of theelectrical connection wire 1054. Therefore, in the present embodiment, the portion Ta1_1 of the first trace Ta1 and the portion Ta2_1 of the second trace Ta2 extend in parallel and overlap with each other, and the portion Ta3_1 of the third trace Ta3 and the portion Ta2_1 of the second trace Ta2 (and/or the portion Ta1_1 of the first trace Ta 1) extend in parallel and do not overlap with each other. On the other hand, as in the first embodiment, compared to the embodiment in which the traces are formed by only two conductive layers alternately, the distance DS1 (shown in fig. 1) from the edge of the display region DR to the edge of the drivingcircuit chip 106 can be reduced by about 34% in this embodiment.

Referring to fig. 5 and fig. 6, fig. 5 is a partially enlarged schematic view of a peripheral region of a display panel according to a third embodiment of the invention, in which fig. 5 is an enlarged schematic view of a region Re in fig. 1, and fig. 6 is a schematic cross-sectional view of a line-changing structure along tangent lines a-a ', B-B ', and C-C ' in fig. 5. As shown in fig. 5, different from the first embodiment, thedisplay panel 10 of the present embodiment further includes a fourthconductive layer 138 disposed on thesubstrate 100, the fourthconductive layer 138 may be disposed on the thirdconductive layer 116, and the fourthconductive layer 138 may include one or more fourth routing lines Ta4 disposed in the peripheral region PR. The first routing line Ta1, the second routing line Ta2, the third routing line Ta3, and the fourth routing line Ta4 may be sequentially a first routing line Ta1, a second routing line Ta2, a third routing line Ta3, a fourth routing line Ta4, and a first routing line Ta1 … along the first direction D1, but not limited thereto. As shown in fig. 5, in the present embodiment, thewires 1051 and 1055 are electrically connected to a first trace Ta1, thewires 1052 and 1056 are electrically connected to a second trace Ta2, thewire 1053 is electrically connected to a third trace Ta3, and thewire 1054 is electrically connected to a fourth trace Ta4, but not limited thereto. The first trace Ta1, the second trace Ta2, the third trace Ta3, and the fourth trace Ta4 are electrically insulated from each other, and the fourth trace Ta4 may be electrically connected to thedriving circuit chip 106 in fig. 1.

Since the first routing line Ta1, the second routing line Ta2, the third routing line Ta3, and the fourth routing line Ta4 all belong to different layers, at least two of the first routing line Ta1, the second routing line Ta2, the third routing line Ta3, and the fourth routing line Ta4 may partially overlap in the peripheral region PR. Taking the first trace Ta1, the second trace Ta2, the third trace Ta3 and the fourth trace Ta4 electrically connected to thewires 1051 and 1054 in fig. 5 as an example, the second trace Ta2, the third trace Ta3 and the fourth trace Ta4 may be bent and extend onto the first trace Ta1 toward the first trace Ta1, and continue to extend along the first trace Ta1 below, so that the second trace Ta2, the third trace Ta3 and the fourth trace Ta4 may partially overlap with the first trace Ta1, so as to reduce the area occupied by the traces in the peripheral region PR. A portion Ta1_1 of the first trace Ta1, a portion Ta2_1 of the second trace Ta2, a portion Ta3_1 of the third trace Ta3, and a portion Ta4_1 of the fourth trace Ta4 extend in parallel and overlap with each other, and a portion Ta1_1 of the first trace Ta1, a portion Ta2_1 of the second trace Ta2, a portion Ta3_1 of the third trace Ta3, and a portion Ta4_1 of the fourth trace Ta4 may extend along the fourth direction D4. In addition, the first trace Ta1 and the second trace Ta2 of theelectrical connection wires 1055 and 1056 may also have the same features as above, and are not described again.

Taking the first trace Ta1 of theelectrical connection wire 1051 and the first trace Ta1 of theelectrical connection wire 1055 as an example, the distance between the portions Ta1_1 of the two adjacent first traces Ta1 may be the minimum distance P1 between the two adjacent traces formed by the same conductive layer. In some embodiments, the traces are formed by only two conductive layers and are arranged alternately, in other words, thewires 1051, 1053 and 1055 can be electrically connected to the first trace Ta1 formed by the firstconductive layer 112, and thewires 1052, 1054 and 1056 can be electrically connected to the second trace Ta2 formed by the secondconductive layer 114. In this case, the distance between the first trace Ta1 of theelectrical connection wire 1051 and the oblique wiring portion of the first trace Ta1 of theelectrical connection wire 1055 is at least 2 times the distance P1. Therefore, the area occupied by the traces in the peripheral region PR can be reduced by using the trace configuration method of the present embodiment. For example, compared to the embodiment in which the trace is formed by only two conductive layers alternately, the distance P1 can be reduced from 2 times P1 in the embodiment to 1 time P1, and the distance DS1 (shown in fig. 1) from the edge of the display region DR to the edge of the drivingcircuit chip 106 can be reduced by about 50%. In addition, the two adjacent portions Ta2_1 of the second trace Ta2 of theelectrical connection wire 1052 and the second trace Ta2 of theelectrical connection wire 1056 in the present embodiment can also have the same features as above. By reducing the distance DS1, the width of the bottom frame of thedisplay panel 10 can be further reduced.

For example, in some embodiments, the traces are formed by only two conductive layers alternately, and the switching element SW for testing is disposed in the first portion R1 of the peripheral region PR. At this time, the width (i.e., the distance DS) of the lower frame of thedisplay panel 10 may be about 4 mm, and the distance DS1 from the edge of the display region DR to the edge of the drivingcircuit chip 106 may be about 2.15 mm. According to the design of the present embodiment, the distance DS1 can be reduced by about 50%, and the distance DS2 can be reduced by about 0.3 mm by using the design of moving the switch element SW upward for testing, in other words, the distance DS of the lower frame of thedisplay panel 10 can be reduced to 4.00-2.15 × 50% -0.30, which is 2.63 mm, but not limited thereto. In some embodiments, the design of the trace formed by four metal layers may be adopted instead of the design of the switch element SW for test moving upward, and the distance DS between the lower frames of thedisplay panel 10 may be reduced to 4.00-2.15 × 50% to 2.93 mm, but not limited thereto.

In addition, since theconductive line 1054 and the fourth trace Ta4 belong to different conductive layers, theconductive line 1054 can be electrically connected to the corresponding fourth trace Ta4 through aline changing structure 140. As shown in fig. 6, the fourthconductive layer 138 is disposed on the third insulatinglayer 126, a fourth insulatinglayer 142 is disposed on the fourthconductive layer 138, and the first transparentconductive layer 128 is disposed on the fourth insulatinglayer 142. Theline changing structure 140 may include a contact pad of the fourthconductive layer 138, a contact pad of the secondconductive layer 114, at least two third connection holes TH3_1 and TH3_2 corresponding to the contact pads, and abridge electrode 1303. The contact pad of the secondconductive layer 114 may be located at one end of theconductive line 1054, and the contact pad of the fourthconductive layer 138 may be located at one end of the fourth trace Ta 4. A third connection hole TH3_1 is disposed in the second insulatinglayer 124, the third insulatinglayer 126, and the fourth insulatinglayer 142 between thebridge electrode 1303 and the secondconductive layer 114 and exposes a portion of the contact pad of the secondconductive layer 114, and another third connection hole TH3_2 is disposed in the fourth insulatinglayer 142 between thebridge electrode 1303 and the fourthconductive layer 138 and exposes a portion of the contact pad of the fourthconductive layer 138. Thebridge electrode 1303 is filled in the third connection holes TH3_1 and TH3_2 and contacts the contact pad of the secondconductive layer 114 and the contact pad of the fourthconductive layer 138 exposed by the third connection holes TH3_1 and TH3_2, that is, the secondconductive layer 114 and the fourthconductive layer 138 are electrically connected to each other through thebridge electrode 1303.

Please refer to fig. 7, which is a partially enlarged view of a peripheral region of a display panel according to a fourth embodiment of the disclosure, and fig. 7 is an enlarged view of a region Re in fig. 1. Unlike the third embodiment, the fourth trace Ta4 of the present embodiment does not overlap with the first trace Ta1, the second trace Ta2 and the third trace Ta3, and as shown in fig. 7, the fourth trace Ta4 of theelectrical connection wire 1054 is disposed between the third trace Ta3 of theelectrical connection wire 1053 and the first trace Ta1 of theelectrical connection wire 1055. In addition, in the present embodiment, a portion Ta1_1 of the first trace Ta1, a portion Ta2_1 of the second trace Ta2, and a portion Ta3_1 of the third trace Ta3 extend in parallel and overlap with each other, and a portion Ta4_1 of the fourth trace Ta4 and a portion Ta1_1 of the first trace Ta1 extend in parallel and do not overlap with each other. On the other hand, as in the third embodiment, compared to the embodiment in which the traces are formed by only two conductive layers alternately, the distance DS1 (shown in fig. 1) from the edge of the display region DR to the edge of the drivingcircuit chip 106 can be reduced by about 50% in this embodiment.

Please refer to fig. 8, which is a partially enlarged view of a peripheral region of a display panel according to a fifth embodiment of the present invention, and fig. 8 is an enlarged view of a region Re in fig. 1. Different from the third embodiment, in the present embodiment, thewire 1052 and thewire 1056 are electrically connected to a third trace Ta3 respectively, and thewire 1053 is electrically connected to a second trace Ta2, so the arrangement of the first trace Ta1, the second trace Ta2, the third trace Ta3 and the fourth trace Ta4 in the first direction D1 may be a first trace Ta1, a third trace Ta3, a second trace Ta2, a fourth trace Ta4 and a first trace Ta1 … in sequence, but not limited thereto. In this embodiment, one first trace Ta1 and one corresponding third trace Ta3 partially overlap, one second trace Ta2 and one corresponding fourth trace Ta4 partially overlap, and the first trace Ta1 and the third trace Ta3 and the second trace Ta2 and the fourth trace Ta4 do not overlap with each other.

In detail, a portion Ta1_1 of the first trace Ta1 and a portion Ta3_1 of the third trace Ta3 extend in parallel and overlap with each other, a portion Ta2_1 of the second trace Ta2 and a portion Ta4_1 of the fourth trace Ta4 extend in parallel and overlap with each other, and a portion Ta1_1 of the first trace Ta1 and a portion Ta3_1 of the third trace Ta3 extend in parallel and do not overlap with each other, and a portion Ta2_1 of the second trace Ta2 and a portion Ta4_1 of the fourth trace Ta4 extend in parallel and do not overlap with each other. On the other hand, as in the third embodiment, compared to the embodiment in which the traces are formed by only two conductive layers alternately, the distance DS1 (shown in fig. 1) from the edge of the display region DR to the edge of the drivingcircuit chip 106 can be reduced by about 50% in this embodiment.

In summary, in the display panel of the invention, the traces disposed in the peripheral region for electrically connecting the data lines may be formed by three or four different conductive layers, and since the traces all belong to different layers, the adjacent traces may partially overlap each other in the peripheral region to reduce the area occupied by the traces, thereby reducing the width of the lower frame of the display panel. In addition, in the display panel of the invention, the switch element for testing is moved upwards and arranged in the second part of the peripheral area of the substrate, so that the distance between the first conductive connecting pad and the second conductive connecting pad in the first part of the peripheral area can be reduced, the distance of the side edge of the driving circuit chip can be reduced, and the width of the lower frame of the display panel can be further reduced.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A display panel, comprising a display area and a peripheral area, wherein the peripheral area is disposed on at least one side of the display area, the display panel comprising:

a substrate;

the first conducting layer is arranged on the substrate and comprises a first routing wire arranged in the peripheral area;

the second conducting layer is arranged on the substrate and comprises a second routing wire arranged in the peripheral area; and

the third conducting layer is arranged on the substrate and comprises a third routing line which is arranged in the peripheral area;

wherein the first trace, the second trace, and the third trace are electrically insulated from each other, wherein at least two of the first trace, the second trace, and the third trace partially overlap in the peripheral region.

2. The display panel of claim 1, wherein a portion of the first trace and a portion of the second trace extend in parallel and overlap each other, and a portion of the third trace and the portion of the second trace extend in parallel and do not overlap each other.

3. The display panel of claim 1, wherein a portion of the first trace, a portion of the second trace, and a portion of the third trace extend in parallel and overlap one another.

4. The display panel of claim 1, further comprising a conductive line and a line replacement structure, wherein the conductive line extends from the display area to the peripheral area, and the line replacement structure is disposed in the peripheral area, and

the wire is electrically connected with the first routing or the third routing in the peripheral area through the wire changing structure.

5. The display panel of claim 1, wherein the peripheral region includes a first portion and a second portion respectively disposed on opposite sides of the display region, and the display panel further comprises:

a driving circuit chip and a plurality of test contact pads disposed in the first portion, wherein the first trace, the second trace and the third trace are electrically connected to the driving circuit chip; and

a plurality of switching elements disposed within the second portion, and one end of one of the switching elements is electrically connected to one of the test contact pads.

6. A display panel, comprising a display area and a peripheral area, wherein the peripheral area is disposed on at least one side of the display area, the display panel comprising:

a substrate;

the first conducting layer is arranged on the substrate and comprises a first routing wire arranged in the peripheral area;

the second conducting layer is arranged on the substrate and comprises a second routing wire arranged in the peripheral area;

the third conducting layer is arranged on the substrate and comprises a third routing line which is arranged in the peripheral area; and

the fourth conducting layer is arranged on the substrate and comprises a fourth routing wire and is arranged in the peripheral area;

wherein the first trace, the second trace, the third trace, and the fourth trace are electrically insulated from each other,

wherein at least two of the first trace, the second trace, the third trace, and the fourth trace partially overlap in the peripheral region.

7. The display panel of claim 6, wherein a portion of the first trace, a portion of the second trace, a portion of the third trace, and a portion of the fourth trace extend in parallel and overlap one another.

8. The display panel of claim 6, wherein a portion of the first trace, a portion of the second trace, and a portion of the third trace extend in parallel and overlap each other, and a portion of the fourth trace and the portion of the first trace extend in parallel and do not overlap each other.

9. The display panel of claim 6, wherein a portion of the first trace and a portion of the third trace extend in parallel and overlap each other, a portion of the second trace and a portion of the fourth trace extend in parallel and overlap each other, and the portion of the first trace and the portion of the third trace extend in parallel and do not overlap each other with the portion of the second trace and the portion of the fourth trace.

10. The display panel according to claim 6, wherein the peripheral region includes a first portion and a second portion respectively disposed on opposite sides of the display region, and the display panel further comprises:

a driving circuit chip and a plurality of test contact pads disposed within the first portion, wherein the first trace, the second trace, the third trace and the fourth trace are electrically connected to the driving circuit chip; and

a plurality of switching elements disposed within the second portion, and one end of one of the switching elements is electrically connected to one of the test contact pads.

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