CN112272023A - FPGA-based signal processing channel selection method - Google Patents
FPGA-based signal processing channel selection methodDownload PDFInfo
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Abstract
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a signal processing channel selection method based on an FPGA (field programmable gate array).
Background
In the face of the fierce scientific and technological competition environment in the world, the effective and high-speed transmission of information plays a crucial role, and the transmission of information is the transmission of signals.
For the selection of the signal transmission channel, the prior art mainly adopts a path of selection for processing, and has the problems that: once equipment breaks down, signal transmission cannot be carried out, one set of equipment has no alternative, if the faults cannot be solved in time, only another set of new equipment can be selected, interference factors of signals in reality are very many, and the risk of singly depending on one channel is very high. If a plurality of channels are directly selected, the more channels are, the more standby schemes are, one channel needs to use a whole set of acquisition and processing equipment, but the cost is difficult to control, the processing difficulty is very large, and the applicability is greatly resisted at the cost and the technical difficulty.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a method for selecting a signal processing channel based on an FPGA, takes the cost and feasibility of signal transmission into consideration, avoids the defect of adopting a single channel in the prior scheme, effectively ensures the transmission of information, processes and judges the signal quality to select a channel of a high-quality signal for signal transmission, and has high engineering usability for an FPGA development platform with high efficiency in signal processing and data interaction.
The purpose of the invention is realized by the following scheme:
a signal processing channel selection method based on FPGA includes the following steps:
s1, storing the signal frequency into a memory, establishing a mapping relation between the signal frequency and the channel, and obtaining the corresponding signal frequency by accessing the memory address of the signal frequency in the memory to complete the mapping between the channel and the signal frequency;
s2, judging whether the channel and signal frequency mapping is finished, if so, entering the step S3, otherwise, jumping back to the step S1;
s3, sequentially judging the parameter configuration of the plurality of channels, and if the channels are search channels, reading the receiving parameters from the memory for updating; otherwise, keeping the received parameters unchanged, and after the parameter configuration is completed, entering step S4;
s4, detecting the signal quality status, and after obtaining the optimal values of the signal quality of the plurality of channels within the time of the status processing buffer waiting, proceeding to step S5;
s5, confirming the channel working state, and respectively judging whether the signal quality of a plurality of channels is larger than a set threshold value; if yes, the channel is locked, otherwise, the channel is searched; if the number of the locking channels is more than or equal to 1, setting the locking channel with the optimal signal quality as a working channel; after the confirmation of the operating states of all the channels is completed, the process returns to step S1.
Further, in step S1, it is detected whether the configuration of the signal frequency point memory matched with the channel is completed, and if so, the channel parameter configuration state is entered, otherwise, the state is maintained.
Further, the memory comprises a frequency point memory.
Further, in step S3, after all the channels are detected, the parameter values read from the memory are placed in the register, and the receiving frequency point update flag is synchronously generated.
Further, in step S4, the optimal values of the signal quality of each of the plurality of channels in the time of the state processing buffer wait are obtained by a comparison method.
Further, in step S5, it is respectively determined whether the optimal value output by each channel in the previous state is greater than a set threshold; if so, setting the working state of the channel to be a locking state, otherwise, setting the working state of the channel to be a searching state; summing the channel locking indications according to bits to obtain the number of the locked channels; if the number of the locking channels is more than or equal to 1, selecting the locking channel with the optimal signal quality from the plurality of channels, and setting the locking channel as a working channel; after the confirmation of the operating states of all the channels is completed, the process returns to step S1.
The invention has the beneficial effects that:
(1) the invention selects multiple paths of acquisition at the signal acquisition part of the equipment, and selects the signal channel with the best quality as a channel by processing, thereby achieving the purposes of alternative and ensuring the transmission of signals, and only one set of equipment is processed after the acquisition, thereby having the advantages of greatly reducing the cost and considering the cost and the feasibility of signal transmission.
(2) The invention avoids the defect of adopting a single channel in the existing scheme, effectively ensures the information transmission, processes and judges the signal quality to select the channel of the high-quality signal for signal transmission, and has higher engineering usability for an FPGA development platform with very high efficiency in signal processing and data interaction.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a channel selection process;
FIG. 2 is a timing diagram of channel parameter update;
FIG. 3 is a flow chart of channel parameter configuration state processing;
FIG. 4 shows specific values of a frequency point memory;
FIG. 5 is a graph of two pieces of latency signal magnitude data;
FIG. 6 is a signal quality threshold;
FIG. 7 is a timing diagram illustrating a first buffer time parameter update;
FIG. 8 is a locking, searching, working channel parameter indication diagram;
FIG. 9 is a timing diagram illustrating a second segment buffer time parameter update;
FIG. 10 is a general diagram of two data update related data variables;
FIG. 11 is a flow chart of the steps of the method of the present invention.
Detailed Description
All of the features disclosed in the specification for all of the embodiments (including any accompanying claims, abstract and drawings), or all of the steps of a method or process so disclosed, may be combined and/or expanded, or substituted, in any way, except for mutually exclusive features and/or steps.
As shown in fig. 1 to 11, a method for selecting a channel based on FPGA signal processing includes the steps of:
s1, storing the signal frequency into a memory, establishing a mapping relation between the signal frequency and the channel, and obtaining the corresponding signal frequency by accessing the memory address of the signal frequency in the memory to complete the mapping between the channel and the signal frequency;
s2, judging whether the channel and signal frequency mapping is finished, if so, entering the step S3, otherwise, jumping back to the step S1;
s3, sequentially judging the parameter configuration of the plurality of channels, and if the channels are search channels, reading the receiving parameters from the memory for updating; otherwise, keeping the received parameters unchanged, and after the parameter configuration is completed, entering step S4;
s4, detecting the signal quality status, and after obtaining the optimal values of the signal quality of the plurality of channels within the time of the status processing buffer waiting, proceeding to step S5;
s5, confirming the channel working state, and respectively judging whether the signal quality of a plurality of channels is larger than a set threshold value; if yes, the channel is locked, otherwise, the channel is searched; if the number of the locking channels is more than or equal to 1, setting the locking channel with the optimal signal quality as a working channel; after the confirmation of the operating states of all the channels is completed, the process returns to step S1.
Further, in step S1, it is detected whether the configuration of the signal frequency point memory matched with the channel is completed, and if so, the channel parameter configuration state is entered, otherwise, the state is maintained.
Further, the memory comprises a frequency point memory.
Further, in step S3, after all the channels are detected, the parameter values read from the memory are placed in the register, and the receiving frequency point update flag is synchronously generated.
Further, in step S4, the optimal values of the signal quality of each of the plurality of channels in the time of the state processing buffer wait are obtained by a comparison method.
Further, in step S5, it is respectively determined whether the optimal value output by each channel in the previous state is greater than a set threshold; if so, setting the working state of the channel to be a locking state, otherwise, setting the working state of the channel to be a searching state; summing the channel locking indications according to bits to obtain the number of the locked channels; if the number of the locking channels is more than or equal to 1, selecting the locking channel with the optimal signal quality from the plurality of channels, and setting the locking channel as a working channel; after the confirmation of the operating states of all the channels is completed, the process returns to step S1.
In other embodiments of the present invention, after the reset is completed, the signal channel selection process is entered.
And finishing mapping between the channel and the signal frequency, detecting whether the configuration of a signal frequency point memory matched with the channel is finished, if the configuration is finished, entering a channel parameter configuration state, and if not, keeping the state unchanged.
And (3) channel parameter configuration states, and sequentially judging the working states of thechannels 1 to 3. If the channel is a search channel, reading the receiving parameters from the signal frequency point memory for updating; otherwise, the receiving parameters are kept unchanged. And after the parameter configuration is finished, entering a signal quality detection state.
And in the signal quality detection state, the optimal values of the signal quality of thechannels 1 to 3 in the time of state processing buffer waiting are respectively obtained and enter the channel working state confirmation.
Confirming the working state of the channel, wherein the main function of the state is to update the working states of thechannels 1 to 3, and the updating rule is as follows:
and respectively judging whether the signal quality of each channel is greater than a set threshold value. If yes, the channel is locked, otherwise, the channel is searched. And if the number of the locking channels is more than or equal to 1, setting the locking channel with the optimal signal quality as a working channel. And after the working states of thechannels 1 to 3 are confirmed, returning to the channel and signal frequency mapping to finish detection.
Channel and signal frequency mapping frequency point memory (RAM _ Freq)
The contents of the RAM _ Freq frequency point memory are detailed in Table 1, data bit width 2byte and depth 14.
TABLE 1 RAM _ Freq Address Allocation
Frequency point use identification (USEState _ Freq [20:0])
The frequency point usage identifier (UseState _ TDMFreq [20:0]) is defined in Table 2.
TABLE 2 frequency Point usage identifier definition
Channel parameter (Chfreq _ Rx)
The receive channel parameters are defined in table 3.
TABLE 3 channel parameter definition
Channel locked status indicator (lockState [2:0])
The channel lock status indication is the output of the receive channel parameter configuration module, which is defined in table 4.
TABLE 4 Lock status indication for channels
Channel search status indication (SearchState [2:0])
The channel search status indication is the channel parameter configuration module output, which is defined in table 5.
TABLE 5 receive channel search status indication
Working channel status indication (WorkState [2:0])
The working channel status indication (WorkState [2:0]) is derived from the receive channel parameter configuration module output, which is defined in Table 6.
Table 6 receive channel demodulation status indication
In other embodiments of the invention, one skilled in the art may perform the following steps, for example:
reset state
The reset signal is detected by using the clk100m clock, and when the reset signal is active, all registers are set to 0, thereby completing the reset.
Channel to signal frequency mapping completion
Detecting whether the configuration of the frequency point memory is completed, if so, entering a channel parameter configuration state, otherwise, keeping the state unchanged
Channel parameter configuration state
The channel parameter configuration state processing flow is shown in fig. 3. Sequentially judging the parameter configuration of thechannels 1 to 3, and reading the parameters from the frequency point memory for updating if the channel is a search channel; otherwise, the parameters are kept unchanged.
Updated parameters require that other channels be unused (by bin use identification usestat _ Freq [20:0 ]); otherwise, the parameters are kept unchanged. And after the parameter configuration is finished, entering a signal quality detection state.
After the detection of 3 channels is completed, the parameter value read from the frequency point memory (RAM _ Freq) is placed on a Chfreq register, and a receiving frequency point Update flag (Chpara _ Update) is synchronously generated.
In the signal quality detection state, the optimum values of the signal qualities of thechannels 1 to 3 in the time of the state processing buffer wait are respectively obtained by a comparison method. And when the buffering time is set to 240ms, entering channel working state confirmation.
Confirming the working state of the channel, wherein the main function of the state is to update the working states of thechannels 1 to 3, and the updating parameters comprise:
a) lane lock status indication (LockState): see Table 4
b) Channel search status indication (SearchState): see Table 5
c) Working channel status indication (workbench): see Table 6
The update rule is as follows:
and respectively judging whether the optimal value output by each channel in the last state is greater than a set threshold. If so, setting the working state of the channel to be a locking state, otherwise, setting the working state of the channel to be a searching state.
And summing the channel locking indications (WorkState) according to bits to obtain the number of the locked channels. If the number of the locking channels is more than or equal to 1, the locking channel with the optimal signal quality in the 3 channels is selected and set as the working channel. And after the working state of thechannels 1 to 3 is confirmed, returning to the state detection of the frequency point memory.
According to the method, software vivado is developed in the FPGA for simulation, and through experiments, the simulation result is consistent with a theoretical value, so that the correctness and the feasibility of the method are proved.
The invention selects multiple paths of acquisition at the signal acquisition part of the equipment, and selects the signal channel with the best quality as a channel by processing, thereby achieving the purposes of alternative and ensuring the transmission of signals, and only one set of equipment is processed after the acquisition, thereby having the advantages of greatly reducing the cost and considering the cost and the feasibility of signal transmission.
The invention avoids the defect of adopting a single channel in the existing scheme, effectively ensures the information transmission, processes and judges the signal quality to select the channel of the high-quality signal for signal transmission, and has higher engineering usability for an FPGA development platform with very high efficiency in signal processing and data interaction.
Simulating in FPGA development software vivado, specifically:
the frequency value of each address of the frequency point memory (RAM _ Freq) is stored in the memory in advance, and the mapping of the channel and the signal frequency is completed as shown in figure 4. (note:rows address 0,store data 2110, and so on in the following).
The signal quality size data of thechannels 1 to 3 of the waiting period is buffered by simulating two state processing, as shown in fig. 5.
The threshold value of the signal quality is set to 16-bit 16-ary number 03ff, as shown in fig. 6, the number and the system are consistent with the data of the signal quality of thechannels 1 to 3, and the observation is convenient.
In the initial state, the states of thechannels 1 to 3 are unknown, and all the channels are set to the search state, and SearchState [0] is 1, SearchState [1] is 1, SearchState [2] is 1, and SearchState [2:0] is 7 according to the correspondence relationship of table 5. The LockState [2:0] corresponding to this time period is 0 and the WorkState [2:0] is 0. The frequency corresponding to channel 1 is the frequency stored in RAM _Freq address 0, ChFreq [15:0] is 2110, the frequency ofchannel 2 isaddress 1, ChFreq [31:16] is 2111, the frequency of channel 3 isaddress 2, ChFreq [47:32] is 2112, and therefore, ChFreq [47:0] is 211221112110, and the simulation result is as shown in fig. 7.
As shown in the figure, in the first state processing buffer waiting time, the optimal signal quality value ofchannel 1 is 0890, the optimal signal quality value ofchannel 2 is 0084, the optimal signal quality value of channel 3 is 0879, the optimal signal quality values of the three channels are compared with the threshold values,channels 1 and 3 are greater than the threshold value, andchannel 2 is smaller than the threshold value, so that LockState [0] is 1, LockState [1] is 0, LockState [2] is 1, LockState [2:0] is 5, and corresponding SearchState [2:0] is 2. And comparing the locked channels, and setting the selected maximum value as a working channel, so that thechannel 1 is the working channel, and WorkState [2:0] is 1. Initial state and first period of time processing LockState, SearchState, WorkState values are as in fig. 8.
In the second state processing buffer waiting time, only thechannel 2 is a search channel through the last state processing, the parameters need to be updated, and other channels are kept unchanged. Since the frequency parameter of the channel cannot be used with the frequency being used,channel 1 uses the frequency of RAM _Freq address 0, channel 3 uses the frequency of RAM _Freq address 2, andchannel 2 updates can only use the frequency of RAM _ Freq address 3 that is not occupied with a new one. Thus, ChFreq [15:0] ═ 2110, ChFreq [31:16] ═ 2114, ChFreq [47:32] ═ 2112, and ChFreq [47:0] ═ 211221142110, as in fig. 9.
The two data update related data variable general diagram is shown in fig. 10.
Through experiments, the simulation result is consistent with a theoretical value, and the correctness and the feasibility of the method are proved. The method has the advantages that 3 channels are selected for signal processing, the problem that 1-path processing cannot work under an unexpected condition can be effectively avoided, 3 paths can be mutually used as main and standby selection, the optimal signal is selected, the processing process is effectively simplified, and the 3 channels are not required to be processed. The method ensures high efficiency and accuracy of signal processing and has higher practicability. The method can be changed on a platform, is applied to different scenes aiming at different conditions, and has high transportability.
The functionality of the present invention, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium, and all or part of the steps of the method according to the embodiments of the present invention are executed in a computer device (which may be a personal computer, a server, or a network device) and corresponding software. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, or an optical disk, exist in a read-only Memory (RAM), a Random Access Memory (RAM), and the like, for performing a test or actual data in a program implementation.
Claims (6)
1. A method for selecting a signal processing channel based on an FPGA (field programmable gate array) is characterized by comprising the following steps of:
s1, storing the signal frequency into a memory, establishing a mapping relation between the signal frequency and the channel, and obtaining the corresponding signal frequency by accessing the memory address of the signal frequency in the memory to complete the mapping between the channel and the signal frequency;
s2, judging whether the channel and signal frequency mapping is finished, if so, entering the step S3, otherwise, jumping back to the step S1;
s3, sequentially judging the parameter configuration of the plurality of channels, and if the channels are search channels, reading the receiving parameters from the memory for updating; otherwise, keeping the received parameters unchanged, and after the parameter configuration is completed, entering step S4;
s4, detecting the signal quality status, and after obtaining the optimal values of the signal quality of the plurality of channels within the time of the status processing buffer waiting, proceeding to step S5;
s5, confirming the channel working state, and respectively judging whether the signal quality of a plurality of channels is larger than a set threshold value; if yes, the channel is locked, otherwise, the channel is searched; if the number of the locking channels is more than or equal to 1, setting the locking channel with the optimal signal quality as a working channel; after the confirmation of the operating states of all the channels is completed, the process returns to step S1.
2. The method for selecting the channel based on the FPGA signal processing of claim 1, wherein in step S1, it is detected whether the configuration of the signal frequency point memory matched with the channel is completed, if so, the channel parameter configuration state is entered, otherwise, the state is kept unchanged.
3. The FPGA-based signal processing channel selection method of claim 1, wherein the memory comprises a frequency bin memory.
4. The method for selecting the channel based on the FPGA signal processing of claim 1, wherein in step S3, after the detection of all the channels is completed, the parameter values read from the memory are placed in the register, and the receiving frequency point update flag is synchronously generated.
5. The method for selecting the channel for processing signals based on FPGA of claim 1, wherein in step S4, a comparison method is used to respectively obtain the optimal values of the signal quality of the plurality of channels in the time of the buffer waiting of the state processing.
6. The method for selecting the channel based on the FPGA signal processing of claim 1, wherein in step S5, it is respectively determined whether the optimal value output by each channel in the last state is greater than a set threshold; if so, setting the working state of the channel to be a locking state, otherwise, setting the working state of the channel to be a searching state; summing the channel locking indications according to bits to obtain the number of the locked channels; if the number of the locking channels is more than or equal to 1, selecting the locking channel with the optimal signal quality from the plurality of channels, and setting the locking channel as a working channel; after the confirmation of the operating states of all the channels is completed, the process returns to step S1.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115371749A (en)* | 2022-08-29 | 2022-11-22 | 西安安森智能仪器股份有限公司 | Echo signal receiving channel switching circuit and method of multi-channel ultrasonic flowmeter |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1250273A (en)* | 1998-08-28 | 2000-04-12 | 日本电气株式会社 | Personal portable telephone system mobile radio station |
| US6400751B1 (en)* | 1998-07-01 | 2002-06-04 | Itt Manufacturing Enterprises, Inc. | Adaptive frequency sharing method and apparatus |
| US20070067813A1 (en)* | 2005-09-22 | 2007-03-22 | Lite-On Technology Corporation | Method and device for receiving digital braodcasts |
| CN102023302A (en)* | 2010-12-17 | 2011-04-20 | 浙江大学 | Multichannel cooperative control method and device in satellite navigation receiver |
| CN102208935A (en)* | 2010-03-31 | 2011-10-05 | 重庆重邮信科通信技术有限公司 | Repeater of time division duplex system |
| CN103384155A (en)* | 2013-07-17 | 2013-11-06 | 三维通信股份有限公司 | Automatic matching method for radio frequency channels of multichannel distributed antenna system |
| DE102013101300A1 (en)* | 2013-02-11 | 2014-08-14 | Dspace Digital Signal Processing And Control Engineering Gmbh | Method for assessing signal value i.e. engine speed, of field programmable gate array at run-time of processing device, involves reading status data from memory as read-back data, and determining signal value by mapping data on value |
| CN104270169A (en)* | 2014-10-21 | 2015-01-07 | 中国航空无线电电子研究所 | Multi-channel self-adaptation frequency-hopping processing method and system suitable for aeronautical ad-hoc network |
| CN105450322A (en)* | 2015-11-11 | 2016-03-30 | 成都飞机工业（集团）有限责任公司 | Multi-bit-stream and multi-redundant telemetry data stream real-time fusion method |
| CN105635856A (en)* | 2015-12-18 | 2016-06-01 | 成都航天通信设备有限责任公司 | Marine voice communication system for unmanned aerial vehicle |
| CN108226761A (en)* | 2017-12-28 | 2018-06-29 | 合肥工大高科信息科技股份有限公司 | A kind of rail traffic vehicles speed acquires the method with replacing self-test in real time |
| US20180270699A1 (en)* | 2017-03-16 | 2018-09-20 | Ofinno Technologies, Llc | Buffer Status Reporting Procedure in a Wireless Device and Wireless Network |
| CN109195178A (en)* | 2018-11-19 | 2019-01-11 | 国网河北省电力有限公司电力科学研究院 | signal quality monitoring method and terminal device |
| CN109471077A (en)* | 2018-11-02 | 2019-03-15 | 北京振兴计量测试研究所 | A Frequency Hopping SAR Echo Signal Generation Method |
- 2020
- 2020-10-23CNCN202011147109.XApatent/CN112272023B/enactiveActive
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6400751B1 (en)* | 1998-07-01 | 2002-06-04 | Itt Manufacturing Enterprises, Inc. | Adaptive frequency sharing method and apparatus |
| CN1250273A (en)* | 1998-08-28 | 2000-04-12 | 日本电气株式会社 | Personal portable telephone system mobile radio station |
| US20070067813A1 (en)* | 2005-09-22 | 2007-03-22 | Lite-On Technology Corporation | Method and device for receiving digital braodcasts |
| CN102208935A (en)* | 2010-03-31 | 2011-10-05 | 重庆重邮信科通信技术有限公司 | Repeater of time division duplex system |
| CN102023302A (en)* | 2010-12-17 | 2011-04-20 | 浙江大学 | Multichannel cooperative control method and device in satellite navigation receiver |
| DE102013101300A1 (en)* | 2013-02-11 | 2014-08-14 | Dspace Digital Signal Processing And Control Engineering Gmbh | Method for assessing signal value i.e. engine speed, of field programmable gate array at run-time of processing device, involves reading status data from memory as read-back data, and determining signal value by mapping data on value |
| CN103384155A (en)* | 2013-07-17 | 2013-11-06 | 三维通信股份有限公司 | Automatic matching method for radio frequency channels of multichannel distributed antenna system |
| CN104270169A (en)* | 2014-10-21 | 2015-01-07 | 中国航空无线电电子研究所 | Multi-channel self-adaptation frequency-hopping processing method and system suitable for aeronautical ad-hoc network |
| CN105450322A (en)* | 2015-11-11 | 2016-03-30 | 成都飞机工业（集团）有限责任公司 | Multi-bit-stream and multi-redundant telemetry data stream real-time fusion method |
| CN105635856A (en)* | 2015-12-18 | 2016-06-01 | 成都航天通信设备有限责任公司 | Marine voice communication system for unmanned aerial vehicle |
| US20180270699A1 (en)* | 2017-03-16 | 2018-09-20 | Ofinno Technologies, Llc | Buffer Status Reporting Procedure in a Wireless Device and Wireless Network |
| CN108226761A (en)* | 2017-12-28 | 2018-06-29 | 合肥工大高科信息科技股份有限公司 | A kind of rail traffic vehicles speed acquires the method with replacing self-test in real time |
| CN109471077A (en)* | 2018-11-02 | 2019-03-15 | 北京振兴计量测试研究所 | A Frequency Hopping SAR Echo Signal Generation Method |
| CN109195178A (en)* | 2018-11-19 | 2019-01-11 | 国网河北省电力有限公司电力科学研究院 | signal quality monitoring method and terminal device |
Non-Patent Citations (1)
| Title |
|---|
| 杨成山: "基于FPGA的数字信道化接收机研究与实现", 《中国优秀硕士学位论文全文数据库信息科技辑》, pages 136 - 30* |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115371749A (en)* | 2022-08-29 | 2022-11-22 | 西安安森智能仪器股份有限公司 | Echo signal receiving channel switching circuit and method of multi-channel ultrasonic flowmeter |
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|---|---|
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