CN112259518A - Fan-out packaging structure of chip and fan-out packaging method thereof - Google Patents
Fan-out packaging structure of chip and fan-out packaging method thereofDownload PDFInfo
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- CN112259518A CN112259518ACN202010019684.5ACN202010019684ACN112259518ACN 112259518 ACN112259518 ACN 112259518ACN 202010019684 ACN202010019684 ACN 202010019684ACN 112259518 ACN112259518 ACN 112259518A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
Abstract
Translated fromChinese
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out packaging structure of a semiconductor and a packaging method thereof.
Background
With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.
The main component of the electronic device for realizing the preset function is a chip, along with the continuous progress of the integrated circuit technology, the integration level of the chip is higher and higher, the function of the chip is stronger and stronger, and the size of the chip is smaller and smaller, so that the chip needs to form a packaging structure through packaging so as to be convenient for the chip to be electrically connected with an external circuit.
In the prior art, a wafer level packaging technology is adopted, and a TSV structure is formed on a wafer to electrically and externally connect a welding pad on the front surface of a chip to the whole back surface of the chip, so that the welding pad is electrically and externally connected in a decentralized arrangement manner, and the chip is electrically connected with other external circuits conveniently. The packaging technology has high requirements on the precision of the process, complex process flow and high cost.
There is wafer-level packaging technology among the prior art, at first the wafer of cutting obtains a chip, then redistribute the chip, form wafer-like, it has packaging material to fill between chip and the chip, through the process of rewiring with the positive pad electrical behavior of chip on external connection to plastic packaging material, realize the decentralized of pad electrical behavior external connection and arrange, but the rewiring process is high to the position precision requirement of chip, and the plastic packaging material breathing problem in the process flow leads to the position of chip to take place the skew easily, lead to the promotion of rewiring process defective rate, also difficult adjustment in the follow-up flow.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides the fan-out packaging structure of the chip and the fan-out packaging method thereof, which can simplify the process flow, reduce the cost, reduce the precision requirement of the process and have better yield.
The invention provides a fan-out packaging structure of a chip, which comprises: the front surface of the flexible circuit board is provided with a plurality of first connecting pads, the back surface of the flexible circuit board is provided with a plurality of second connecting pads, and the second connecting pads are electrically connected with the first connecting pads; the front surface of the first chip is attached to the front surface of the flexible circuit board, and the first welding pads are electrically connected with the first connecting pads; and the plastic packaging layer is arranged on the front surface of the flexible circuit board and wraps the first chip.
Preferably, the fan-out package structure of the chip has at least one third chip, the front surface of which has a plurality of third bonding pads, the front surface of the third chip is attached to the front surface of the flexible circuit board, and the third bonding pads are electrically connected to the first connection pads.
Preferably, the back surface of the flexible circuit board is provided with a circular or columnar welding point, and the welding point is electrically connected with the second connecting pad.
Preferably, the front surface of the flexible circuit board is provided with a plurality of third connecting pads, the plastic packaging layer covers the third connecting pads, the third connecting pads are electrically connected with the first connecting pads or the second connecting pads, the plastic packaging layer is provided with a plurality of through holes, the bottoms of the through holes are exposed out of the third connecting pads, and the through holes are internally provided with electric connection parts electrically connected with the third connecting pads.
Preferably, the chip further comprises a second chip, wherein the front surface of the second chip is provided with a plurality of second bonding pads, the front surface of the second chip is stacked on the back surface of the first chip, and the second bonding pads are electrically connected with the electrical connection parts.
Preferably, the electrical connection portion is a metal conductive column or a rewiring circuit.
The invention also provides a fan-out packaging method of the chip, which comprises the following steps: providing a carrier plate; providing a flexible circuit board, fixing the back of the flexible circuit board on the carrier plate, wherein the flexible circuit board is provided with flexible circuit board units which are arranged in an array manner, the front of each flexible circuit board unit is provided with a plurality of first connecting pads, the back of each flexible circuit board unit is provided with a plurality of second connecting pads, and the second connecting pads are electrically connected with the first connecting pads; providing a plurality of first chips, wherein the front surfaces of the first chips are provided with a plurality of first welding pads; the first chip is inversely installed on the front face of the flexible circuit board unit, so that the front face of the first chip is attached to the front face of the flexible circuit board unit, and the first welding pad is electrically connected with the first connecting pad; forming a plastic packaging layer on the front surface of the flexible circuit board through a plastic packaging process, wherein the first chip is coated by the plastic packaging layer; the fan-out packaging structure of the chip is formed through a cutting process.
Preferably, the front surface of the flexible circuit board is provided with a plurality of third connecting pads, the plastic packaging layer covers the third connecting pads, and the third connecting pads are electrically connected with the first connecting pads or the second connecting pads; after forming the plastic packaging layer and before cutting, forming a plurality of through holes on the plastic packaging layer, wherein the bottom of each through hole exposes the third connecting pad; and forming an electric connection part electrically connected with the third connecting pad in the through hole.
Preferably, a plurality of second chips are provided, and the front surface of each second chip is provided with a plurality of second welding pads; and stacking the front surface of the second chip on the back surface of the first chip, and electrically connecting the second welding pad with the electric connection part.
Preferably, the flexible circuit board is fixed on the carrier board through a temporary bonding glue, and after the plastic package layer is formed and before cutting, the temporary bonding glue loses viscosity through a de-bonding process.
Preferably, after removing the viscosity of the temporary bonding glue and before cutting, the carrier board is removed, and then a circular or columnar solder joint is formed on the back surface of the flexible circuit board, and the solder joint is electrically connected with the second connection pad.
The invention has the beneficial effects that: the fan-out circuit is designed by utilizing the flexible circuit board in advance, the fan-out circuit does not need to be formed in a chip packaging stage, the process flow is simplified, the first chip and the flexible circuit board are fixedly and electrically connected in position before the plastic packaging layer is formed, the expansion and contraction of the plastic packaging layer in the subsequent process hardly cause the disconnection of the first chip and the flexible circuit board, the packaging yield cannot be reduced, and the precision requirement of the process is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a fan-out package structure of a chip according to a first preferred embodiment of the present invention;
FIG. 2 is a top view of a fan-out package structure of a chip in accordance with a second preferred embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a fan-out package structure of a chip according to a third embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a fan-out package structure of a chip according to a fourth embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a fan-out package structure of a chip according to a fifth embodiment of the present invention;
FIGS. 6-8 are process structure diagrams of a method of forming a fan-out package structure of the chip of FIG. 1;
fig. 9-12 are process structure diagrams of a method of forming a fan-out package structure of the chip of fig. 5.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
Referring to fig. 1, a structural schematic diagram of a fan-out package structure of a chip according to a first preferred embodiment of the present invention includes aflexible circuit board 10, afirst chip 100, and amolding compound layer 20.
The front surface of the flexible printedcircuit board 10 has a plurality offirst connection pads 11, and the back surface thereof has a plurality ofsecond connection pads 12, the flexible printedcircuit board 10 is a printed circuit with high reliability and excellent flexibility, and thesecond connection pads 12 respectively located on the front and back surfaces are electrically connected with thefirst connection pads 11 by embedding a circuit design on a flexible light and thin plastic sheet.
The front surface of thefirst chip 100 has a plurality offirst bonding pads 101, the front surface of thefirst chip 100 is attached to the front surface of the flexible printedcircuit board 10, and thefirst bonding pads 101 are electrically connected to thefirst connection pads 11. In this embodiment, thefirst bonding pad 101 and thefirst connection pad 11 can be fixed and electrically connected by forming a metal micro bump on one of them and then welding them.
Themolding compound layer 20 is disposed on the front surface of the flexible printedcircuit board 10 and covers thefirst chip 100. The molding compound is cured to form themolding layer 20, and themolding layer 20 further cures and molds thefirst chip 100 and theflexible circuit board 10, so that the stability of the whole packaging structure is improved.
Referring to fig. 2, which is a schematic top view of a fan-out package structure of a chip according to a second preferred embodiment of the present invention, in this embodiment, athird chip 300 is further disposed on the front surface of theflexible circuit board 10, the front surface of thethird chip 300 has a plurality ofthird bonding pads 301, the front surface of thethird chip 300 is attached to the front surface of theflexible circuit board 10, and thethird bonding pads 301 are electrically connected to thefirst bonding pads 11. Thethird chip 300 may be the same chip as thefirst chip 100 or may be a different chip from thefirst chip 100.
In fig. 2, in order to realize the electrical connection of the partial I/O terminal between thefirst chip 100 and thethird chip 300, the electrical connection of the partial I/O terminal between thefirst chip 100 and thethird chip 300 can be realized by disposing the electrical connection of the partialfirst connection pad 11.
In the present invention, the connection pad disposed on the front side of the flexible printedcircuit board 10 and used for soldering with thefirst chip 100 is referred to as afirst connection pad 11, and the connection pad disposed on the back side of the flexible printedcircuit board 10 is referred to as asecond connection pad 12, so that some of thefirst connection pads 11 can be electrically connected according to actual requirements.
The number of chips and functions of the chips disposed on the front surface of the flexible printedcircuit board 10 are not particularly limited, and one or two or more chips may be disposed in one package according to actual needs.
Referring to fig. 3, a schematic structural diagram of a fan-out package structure of a chip according to a third embodiment of the invention is different from fig. 1 in that a circular orcolumnar solder joint 13 is disposed on a back surface of a flexible printedcircuit 10, thesolder joint 13 is electrically connected to asecond connection pad 12, and thesolder joint 13 is directly formed on thesecond connection pad 12. In fig. 3, which is the most commonly used BGA technology, the second connectingpads 12 are arranged on the back surface of the flexible printedcircuit board 10 in an array manner, and circular orcylindrical solder joints 13 are formed on the second connectingpads 12 by a ball-mounting process.
Referring to fig. 4, which is a schematic structural view of a fan-out package structure of a chip according to a fourth embodiment of the present invention, a front surface of a flexible printedcircuit 10 has a plurality ofthird connection pads 14, thethird connection pads 14 are disposed on a periphery of afirst connection pad 11, amolding layer 20 covers thethird connection pads 14, thethird connection pads 14 are electrically connected to thefirst connection pad 11 or asecond connection pad 12, themolding layer 20 has a plurality of through holes, bottom portions of the through holes expose thethird connection pads 14, and the through holes haveelectrical connection portions 15 electrically connected to thethird connection pads 14. Theelectrical connection portion 15 can be electrically connected to an external circuit, and theelectrical connection portion 15 is used to electrically connect thethird connection pad 14 to an external circuit.
Please refer to fig. 5, which is a schematic structural diagram of a fan-out package structure of a chip according to a fifth embodiment of the present invention, the package structure includes asecond chip 200, a front surface of thesecond chip 200 has a plurality ofsecond bonding pads 201, the front surface of thesecond chip 200 is stacked on a back surface of thefirst chip 100, and thesecond bonding pads 201 are electrically connected to theelectrical connection portions 15.
In the present embodiment, theelectrical connection portion 15 is a metal conductive pillar. Thesecond bonding pad 201 and theelectrical connection portion 15 are fixed and electrically connected by forming a metal micro-bump thereon and then welding the metal micro-bump and the second bonding pad to each other.
In other embodiments of the present invention, when the size of thesecond chip 200 is smaller than that of thefirst chip 100 or thesecond pads 201 of thesecond chip 200 are not directly corresponding to the third connectingpads 14 but are misaligned, theelectrical connection portion 15 may be configured as a redistribution circuit for electrically connecting thesecond pads 201 to the third connectingpads 14.
In order to further improve the stability of the package structure, asecond molding layer 30 may be formed on themolding layer 20.
The invention also provides a fan-out packaging method of the chip, which comprises the following steps:
referring to fig. 6, acarrier 50 is provided; providing a flexible circuit board, fixing the back of the flexible circuit board on acarrier plate 50, wherein the flexible circuit board is provided with flexiblecircuit board units 10 arranged in an array, the front of each flexiblecircuit board unit 10 is provided with a plurality of first connectingpads 11, the back of each flexible circuit board unit is provided with a plurality of second connectingpads 12, and the second connectingpads 12 are electrically connected with the first connectingpads 11. The flexible printed circuit board is a printed circuit with high reliability and excellent flexibility, and thesecond connection pads 12 on the front and back surfaces are electrically connected with thefirst connection pads 11 by embedding a circuit design on a bendable light and thin plastic sheet.
In the present embodiment, the flexible printed circuit board is fixed on thecarrier 50 by temporary bonding glue.
Preferably, after removing the viscosity of the temporary bonding glue and before cutting, the carrier board is removed, and then a circular or columnar solder joint is formed on the back surface of the flexible circuit board, and the solder joint is electrically connected with the second connection pad.
Referring to fig. 7, a plurality offirst chips 100 are provided, wherein a front surface of thefirst chip 100 has a plurality offirst pads 101; thefirst chip 100 is flip-chip mounted on the front surface of the flexible printedcircuit board unit 10, the front surface of thefirst chip 100 is attached to the front surface of the flexible printedcircuit board unit 10, and thefirst bonding pads 101 are electrically connected to thefirst connection pads 11. In the embodiment, the metal micro-bump is formed on one of thefirst bonding pad 101 and thefirst connection pad 11, and then the two are soldered to each other, so as to realize the fixation and the electrical connection between the two.
Referring to fig. 8, aplastic package layer 20 is formed on the front surface of the flexible circuit board through a plastic package process, and thefirst chip 100 is covered by theplastic package layer 20;
after themolding layer 20 is formed, the temporary bonding paste is tack-free by a debonding process.
Then, a fan-out package structure of the chip as shown in fig. 1 is formed through a dicing process.
In order to form the fan-out package structure of the chip as shown in fig. 3, after removing the adhesion of the temporary bonding paste and before cutting, thecarrier board 50 is removed, and then circular or pillar-shaped pads 13 are formed on the back surface of the flexible circuit board through a ball-planting process, thepads 13 are electrically connected to thesecond connection pads 12, and thepads 13 are directly formed on thesecond connection pads 12. And then cutting is carried out to form the fan-out packaging structure of the chip shown in fig. 3.
In order to form the fan-out package structure of the chip as shown in fig. 5, the method further comprises the following steps:
referring to fig. 9, a plurality of third connectingpads 14 are disposed on the front surface of the flexible printedcircuit unit 10 of the flexible printed circuit, the third connectingpads 14 are disposed on the periphery of the first connectingpads 11, theplastic sealing layer 20 covers the third connectingpads 14, and the third connectingpads 14 are electrically connected to the first connectingpads 11 or the second connectingpads 12.
A plurality of throughholes 21 are formed on themolding layer 20, and the bottom of the throughholes 21 expose thethird connection pads 14. In the present embodiment, the viahole 21 is formed by a laser drilling process.
Referring to fig. 10, anelectrical connection portion 15 electrically connected to thethird connection pad 14 is formed in the throughhole 21. Theelectrical connection portion 15 can be electrically connected to an external circuit, and theelectrical connection portion 15 is used to electrically connect thethird connection pad 14 to an external circuit.
In the present embodiment, theelectrical connection portion 15 is a metal conductive pillar. In other embodiments of the present invention, when the size of thesecond chip 200 is smaller than that of thefirst chip 100 or thesecond pads 201 of thesecond chip 200 are not directly corresponding to the third connectingpads 14 but are misaligned, a redistribution circuit may be formed as theelectrical connection portion 15 through an RDL process to electrically connect thesecond pads 201 to the third connectingpads 14.
Referring to fig. 11, asecond chip 200 is provided, wherein a front surface of thesecond chip 200 has a plurality ofsecond bonding pads 201, the front surface of thesecond chip 200 is stacked on the back surface of thefirst chip 100, and thesecond bonding pads 201 are electrically connected to theelectrical connection portions 15. In the present embodiment, theelectrical connection portion 15 is a metal conductive pillar. Thesecond bonding pad 201 and theelectrical connection portion 15 are fixed and electrically connected by forming a metal micro-bump thereon and then welding the metal micro-bump and the second bonding pad to each other.
Referring to fig. 12, asecond molding layer 30 is formed through a molding process.
Then, thecarrier 50 is removed, and then a circular or cylindrical solder joint 13 is formed on the back surface of the flexible printed circuit board by a ball-mounting process, the solder joint 13 is electrically connected to the second connectingpad 12, and the solder joint 13 is directly formed on the second connectingpad 12.
And then cutting is carried out to form the fan-out packaging structure of the chip shown in fig. 5.
The invention has the beneficial effects that: the fan-out circuit is designed by utilizing the flexible circuit board in advance, the fan-out circuit does not need to be formed in a chip packaging stage, the process flow is simplified, the first chip and the flexible circuit board are fixedly and electrically connected in position before the plastic packaging layer is formed, the expansion and contraction of the plastic packaging layer in the subsequent process hardly cause the disconnection of the first chip and the flexible circuit board, the packaging yield cannot be reduced, and the precision requirement of the process is reduced.
The invention is described above with reference to the accompanying drawings, it is obvious that the invention is not limited to the above embodiments, and it is within the scope of the invention to adopt various insubstantial modifications of the technical solution of the invention or to apply the concept and technical solution of the invention directly to other occasions without any modification.
Claims (11)
Translated fromChinesePriority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010019684.5ACN112259518A (en) | 2020-01-08 | 2020-01-08 | Fan-out packaging structure of chip and fan-out packaging method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010019684.5ACN112259518A (en) | 2020-01-08 | 2020-01-08 | Fan-out packaging structure of chip and fan-out packaging method thereof |
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| CN112259518Atrue CN112259518A (en) | 2021-01-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020386A (en)* | 2022-06-17 | 2022-09-06 | 长电科技管理有限公司 | Packaging structure, manufacturing method of packaging structure, circuit board structure and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020386A (en)* | 2022-06-17 | 2022-09-06 | 长电科技管理有限公司 | Packaging structure, manufacturing method of packaging structure, circuit board structure and electronic equipment |
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