Drawings
Fig. 1 is a schematic diagram of a primary controller applied to a primary side of a power converter according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a compensation voltage generation circuit within the primary controller for generating the compensation voltage.
Fig. 3 is a diagram illustrating an actual value of the sensing voltage and an ideal value of the sensing voltage.
Fig. 4 is a schematic diagram illustrating a relationship between an output current on the secondary side of the power converter and an input voltage on the primary side of the power converter.
Fig. 5 is a schematic diagram illustrating a current compensation circuit.
Fig. 6 is a schematic diagram illustrating a relationship between the compensation current and the auxiliary voltage.
Fig. 7 is a diagram illustrating the relationship between output current, output voltage and input voltage.
Fig. 8 is a schematic diagram illustrating a reference current source.
Fig. 9 is a diagram illustrating the relationship between the output current, the output voltage, and the input voltage.
Fig. 10 is a flowchart of an operation method of a primary controller applied to a primary side of a power converter according to a second embodiment of the present invention.
Wherein the reference numerals are as follows:
100 power converter
101 voltage dividing circuit
102 power switch
103 auxiliary winding
104 sense resistor
106 primary side winding
108 secondary side winding
110 diode
200 primary controller
202 current compensation circuit
204 compensation voltage generating circuit
2042 reference current source
2044 switch
2046 Peak Current Source
2022 digital-to-analog converter
20242. 20422, 20424 and 20436 operational amplifier
20244. 20426, 20428, 20434, 20438 NMOS metal oxide semiconductor transistors
20246. 20440 resistor
20248. 20250, 20252, 20430 pmos transistors
20442 capacitance
20444 voltage-current converter
CCOMP compensation capacitor
COMP, GATE, ZCD, CS, HV, VCC, pin
GND
DS1, DS2 digital signals
GCS Gate control Signal
I1 first Current
I2 second Current
IPRI, IS current
IOUT output current
Peak current of IPK
IREF reference current
ICC compensation current
PRI Primary side
SEC Secondary side
TDIS discharge time
TON on time
VDC direct voltage
VCOMP compensation voltage
VS sense voltage
Peak voltage of VPK
Ideal peak voltage of VIPK
VAC input voltage
Auxiliary voltage of VZCD
Constant voltage of VZCDM
VHV, VAUX, VVPO voltages
VOUT output voltage
VREF reference voltage
1000step 1006
Detailed Description
Referring to fig. 1 and 2, fig. 1 is a schematic diagram of aprimary controller 200 applied to a primary side PRI of apower converter 100 according to a first embodiment of the present invention, and fig. 2 is a schematic diagram illustrating a compensationvoltage generating circuit 204 for generating a compensation voltage VCOMP in theprimary controller 200, wherein theprimary controller 200 includes acurrent compensation circuit 202 and a compensationvoltage generating circuit 204, thepower converter 100 is a flyback power converter (flyback power converter), and thecurrent compensation circuit 202 is coupled to an auxiliary winding 103 of the primary side PRI of thepower converter 100 through avoltage dividing circuit 101. As shown in fig. 2, the compensationvoltage generating circuit 204 determines the compensation voltage VCOMP at the pin COMP of theprimary controller 200 by using a peak current IPK, the discharge time TDIS of the secondary side SEC of thepower converter 100, and a reference current IREF. In addition, as shown in fig. 2, the compensationvoltage generating circuit 204 includes a referencecurrent source 2042, aswitch 2044, and a peakcurrent source 2046, wherein the referencecurrent source 2042 is configured to provide a reference current IREF, theswitch 2044 is turned on according to the discharge time TDIS, the peakcurrent source 2046 is configured to provide a peak current IPK, and the coupling relationship among the referencecurrent source 2042, theswitch 2044, and the peakcurrent source 2046 can refer to fig. 2, which is not repeated herein. After the compensation voltage VCOMP is generated, a GATE control signal generating circuit (not shown in fig. 1 and 2) in thepower converter 100 generates a GATE control signal GCS according to the compensation voltage VCOMP to control thepower switch 102 of thepower converter 100 to turn on or off, wherein the GATE control signal GCS is transmitted to thepower switch 102 through the pin GATE of theprimary controller 200, and the peak current IPK is determined by equation (1):
as shown in equation (1), VPK is the peak voltage of the primary side PRI of thepower converter 100, RS is the resistance of thesensing resistor 104 of the primary side PRI of thepower converter 100, and K is a constant.
In addition, as shown in fig. 2, when the compensation voltage VCOMP is stable, equation (2) can be determined according to the charge conservation on the compensation capacitor CCOMP coupled to the pin COMP:
IREF×TS=IPK×TDIS (2)
as shown in equation (2), TS is the switching period of thepower switch 102. In addition, it should be understood by those skilled in the art that the output current IOUT of the secondary side SEC of thepower converter 100 can be determined by equation (3):
as shown in equation (3), NP is the number of turns of the primary winding 106 of the primary side PRI of thepower converter 100, and NS is the number of turns of the secondary winding 108 of the secondary side SEC of thepower converter 100. Since the sensing voltage VS across thesensing resistor 104 is determined by thesensing resistor 104, the on-time TON of thepower switch 102 and the current IPRI flowing through the primary side PRI of thepower converter 100, the peak voltage VPK of the sensing voltage VS is ideally determined by the sensing voltage VS and the on-time TON of thepower switch 102. However, because of the non-ideality of the sensing voltage VS (wherein the actual value of the sensing voltage VS may refer to the solid line shown in fig. 3 and the ideal value of the sensing voltage VS may refer to the dashed line shown in fig. 3), the actual peak voltage VPK is not equal to the ideal peak voltage VIPK, that is, the peak voltage VPK has an error. In addition, in practice, the discharge time TDIS of the secondary side SEC of thepower converter 100 is not ideal, that is, the start point and the end point of the discharge time TDIS cannot be accurately determined, so that the discharge time TDIS is not equal to the ideal discharge time, that is, the discharge time TDIS also has an error. Therefore, since the peak voltage VPK has an error and the discharge time TDIS also has an error, the output current IOUT actually varies with the output voltage VOUT of the secondary side SEC of the power converter 100 (as shown in fig. 4), where the vertical axis of fig. 4 is the output current IOUT and the horizontal axis of fig. 4 is the input voltage VAC of the primary side PRI of thepower converter 100.
Since the compensation voltage VCOMP is related to the output voltage VOUT and the gate control signal generating circuit can generate the gate control signal GCS to control the on-time TON of thepower switch 102 of thepower converter 100 according to the compensation voltage VCOMP, the on-time TON of thepower switch 102 is related to the output voltage VOUT. Since the on-time TON of thepower switch 102 is related to the output voltage VOUT, and the peak voltage VPK can be determined by the sensing voltage VS and the on-time TON of thepower switch 102, the peak voltage VPK is also related to the output voltage VOUT. In addition, since the discharge time TDIS of the secondary side SEC of thepower converter 100 is related to the on time TON of thepower switch 102, the discharge time TDIS is also related to the output voltage VOUT. Therefore, since the peak voltage VPK and the discharging time TDIS are both related to the output voltage VOUT, as shown in fig. 5, thecurrent compensation circuit 202 can generate a compensation current ICC to thesense resistor 104 according to a dc voltage VDC and an auxiliary voltage VZCD, wherein thecurrent compensation circuit 202 receives the auxiliary voltage VZCD through the pin ZCD of theprimary controller 200, the compensation current ICC flows to thesense resistor 104 through the pin CS of theprimary controller 200 during the on time TON of thepower switch 102, and the dc voltage VDC is related to the voltage VHV at the pin HV of the primary controller 200 (for example, the dc voltage VDC is divided by the voltage VHV). In addition, since the voltage VHV is related to the input voltage VAC, the direct-current voltage VDC is also related to the input voltage VAC. In addition, as shown in fig. 1, since the auxiliary voltage VZCD is related to the voltage VAUX generated by the auxiliary winding 103, the auxiliary voltage VZCD is also related to the output voltage VOUT. In addition, as shown in fig. 1, theprimary controller 200 receives the voltage VAUX through a pin VCC and adiode 110, and generates an operating voltage in theprimary controller 200 according to the voltage VAUX. In addition, as shown in fig. 1, theprimary controller 200 is grounded through a pin GND.
As shown in fig. 5, a Digital-to-Analog Converter (DAC) 2022 in thecurrent compensation circuit 202 can convert the auxiliary voltage VZCD into Digital signals DS1 and DS2, but the present invention is not limited to theDAC 2022 being a two-bit DAC. As shown in fig. 5, anoperational amplifier 20242, annmos transistor 20244 and aresistor 20246 in the compensationcurrent generating unit 2024 can determine a current IS according to the dc voltage VDC; then, a first current mirror composed ofpmos transistors 20248, 20250, 20252 in the compensationcurrent generating unit 2024 generates the compensation current ICC to thesensing resistor 104 according to the current IS and the digital signals DS1, DS 2. In addition, theoperational amplifier 20242, thenmos transistor 20244, theresistor 20246 and thepmos transistors 20248, 20250 and 20252 are coupled with reference to fig. 5, and are not described herein again. In addition, since thecurrent compensation circuit 202 generates the compensation current ICC based on the dc voltage VDC and the auxiliary voltage VZCD as shown in fig. 5, the compensation current ICC is related to both the input voltage VAC and the output voltage VOUT (since the dc voltage VDC is related to the input voltage VAC and the auxiliary voltage VZCD is related to the output voltage VOUT). In addition, as shown in fig. 1, because the compensation current ICC flows to thesensing resistor 104 through the pin CS of theprimary controller 200, the compensation current ICC changes the peak current IPK of the primary side PRI of thepower converter 100, wherein because the compensation current ICC is related to the input voltage VAC and the output voltage VOUT at the same time, the peak current IPK is also related to the input voltage VAC and the output voltage VOUT at the same time.
In addition, since the on-time TON of thepower switch 102 is also larger when the output voltage VOUT is higher, the influence of the error of the on-time TON of thepower switch 102 is smaller. Therefore, as shown in fig. 6, when the output voltage VOUT is higher (i.e., the auxiliary voltage VZCD is higher), the compensation current ICC is smaller, i.e., the compensation current ICC decreases with the increase of the output voltage VOUT. In addition, the present invention is not limited to the circuit architecture of thecurrent compensation circuit 202 in fig. 5, that is, a current compensation circuit that can make the compensation current ICC decrease with the increase of the output voltage VOUT falls into the scope of the present invention. In addition, the present invention is not limited to the compensationcurrent generating unit 2024 generating the compensation current ICC in a digital manner as shown in fig. 6, that is, in another embodiment of the present invention, the compensationcurrent generating unit 2024 generates the compensation current ICC in an analog manner. In addition, after the compensationcurrent generating unit 2024 generates the compensation current ICC to thesensing resistor 104, the relationship between the output current IOUT, the output voltage VOUT, and the input voltage VAC may be referred to fig. 7. As shown in fig. 7, although the curves corresponding to the output current IOUT (corresponding to different output voltages VOUT) are flat and consistent, there is an offset between the curves, wherein the offset is related to the smaller gain of the negative feedback loop of the constant current control in theprimary controller 200.
Equation (3) is that the negative feedback loop based on the constant current control has a sufficiently large gain, so when the negative feedback loop of the constant current control has a small gain, equation (3) must introduce a factor regarding the gain of the negative feedback loop into equation (4):
as shown in equation (4), GCC is the gain of the negative feedback loop. Further, formula (5) can be obtained by substituting formula (1) and formula (2) for formula (4):
as shown in equation (5), when the gain GCC of the negative feedback loop is small and the output voltage VOUT varies, the output current IOUT will vary with the output voltage VOUT, so the output current IOUT can be eliminated by adjusting the reference current IREF to eliminate the influence of the gain GCC of the negative feedback loop on the output current IOUT. In addition, as can also be seen from equation (5), the output current IOUT and the reference current IREF are positively correlated, so the reference current IREF provided by the referencecurrent source 2042 must be variable and vary with the output voltage VOUT of the secondary side SEC of thepower converter 100 to eliminate the offset between the curves.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating the referencecurrent source 2042. As shown in fig. 8, theoperational amplifiers 20422, 20424, thenmos 20426, 20428, thepmos 20430, and theresistor 20432 in the referencecurrent source 2042 determine a first current I1. As shown in fig. 8, a certain voltage vzcm is set according to the maximum value of the operating range of the output voltage VOUT, so that the first current I1 is inversely changed with the auxiliary voltage VZCD, that is, the first current I1 is decreased with the increase of the auxiliary voltage VZCD and the first current I1 is increased with the decrease of the auxiliary voltage VZCD. Since the auxiliary voltage VZCD is positively correlated with the output voltage VOUT, the first current I1 also varies inversely with the output voltage VOUT. Then, a second current mirror formed by thenmos 20428 and thenmos 20434 in the referencecurrent source 2042 can generate a second current I2 according to the first current I1, wherein the ratio of the width-to-length ratio of thenmos 20434 to the width-to-length ratio of thenmos 20428 and the first current I1 can determine the second current I2 according to equation (6), wherein the second current I2 inversely varies with the output voltage VOUT because the first current I1 inversely varies with the output voltage VOUT:
as shown in formula (6), (W/L)20434Is the width-to-length ratio of theNMOS transistor 20434, and (W/L)20428Is the width-to-length ratio ofnmos transistor 20428.
In addition, as shown in fig. 8, the referencecurrent source 2042 may utilize anoperational amplifier 20436, annmos 20438, aresistor 20440, a reference voltage VREF, and a second current I2 to determine a voltage VVO by equation (7), wherein acapacitor 20442 is used to stabilize the voltage VVO:
VVO=VREF-(R20440×I2) (7)
as shown in formula (7), R20440The resistance of theresistor 20440, wherein the voltage VVO increases with the increase of the output voltage VOUT when the output voltage VOUT increases because the second current I2 varies inversely with the output voltage VOUT, that is, the voltage VVO varies positively with the output voltage VOUT.
After the voltage VVO is generated, the referencecurrent source 2042 may generate the reference current IREF by using avoltage converter 20444. Because the voltage VVO varies in the forward direction with the output voltage VOUT, the reference current IREF also varies in the forward direction with the output voltage VOUT. Therefore, the offset shown in fig. 7 will be eliminated because the reference current IREF can be changed in the positive direction of the output voltage VOUT (as shown in fig. 9). Therefore, as shown in fig. 9, theprimary controller 200 can utilize the compensation current ICC generated by thecurrent compensation circuit 202 and the reference current IREF generated by the referencecurrent source 2042 to make the output current IOUT of the secondary side SEC of thepower converter 100 not change with the output voltage VOUT of the secondary side SEC of thepower converter 100. In addition, reference may be made to fig. 8 for the coupling relationship between theoperational amplifiers 20422, 20424, 20436, thenmos 20426, 20428, 20434, 20438, thepmos 20430, theresistors 20432, 20440, thecapacitor 20442 and the vsc, which is not described herein again. In addition, the present invention is not limited to the circuit architecture of the referencecurrent source 2042 in fig. 8, that is, any reference current source that can increase the reference current IREF with the increase of the output voltage VOUT is within the scope of the present invention.
Referring to fig. 1 to 10, fig. 10 is a flowchart illustrating an operation method of a primary controller applied to a primary side of a power converter according to a second embodiment of the present invention. The operation method of fig. 10 is illustrated by using thepower converter 100 and theprimary controller 200 of fig. 1, the compensationvoltage generating circuit 204 of fig. 2, the current compensatingcircuit 202 of fig. 5 and the referencecurrent source 2042 of fig. 8, and the detailed steps are as follows:
step 1000: starting;
step 1002: thecurrent compensation circuit 202 generates a compensation current ICC to thesense resistor 104 of the primary-side PRI of thepower converter 100 according to the dc voltage VDC and the auxiliary voltage VZCD;
step 1004: the compensationvoltage generation circuit 204 generates a compensation voltage VCOMP according to the reference current IREF, the discharge time TDIS of the secondary side SEC of thepower converter 100, and the peak current IPK;
step 1006: the gate control signal generating circuit generates the gate control signal GCS to thepower switch 102 of the primary-side PRI of thepower converter 100 according to the compensation voltage VCOMP, and then jumps back tostep 1002.
Instep 1002, as shown in fig. 5, thecurrent compensation circuit 202 may generate a compensation current ICC to thesensing resistor 104 according to the dc voltage VDC and the auxiliary voltage VZCD, wherein the compensation current ICC flows to thesensing resistor 104 through the pin CS of theprimary controller 200 during the on-time TON of thepower switch 102, and the dc voltage VDC is related to the voltage VHV at the pin HV of theprimary controller 200. In addition, since the voltage VHV is related to the input voltage VAC, the direct-current voltage VDC is also related to the input voltage VAC. In addition, as shown in fig. 1, since the auxiliary voltage VZCD is related to the voltage VAUX generated by the auxiliary winding 103, the auxiliary voltage VZCD is also related to the output voltage VOUT. As shown in fig. 5, the digital-to-analog converter 2022 in thecurrent compensation circuit 202 can convert the auxiliary voltage VZCD into digital signals DS1, DS 2. As shown in fig. 5, theoperational amplifier 20242, thenmos transistor 20244 and theresistor 20246 in the compensationcurrent generating unit 2024 can determine the current IS according to the dc voltage VDC; then, the first current mirror composed of thepmos transistors 20248, 20250, 20252 in the compensationcurrent generating unit 2024 can generate the compensation current ICC to thesensing resistor 104 according to the current IS and the digital signals DS1, DS 2. In addition, since thecurrent compensation circuit 202 generates the compensation current ICC based on the dc voltage VDC and the auxiliary voltage VZCD as shown in fig. 5, the compensation current ICC is related to both the input voltage VAC and the output voltage VOUT (since the dc voltage VDC is related to the input voltage VAC and the auxiliary voltage VZCD is related to the output voltage VOUT). In addition, as shown in fig. 1, because the compensation current ICC flows to thesensing resistor 104 through the pin CS of theprimary controller 200, the compensation current ICC changes the peak current IPK of the primary side PRI of thepower converter 100, wherein because the compensation current ICC is related to the input voltage VAC and the output voltage VOUT at the same time, the peak current IPK is also related to the input voltage VAC and the output voltage VOUT at the same time.
In addition, since the on-time TON of thepower switch 102 is also larger when the output voltage VOUT is higher, the influence of the error of the on-time TON of thepower switch 102 is smaller. Therefore, as shown in fig. 6, when the output voltage VOUT is higher (i.e., the auxiliary voltage VZCD is higher), the compensation current ICC is smaller, i.e., the compensation current ICC decreases with the increase of the output voltage VOUT. In addition, after the compensationcurrent generating unit 2024 generates the compensation current ICC to thesensing resistor 104, the relationship between the output current IOUT, the output voltage VOUT, and the input voltage VAC may be referred to fig. 7. As shown in fig. 7, although the curves corresponding to the output current IOUT (corresponding to different output voltages VOUT) are flat and consistent, there is an offset between the curves, wherein the offset is related to the smaller gain of the negative feedback loop of the constant current control in theprimary controller 200.
Instep 1004, as shown in fig. 8, theoperational amplifiers 20422, 20424, thenmos 20426, 20428, thepmos 20430, and theresistor 20432 in the referencecurrent source 2042 determine the first current I1. As shown in fig. 8, the constant voltage vzcm is set according to the maximum value of the operating range of the output voltage VOUT, so the first current I1 is inversely changed with the auxiliary voltage VZCD, that is, the first current I1 is decreased with the increase of the auxiliary voltage VZCD and the first current I1 is increased with the decrease of the auxiliary voltage VZCD. Since the auxiliary voltage VZCD is positively correlated with the output voltage VOUT, the first current I1 also varies inversely with the output voltage VOUT. Then, the second current mirror formed by thenmos 20428 and thenmos 20434 in the referencecurrent source 2042 can generate a second current I2 according to the first current I1, wherein the ratio of the width-to-length ratio of thenmos 20434 to the width-to-length ratio of thenmos 20428 and the first current I1 can determine the second current I2 by equation (6), and the second current I2 also inversely varies with the output voltage VOUT because the first current I1 inversely varies with the output voltage VOUT. In addition, as shown in fig. 8, the referencecurrent source 2042 may determine the voltage VVO by equation (7) using theoperational amplifier 20436, thenmos 20438, theresistor 20440, the reference voltage VREF, and the second current I2. Since the second current I2 varies inversely with the output voltage VOUT, when the output voltage VOUT increases, the voltage VVO increases with the increase of the output voltage VOUT, that is, the voltage VVO varies positively with the output voltage VOUT. Therefore, after the voltage VVO is generated, the referencecurrent source 2042 can generate the reference current IREF by using thevoltage converter 20444. Because the voltage VVO varies in the forward direction with the output voltage VOUT, the reference current IREF also varies in the forward direction with the output voltage VOUT. Then, as shown in fig. 2, the compensationvoltage generating circuit 204 can determine the compensation voltage VCOMP at the pin COMP of theprimary controller 200 by using the peak current IPK, the discharge time TDIS of the secondary side SEC of thepower converter 100, and the reference current IREF.
Instep 1006, after the compensation voltage VCOMP is generated, the gate control signal generating circuit (not shown in fig. 1 and 2) generates the gate control signal GCS to control thepower switch 102 of thepower converter 100 to turn on or off according to the compensation voltage VCOMP.
Therefore, as shown in fig. 9, after the compensation current ICC and the reference current IREF are generated, theprimary controller 200 can make the output current IOUT not change with the output voltage VOUT.
In summary, the primary controller applied to the primary side of the power converter and the operating method thereof disclosed by the present invention utilize the compensation current generated by the current compensation circuit and varying in a reverse direction with respect to the output voltage and the reference current generated by the reference current source and varying in a forward direction with respect to the output voltage to make the output current not vary with the output voltage. Therefore, compared with the prior art, the compensation current and the reference current are related to the output voltage, so the invention can effectively eliminate the influence of the output voltage on the output current.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.