CN112117192A

Movatterモバイル変換

Info

Publication number: CN112117192A
Application number: CN201910545011.0A
Authority: CN
Inventors: 张海洋; 郑二虎; 洪中山
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-06-21
Filing date: 2019-06-21
Publication date: 2020-12-22
Anticipated expiration: 2039-06-21
Also published as: CN112117192B

Abstract

Translated fromChinese

一种半导体结构的形成方法，包括：提供衬底，所述衬底上具有分立排列的第一鳍部以及第二鳍部；在所述衬底上形成隔离层，所述隔离层填充满所述第一鳍部及所述第二鳍部间的间隙，且所述隔离层的顶部与所述第一鳍部和第二鳍部的顶部齐平；在所述第一鳍部上形成掩膜层，且所述掩膜层覆盖所述隔离层顶部的部分表面；以所述掩膜层为掩膜，采用原子层刻蚀工艺刻蚀所述隔离层，使得刻蚀所述隔离层时不会偏移，不会损害所述第一鳍部。进一步，也可以将所述第二鳍部完全去除干净，使得最终形成鳍部均匀，半导体器件性能得到提升。

A method for forming a semiconductor structure, comprising: providing a substrate having discretely arranged first fins and second fins; forming an isolation layer on the substrate, the isolation layer filling all a gap between the first fin and the second fin, and the top of the isolation layer is flush with the top of the first fin and the second fin; a mask is formed on the first fin film layer, and the mask layer covers part of the surface of the top of the isolation layer; using the mask layer as a mask, the isolation layer is etched by the atomic layer etching process, so that when the isolation layer is etched No offset, no damage to the first fin. Further, the second fin portion can also be completely removed, so that the final fin portion is formed uniformly and the performance of the semiconductor device is improved.

Description

Translated fromChinese

半导体结构的形成方法Method of forming a semiconductor structure

技术领域technical field

本发明涉及半导体制作领域，特别涉及一种半导体结构的形成方法。The invention relates to the field of semiconductor fabrication, in particular to a method for forming a semiconductor structure.

背景技术Background technique

随着半导体制造技术的飞速发展，半导体器件朝着更高元件密度以及更高集成度的方向发展，平面晶体管的栅极尺寸越来越小，从而栅极对沟道电流的控制能力变弱，容易产生短沟道效应，造成漏电流问题，进而影响半导体器件的电学性能。With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing in the direction of higher component density and higher integration. It is easy to produce short channel effect, causing leakage current problem, which in turn affects the electrical performance of semiconductor devices.

为了克服晶体管的短沟道效应，抑制漏电流，现有技术提出了鳍式场效晶体管(Fin FET)，鳍式场效应晶体管时一种常见的多栅器件，鳍式场效应晶体管的结构包括：位于半导体衬底表面的鳍部和介质层，所述介质层覆盖部分所述鳍部的侧壁，且介质层表面低于鳍部顶部；位于介质层表面，以及鳍部的顶部和侧壁表面的栅极结构；位于所述栅极结构两侧的鳍部内的源区和漏区。In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fin field effect transistor (Fin FET), which is a common multi-gate device. The structure of the fin field effect transistor includes: : The fin and the dielectric layer are located on the surface of the semiconductor substrate, the dielectric layer covers part of the sidewall of the fin, and the surface of the dielectric layer is lower than the top of the fin; located on the surface of the dielectric layer, and the top and sidewalls of the fin Surface gate structure; source and drain regions within the fins on both sides of the gate structure.

然而，随着半导体器件的密度提高，尺寸缩小，鳍式场效应晶体管构成的半导体器件的电学性能和良率仍有待提高。However, as the density and size of semiconductor devices are increased, the electrical properties and yields of semiconductor devices formed by fin field effect transistors still need to be improved.

发明内容SUMMARY OF THE INVENTION

本发明解决的问题是提供一种半导体结构的形成方法，能够使得半导体器件的性能提高良率改善。The problem solved by the present invention is to provide a method for forming a semiconductor structure, which can improve the performance of the semiconductor device and improve the yield.

为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供衬底，所述衬底上具有分立排列的第一鳍部以及第二鳍部；在所述衬底上形成隔离层，所述隔离层填充满所述第一鳍部及所述第二鳍部间的间隙，且所述隔离层的顶部与所述第一鳍部和第二鳍部的顶部齐平；在所述第一鳍部上形成掩膜层，且所述掩膜层覆盖所述隔离层顶部的部分表面；以所述掩膜层为掩膜，采用原子层刻蚀工艺刻蚀所述隔离层至露出所述衬底；去除所述第二鳍部。In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having discretely arranged first fins and second fins; and forming an isolation layer on the substrate , the isolation layer fills the gap between the first fin and the second fin, and the top of the isolation layer is flush with the top of the first fin and the second fin; A mask layer is formed on the first fin, and the mask layer covers part of the surface of the top of the isolation layer; using the mask layer as a mask, the isolation layer is etched by an atomic layer etching process to exposing the substrate; removing the second fin.

可选的，所述原子层刻蚀工艺的参数为：刻蚀气体包括He、NH₃和NF₃，刻蚀腔室压强为2torr至10torr，NH₃流量为200sccm至500sccm，NF₃流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。Optionally, the parameters of the atomic layer etching process are: the etching gas includes He, NH₃ and NF₃ , the pressure of the etching chamber is 2torr to 10torr, the flow rate of NH₃ is 200sccm to 500sccm, and the flow rate of NF₃ is 20sccm to 200 sccm, the He flow rate was 600 sccm to 2000 sccm, and the etching time was 20 s to 100 s.

可选的，所述隔离层的材料为氧化硅、碳氧化硅、碳氮氧化硅或氮氧化硅。Optionally, the material of the isolation layer is silicon oxide, silicon oxycarbide, silicon oxycarbonitride or silicon oxynitride.

可选的，在所述衬底上形成隔离层的工艺包括：化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。Optionally, the process of forming the isolation layer on the substrate includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

可选的，所述掩膜层的材料为氮化硅或碳氧化硅、碳氮氧化硅或氮氧化硅。Optionally, the material of the mask layer is silicon nitride or silicon oxycarbide, silicon oxycarbonitride or silicon oxynitride.

可选的，在形成所述隔离层之前，还包括：在所述第一鳍部和所述第二鳍部顶部表面形成保护层。Optionally, before forming the isolation layer, the method further includes: forming a protective layer on the top surfaces of the first fin and the second fin.

可选的，所述保护层的材料为氮化硅。Optionally, the material of the protective layer is silicon nitride.

可选的，去除所述第二鳍部与刻蚀所述隔离层同步进行。Optionally, removing the second fin is performed simultaneously with etching the isolation layer.

可选的，采用原子层刻蚀工艺去除所述第二鳍部。Optionally, an atomic layer etching process is used to remove the second fin.

可选的，去除所述第二鳍部工艺在刻蚀所述隔离层之后进行。Optionally, the process of removing the second fin is performed after etching the isolation layer.

可选的，去除所述第二鳍部的工艺为鳍部切割工艺。Optionally, the process of removing the second fin is a fin cutting process.

可选的，去除所述第二鳍部之后，还包括：去除所述掩膜层，以所述第一鳍部及剩余的所述隔离层为掩膜，刻蚀所述衬底，形成凹槽；继续以所述第一鳍部及剩余的所述隔离层为掩膜，沿所述凹槽刻蚀所述衬底，加宽所述凹槽。Optionally, after removing the second fin, the method further includes: removing the mask layer, and using the first fin and the remaining isolation layer as masks, etching the substrate to form a concave groove; continue to use the first fin and the remaining isolation layer as a mask to etch the substrate along the groove to widen the groove.

可选的，形成所述凹槽的工艺为干法刻蚀，工艺参数为：刻蚀气体包括He、NH₃和NF₃，刻蚀腔室压强为2torr至10torr，NH₃流量为200sccm至500sccm，NF₃流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。Optionally, the process of forming the groove is dry etching, and the process parameters are: the etching gas includes He, NH₃ and NF₃ , the pressure of the etching chamber is 2torr to 10torr, and the flow rate of NH₃ is 200sccm to 500sccm , the NF₃ flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.

可选的，采用回刻蚀的方法横向加宽所述凹槽，工艺参数为：气体包括He、NH₃和NF₃，刻蚀腔室压强为2torr至10torr，NH₃流量为200sccm至500sccm，NF₃流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。Optionally, the groove is laterally widened by an etch-back method, and the process parameters are: the gas includes He, NH₃ and NF₃ , the pressure of the etching chamber is 2torr to 10torr, and the flow rate of NH₃ is 200sccm to 500sccm, The NF₃ flow rate was 20sccm to 200sccm, the He flow rate was 600sccm to 2000sccm, and the etching time was 20 s to 100 s.

与现有技术相比，本发明的技术方案具有以下优点：Compared with the prior art, the technical solution of the present invention has the following advantages:

所述隔离层的顶部与所述第一鳍部和第二鳍部的顶部齐平，避免形成所述掩膜层偏移。掩膜层覆盖所述隔离层顶部的部分表面；以所述掩膜层为掩膜，采用原子层刻蚀工艺刻蚀所述隔离层，所述原子层刻蚀工艺刻蚀的定向性良好，使得刻蚀所述隔离层时不会偏移，不会损害所述第一鳍部，利于将所述第二鳍部完全去除干净；进而使得最终形成鳍部均匀，半导体器件性能得到提升。The tops of the isolation layers are flush with the tops of the first and second fins to avoid forming the mask layer offset. A mask layer covers part of the surface of the top of the isolation layer; using the mask layer as a mask, the isolation layer is etched by an atomic layer etching process, and the etching direction of the atomic layer etching process is good, The isolation layer will not be offset and the first fin will not be damaged when etching the isolation layer, so that the second fin will be completely removed; further, the final fin will be formed uniformly, and the performance of the semiconductor device will be improved.

附图说明Description of drawings

图1至图3是一种半导体结构的形成方法各步骤的结构示意图；1 to 3 are schematic structural diagrams of each step of a method for forming a semiconductor structure;

图4至图11是本发明一实施例的半导体结构的形成过程的结构示意图；4 to 11 are schematic structural diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention;

图12至图15是本发明另一实施例的半导体结构的形成过程的结构示意图。FIG. 12 to FIG. 15 are schematic structural diagrams of a process of forming a semiconductor structure according to another embodiment of the present invention.

具体实施方式Detailed ways

如背景技术所述，随着半导体器件的密度提高，尺寸缩小，所形成的鳍式场效应晶体管的性能差，可靠性低。以下将结合附图进行说明。As described in the background art, as the density of semiconductor devices increases and the size decreases, the formed fin field effect transistors have poor performance and low reliability. The following description will be made with reference to the accompanying drawings.

图1至图3是一种半导体结构的形成过程的剖面结构示意图。FIG. 1 to FIG. 3 are schematic cross-sectional structural views of a process of forming a semiconductor structure.

参考图1，提供衬底100，所述衬底100上具有分立排列的第一鳍部101以及第二鳍部102。所述第一鳍部101位于第二鳍部102周围。Referring to FIG. 1 , asubstrate 100 is provided, and thesubstrate 100 has a firstfin portion 101 and a secondfin portion 102 arranged in a discrete manner thereon. Thefirst fins 101 are located around thesecond fins 102 .

参考图2，在所述衬底100上形成一层介质层103，所述介质层103的材料为旋涂碳(SoC)，所述介质层103覆盖所述第一鳍部101与所述第二鳍部102，且所述介质层103填充满所述第一鳍部101和第二鳍部102的间隙。Referring to FIG. 2 , adielectric layer 103 is formed on thesubstrate 100 , thedielectric layer 103 is made of spin-on carbon (SoC), and thedielectric layer 103 covers thefirst fins 101 and thefirst fins 101 . Twofins 102 , and thedielectric layer 103 fills the gap between thefirst fin 101 and thesecond fin 102 .

在所述介质层103上表面形成抗反射层(Si-ARC)104，且所述抗反射层104覆盖所述介质层103顶部的部分表面；在所述抗反射层104上表面形成光刻胶层105。An anti-reflection layer (Si-ARC) 104 is formed on the upper surface of thedielectric layer 103, and theanti-reflection layer 104 covers part of the surface of the top of thedielectric layer 103; a photoresist is formed on the upper surface of theanti-reflection layer 104Layer 105.

参考图3，以所述光刻胶层105以及所述抗反射层104为掩膜，刻蚀所述介质层103，并去除所述第二鳍部102。Referring to FIG. 3 , using thephotoresist layer 105 and theanti-reflection layer 104 as masks, thedielectric layer 103 is etched, and thesecond fins 102 are removed.

需要说明的是，所述第一鳍部101是用于形成器件所需的有效鳍部，所述第二鳍部102是为了克服负载效应而额外形成的伪鳍部。需要去除伪鳍部，即需要去除所述第二鳍部102。It should be noted that thefirst fin portion 101 is an effective fin portion required for forming a device, and thesecond fin portion 102 is an additional dummy fin portion formed to overcome the load effect. The dummy fins need to be removed, that is, thesecond fins 102 need to be removed.

经研究发现，在去除所述第二鳍部102的过程中，是以所述光刻胶层105以及所述抗反射层104为掩膜，刻蚀所述介质层103，由于在形成所述光刻胶层105以及所述抗反射层104之前，所述介质层103完全覆盖所述第一鳍部101以及所述第二鳍部102的顶部，在形成所述光刻胶层105以及所述抗反射层104时，有可能会出现光感偏差，发生偏移；同时，传统的刻蚀工艺在向下更深处刻蚀时，蚀刻设备中电极在高温高压下激发等离子体定向轰击以刻蚀所述介质层103，可是过程中难以避免的会发生偏移，最终导致刻蚀后所述第一鳍部101的部分材料被刻蚀，所述第一鳍部101的形貌受损，并且需要被刻蚀掉的所述第二鳍部102的部分材料剩余，造成最终的鳍部宽度不一，进而影响鳍式场效应晶体管的性能。It has been found through research that in the process of removing thesecond fin 102, thephotoresist layer 105 and theanti-reflection layer 104 are used as masks to etch thedielectric layer 103. Before thephotoresist layer 105 and theanti-reflection layer 104, thedielectric layer 103 completely covers the tops of thefirst fins 101 and thesecond fins 102. When theanti-reflection layer 104 is described, there may be photosensitive deviation and offset; at the same time, when the traditional etching process is etched further down, the electrodes in the etching equipment excite plasma directional bombardment under high temperature and high pressure to etch Thedielectric layer 103 is etched, but it is unavoidable that a shift will occur during the process, which eventually causes part of the material of thefirst fins 101 to be etched after the etching, and the shape of thefirst fins 101 is damaged. In addition, part of the material of thesecond fin portion 102 that needs to be etched away remains, resulting in different widths of the final fin portion, thereby affecting the performance of the fin field effect transistor.

为了解决上述技术问题，本发明通过在所述衬底上形成隔离层，所述隔离层填充满所述第一鳍部及所述第二鳍部间的间隙，且所述隔离层的顶部与所述第一鳍部和第二鳍部的顶部齐平；在所述第一鳍部上形成掩膜层，且所述掩膜层覆盖所述隔离层顶部的部分表面；所述隔离层的顶部与所述第一鳍部和第二鳍部的顶部齐平，避免形成所述掩膜层偏移。以所述掩膜层为掩膜，采用原子层刻蚀工艺刻蚀所述隔离层至露出所述衬底；所述原子层刻蚀工艺垂直方向的蚀刻速率远大于横向的蚀刻速率，使得刻蚀所述隔离层时不会偏移，不会损害所述第一鳍部，进一步，也可以将所述第二鳍部完全去除干净。使得最终形成鳍部均匀，器件性能得到提升。In order to solve the above technical problem, the present invention forms an isolation layer on the substrate, the isolation layer fills the gap between the first fin and the second fin, and the top of the isolation layer is connected to the The tops of the first fin and the second fin are flush; a mask layer is formed on the first fin, and the mask layer covers part of the surface of the top of the isolation layer; The tops are flush with the tops of the first and second fins to avoid forming the mask layer offset. Using the mask layer as a mask, an atomic layer etching process is used to etch the isolation layer until the substrate is exposed; the vertical etching rate of the atomic layer etching process is much greater than the lateral etching rate, so that the etching The isolation layer will not be offset during etching, and the first fins will not be damaged. Further, the second fins can also be completely removed. The fins are finally formed uniformly, and the performance of the device is improved.

为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

第一实施例first embodiment

图4至图11是本发明一实施例的半导体结构的形成过程的结构示意图。4 to 11 are schematic structural diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention.

参考图4，提供衬底200，所述衬底200上具有分立排列的第一鳍部201以及第二鳍部202；在所述第一鳍部201和所述第二鳍部202顶部表面形成保护层300。Referring to FIG. 4 , asubstrate 200 is provided, and thesubstrate 200 has discretely arranged first fins 201 andsecond fins 202 ; formed on top surfaces of thefirst fins 201 and thesecond fins 202Protective layer 300 .

所述衬底200、第一鳍部201、第二鳍部202以及所述保护层300的形成步骤包括：提供半导体基底(图未示)；在所述半导体基底上形成第一图形化掩膜层(图未示)。所述第一图形化掩膜层定义第一鳍部201和第二鳍部202的位置和形状；以所述第一图形化掩膜层为掩膜，刻蚀所述半导体基底，形成所述衬底200、第一鳍部201、第二鳍部202以及位于第一鳍部201和第二鳍部202顶部的所述保护层300。The steps of forming thesubstrate 200 , thefirst fin portion 201 , thesecond fin portion 202 and theprotective layer 300 include: providing a semiconductor substrate (not shown); forming a first patterning mask on the semiconductor substrate layer (not shown). The first patterned mask layer defines the position and shape of thefirst fin portion 201 and thesecond fin portion 202; using the first patterned mask layer as a mask, the semiconductor substrate is etched to form the Thesubstrate 200 , thefirst fins 201 , thesecond fins 202 , and theprotective layer 300 on top of the first andsecond fins 201 and 202 .

所述半导体基底的材料包括硅、锗、锗化硅、砷化镓、铟镓砷等半导体材料，其中硅材料包括单晶硅、多晶硅或非晶硅。所述半导体基底还能够是绝缘体上半导体结构，所述绝缘体上半导体结构包括绝缘体及位于绝缘体上的半导体材料层，所述半导体材料层的材料包括硅、锗、锗化硅、砷化镓、铟镓砷等半导体材料。The material of the semiconductor substrate includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, etc., wherein the silicon material includes single crystal silicon, polycrystalline silicon or amorphous silicon. The semiconductor substrate can also be a semiconductor-on-insulator structure, and the semiconductor-on-insulator structure includes an insulator and a semiconductor material layer on the insulator, and the material of the semiconductor material layer includes silicon, germanium, silicon germanium, gallium arsenide, indium Semiconductor materials such as gallium arsenide.

在本实施例中，所述半导体基底的材料为单晶硅。即所述衬底200、第一鳍部201、以及第二鳍部202的材料为单晶硅。In this embodiment, the material of the semiconductor substrate is single crystal silicon. That is, thesubstrate 200 , thefirst fins 201 and thesecond fins 202 are made of single crystal silicon.

本实施例中，所述保护层300用于后续对隔离层进行平坦化时，保护所述第一鳍部201和第二鳍部202的顶部不受损伤，同时也作为后续隔离层平坦化时的终止层。In this embodiment, theprotective layer 300 is used to protect the tops of thefirst fins 201 and thesecond fins 202 from damage when the isolation layer is subsequently planarized, and also serves as a subsequent planarization of the isolation layer. terminating layer.

本实施例中，所述第一图形化掩膜层的形成工艺为化学气相沉积工艺。其他实施例中，所述第一图像化掩膜层的形成工艺还可以是物理气相沉积工艺或原子层沉积工艺。In this embodiment, the formation process of the first patterned mask layer is a chemical vapor deposition process. In other embodiments, the formation process of the first imaged mask layer may also be a physical vapor deposition process or an atomic layer deposition process.

本实施例中，所述保护层300的材料为氮化硅。其他实施例中，所述保护层300的材料包括氮碳化硅、氮硼化硅、氮碳氧化硅或氮氧化硅。In this embodiment, the material of theprotective layer 300 is silicon nitride. In other embodiments, the material of theprotective layer 300 includes silicon nitride carbide, silicon boron nitride, silicon oxynitride or silicon oxynitride.

在其他实施例中，所述衬底200、第一鳍部201、以及第二鳍部211的形成步骤还包括：提供半导体基底(未图示)，在所述半导体基底上先形成初始保护层，在所述初始保护层上形成图形化层，以所述图形化层为掩膜，刻蚀所述初始保护层和所述半导体基底，以形成所述第一鳍部201、第二鳍部211以及位于第一鳍部201和第二鳍部211顶部的保护层300。In other embodiments, the steps of forming thesubstrate 200 , thefirst fins 201 and the second fins 211 further include: providing a semiconductor base (not shown), and first forming an initial protective layer on the semiconductor base , forming a patterned layer on the initial protective layer, and using the patterned layer as a mask to etch the initial protective layer and the semiconductor substrate to form thefirst fin portion 201 and the second fin portion 211 and theprotective layer 300 on top of thefirst fins 201 and the second fins 211 .

参考图5，在所述衬底200上形成隔离层400。所述隔离层400填充满所述第一鳍部201及所述第二鳍部202间的间隙。具体的，所述隔离层400覆盖所述第一鳍部201和第二鳍部202的侧壁，且暴露出所述第一鳍部201和第二鳍部202的顶部表面。Referring to FIG. 5 , anisolation layer 400 is formed on thesubstrate 200 . Theisolation layer 400 fills the gap between thefirst fin portion 201 and thesecond fin portion 202 . Specifically, theisolation layer 400 covers the sidewalls of thefirst fins 201 and thesecond fins 202 and exposes the top surfaces of thefirst fins 201 and thesecond fins 202 .

所述隔离层400的形成步骤包括：在所述衬底200上形成隔离层400，所述隔离层400覆盖所述第一鳍部201和第二鳍部211的顶部表面；平坦化所述隔离层400。The steps of forming theisolation layer 400 include: forming anisolation layer 400 on thesubstrate 200, theisolation layer 400 covering the top surfaces of thefirst fins 201 and the second fins 211; planarizing theisolation Layer 400.

本实施例中，所述隔离层400的材料为氧化硅；其他实施例中，所述隔离层400的材料还可以是碳氧化硅、碳氮氧化硅或氮氧化硅。In this embodiment, the material of theisolation layer 400 is silicon oxide; in other embodiments, the material of theisolation layer 400 may also be silicon oxycarbide, silicon oxycarbonitride or silicon oxynitride.

所述隔离层400的形成工艺为流体化学气相沉积工艺(Flowable Chemical VaporDeposition，简称FCVD)。所述流体化学气相沉积的工艺步骤包括：在所述衬底200上形成含硅的前驱体，所述含硅的前驱体覆盖所述第一鳍部201和第二鳍部202；对所述含硅的前驱体进行氧化处理形成初始隔离层(图未示)；对所述初始隔离层进行退火处理形成隔离层400。The formation process of theisolation layer 400 is a fluid chemical vapor deposition process (Flowable Chemical Vapor Deposition, FCVD for short). The process steps of the fluid chemical vapor deposition include: forming a silicon-containing precursor on thesubstrate 200, the silicon-containing precursor covering thefirst fin portion 201 and thesecond fin portion 202; The precursor containing silicon is oxidized to form an initial isolation layer (not shown); the initial isolation layer is annealed to form anisolation layer 400 .

在其他实施例中，所述隔离层400还能够采用等离子体增强化学气相沉积工艺(PECVD)或者高深宽比化学气相沉积工艺(HARP)。In other embodiments, theisolation layer 400 can also adopt plasma enhanced chemical vapor deposition (PECVD) or high aspect ratio chemical vapor deposition (HARP).

所述平坦化工艺为化学机械抛光工艺(CMP)；在本实施例中，所述化学机械抛光工艺直至暴露出所述第一鳍部201和第二鳍部202的顶部的保护层300。The planarization process is a chemical mechanical polishing process (CMP); in this embodiment, the chemical mechanical polishing process is performed until theprotective layer 300 on the tops of thefirst fins 201 and thesecond fins 202 is exposed.

参考图6，在所述第一鳍部201上形成掩膜层500，且所述掩膜层500覆盖所述隔离层400顶部的部分表面。Referring to FIG. 6 , amask layer 500 is formed on thefirst fin portion 201 , and themask layer 500 covers a part of the surface of the top of theisolation layer 400 .

所述掩膜层500的形成步骤包括：在所述保护层300以及所述隔离层400顶部表面形成初始掩膜层(未图示)，在所述初始掩膜层上表面形成图形化光刻胶，所述图形化光刻胶定义第二鳍部202的位置和形状，以所述图形化光刻胶为掩膜刻蚀所述初始掩膜层，形成所述掩膜层500。The steps of forming themask layer 500 include: forming an initial mask layer (not shown) on the top surface of theprotective layer 300 and theisolation layer 400 , and forming a patterned lithography on the upper surface of the initial mask layer The patterned photoresist defines the position and shape of thesecond fins 202 , and the initial mask layer is etched using the patterned photoresist as a mask to form themask layer 500 .

本实施例中，所述掩膜层500的形成工艺为化学气相沉积工艺；其他实施例中，所述掩膜层500的形成工艺还可以是物理气相沉积工艺或原子层沉积工艺。In this embodiment, the formation process of themask layer 500 is a chemical vapor deposition process; in other embodiments, the formation process of themask layer 500 may also be a physical vapor deposition process or an atomic layer deposition process.

本实施例中，所述掩膜层500的材料为氮化硅或碳氧化硅、碳氮氧化硅或氮氧化硅。In this embodiment, the material of themask layer 500 is silicon nitride or silicon oxycarbide, silicon oxycarbonitride or silicon oxynitride.

本实施例中，所述掩膜层500的材料为氮化硅，所述掩膜层500的厚度为3nm～5nm。In this embodiment, the material of themask layer 500 is silicon nitride, and the thickness of themask layer 500 is 3 nm˜5 nm.

参考图7，以所述掩膜层500为掩膜，采用原子层刻蚀(ALE)工艺刻蚀所述隔离层400至露出所述衬底200以及所述第二鳍部202的侧壁表面。Referring to FIG. 7 , using themask layer 500 as a mask, theisolation layer 400 is etched by an atomic layer etching (ALE) process to expose thesubstrate 200 and the sidewall surfaces of thesecond fins 202 .

采用原子层刻蚀工艺对所述隔离层400进行刻蚀时，以一种有序的方式在原子尺度逐层去除材料，能够实现定向刻蚀和高选择比，即使深宽比不同的情况下，也能实现等量刻蚀，能够实现精准控制。When theisolation layer 400 is etched by the atomic layer etching process, the material is removed layer by layer at the atomic scale in an orderly manner, which can achieve directional etching and high selectivity, even in the case of different aspect ratios , can also achieve the same amount of etching, can achieve precise control.

本实施例中，控制所述原子层刻蚀工艺参数，使得以所述掩膜层500为掩膜刻蚀所述隔离层400时，垂直的将待刻蚀掉的部分所述隔离层去除。In this embodiment, the atomic layer etching process parameters are controlled so that when theisolation layer 400 is etched using themask layer 500 as a mask, the part of the isolation layer to be etched is removed vertically.

本实施例中，所述原子层刻蚀工艺参数包括：刻蚀气体包括He、NH₃和NF₃，刻蚀腔室压强为2torr至10torr，NH₃流量为200sccm至500sccm，NF₃流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。In this embodiment, the atomic layer etching process parameters include: the etching gas includes He, NH₃ and NF₃ , the pressure of the etching chamber is 2torr to 10torr, the flow rate of NH₃ is 200sccm to 500sccm, and the flow rate of NF₃ is 20sccm to 200 sccm, the He flow rate was 600 sccm to 2000 sccm, and the etching time was 20 s to 100 s.

参考图8，去除所述掩膜层500(参考图7)。Referring to FIG. 8, the mask layer 500 (refer to FIG. 7) is removed.

本实施例中，去除所述掩膜层500的工艺为湿法刻蚀的方法。所述湿法刻蚀工艺的刻蚀溶液为稀释的氢氟酸溶液；其中，HF与H₂O的体积比为1/1000～1/100。In this embodiment, the process of removing themask layer 500 is a wet etching method. The etching solution of the wet etching process is a diluted hydrofluoric acid solution; wherein, the volume ratio of HF to H₂ O is 1/1000-1/100.

参考图9，去除所述第二鳍部202(参考图8)，形成开口401。Referring to FIG. 9 , the second fins 202 (refer to FIG. 8 ) are removed to formopenings 401 .

本实施例中，去除所述第二鳍部202并形成开口401的工艺为鳍部切割工艺，包括：干法刻蚀工艺或湿法刻蚀工艺的一种或多种组合。In this embodiment, the process of removing thesecond fins 202 and forming theopenings 401 is a fin cutting process, including one or more combinations of dry etching processes or wet etching processes.

本实施例中，所述鳍部切割工艺为干法刻蚀工艺，所述干法刻蚀的工艺参数包括：采用的刻蚀气体包括HBr和Ar，其中，HBr的流速为10sccm～1000sccm，Ar的流速为10sccm～1000sccm。In this embodiment, the fin cutting process is a dry etching process, and the process parameters of the dry etching include: the used etching gas includes HBr and Ar, wherein the flow rate of HBr is 10 sccm to 1000 sccm, and the flow rate of Ar The flow rate is 10sccm ~ 1000sccm.

在其他实施例中，刻蚀去除的工艺参数包括：刻蚀气体为HBr、O₂和Cl₂，还向刻蚀腔室内通入He，刻蚀腔室压强为2毫托至50毫托，刻蚀的源功率为200瓦至2000瓦，刻蚀加偏压功率为10瓦至100瓦，HBr流量为50sccm至500sccm，O₂流量为2sccm至20sccm，Cl₂流量为10sccm至300sccm，He流量为50sccm至500sccm。In other embodiments, the process parameters for etching and removing include: the etching gas is HBr, O₂ and Cl₂ , and He is also introduced into the etching chamber, and the pressure of the etching chamber is 2 mtorr to 50 mtorr, The source power for etching is 200 watts to 2000 watts, the etch plus bias power is 10 watts to 100 watts, the HBr flow rate is 50sccm to 500sccm, the_O2 flow rate is 2sccm to_20sccm , the Cl2 flow rate is 10sccm to 300sccm, and the He flow rate is 50sccm to 500sccm.

其他实施例中，也可以采用湿法刻蚀工艺去除所述第二鳍部202。所述湿法刻蚀的工艺采用的刻蚀溶液可以是四甲基氢氧化氨(TMAH)溶液或KOH溶液。In other embodiments, thesecond fin portion 202 may also be removed by a wet etching process. The etching solution used in the wet etching process may be a tetramethylammonium hydroxide (TMAH) solution or a KOH solution.

湿法刻蚀溶液为四甲基氢氧化铵溶液，四甲基氢氧化铵溶液对硅和氧化硅具有很好的刻蚀选择比，在去除所述第二鳍部202的条件下对侧壁的氧化硅没有影响，能够保证形成所述开口401的形貌完整。The wet etching solution is a tetramethyl ammonium hydroxide solution. The tetramethyl ammonium hydroxide solution has a good etching selectivity ratio to silicon and silicon oxide. The silicon oxide has no influence, which can ensure that the topography of theopening 401 is complete.

需要说明的是，在其他实施例中，可以在去除所述第二鳍部202之后，再去除所述掩膜层500。It should be noted that, in other embodiments, themask layer 500 may be removed after thesecond fin portion 202 is removed.

参考图10，以所述开口401为掩膜，刻蚀所述衬底200，形成凹槽402。Referring to FIG. 10 , using theopening 401 as a mask, thesubstrate 200 is etched to form agroove 402 .

所述开口401是由所述第一鳍部201及剩余的所述隔离层400围成的。沿所述401向所述衬底200进行刻蚀目的是增大所述第一鳍部201之间的绝缘性，提高半导体的器件性能。Theopening 401 is surrounded by thefirst fin 201 and the rest of theisolation layer 400 . The purpose of etching thesubstrate 200 along the 401 is to increase the insulation between thefirst fins 201 and improve the device performance of the semiconductor.

形成所述凹槽402的工艺为干法刻蚀，工艺参数为：刻蚀气体包括He、NH3和NF3，刻蚀腔室压强为2torr至10torr，NH3流量为200sccm至500sccm，NF3流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。The process for forming thegroove 402 is dry etching, and the process parameters are: the etching gas includes He, NH3 and NF3, the pressure of the etching chamber is 2torr to 10torr, the flow rate of NH3 is 200sccm to 500sccm, and the flow rate of NF3 is 20sccm to 20 torr. 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.

参考图11，继续以所述开口401为掩膜，沿所述凹槽402刻蚀所述衬底，加宽所述凹槽402。Referring to FIG. 11 , continuing to use theopening 401 as a mask, the substrate is etched along thegroove 402 to widen thegroove 402 .

采用回刻蚀的方法横向加宽所述凹槽，工艺参数为：刻蚀气体包括He、NH₃和NF₃，刻蚀腔室压强为2torr至10torr，NH₃流量为200sccm至500sccm，NF₃流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。The groove is laterally widened by an etch-back method. The process parameters are: the etching gas includes He, NH₃ and NF₃ , the pressure of the etching chamber is 2torr to 10torr, the flow rate of NH₃ is 200sccm to 500sccm, and the NF₃ The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.

加宽所述凹槽402的目的是进一步隔离所述第一鳍部201，提高所述第一鳍部201之间的绝缘性，进一步提高所述半导体器件的性能。The purpose of widening thegrooves 402 is to further isolate thefirst fins 201 , improve the insulation between thefirst fins 201 , and further improve the performance of the semiconductor device.

第二实施例Second Embodiment

本实施例与第一实施例的区别在于形成所述开口401的过程不同，如下将对区别部分进行详细叙述。The difference between this embodiment and the first embodiment is that the process of forming theopening 401 is different, and the difference will be described in detail below.

参考图12，提供所述衬底200，所述衬底200上具有分立排列的第一鳍部201以及第二鳍部202；在所述第一鳍部201和所述第二鳍部202顶部表面形成保护层300；在所述衬底200上形成隔离层400，所述隔离层400填充满所述第一鳍部201及所述第二鳍部202间的间隙，所述隔离层400顶部表面与所述第一鳍部201及所述第二鳍部202顶部表面齐平；在所述第一鳍部201上形成掩膜层500，且所述掩膜层500覆盖所述隔离层400顶部的部分表面。Referring to FIG. 12 , thesubstrate 200 is provided, and thesubstrate 200 has discretely arrangedfirst fins 201 andsecond fins 202 ; on top of thefirst fins 201 and the second fins 202 Aprotective layer 300 is formed on the surface; anisolation layer 400 is formed on thesubstrate 200 , theisolation layer 400 fills the gap between thefirst fin 201 and thesecond fin 202 , and the top of theisolation layer 400 The surface is flush with the top surfaces of thefirst fins 201 and thesecond fins 202 ; amask layer 500 is formed on thefirst fins 201 , and themask layer 500 covers theisolation layer 400 part of the top surface.

本实施例中，所述掩膜层500的厚度为3nm～5nm。In this embodiment, the thickness of themask layer 500 is 3 nm˜5 nm.

本实施例中上述各步骤的形成过程与第一实施例相同，在此不在赘述。The formation process of the above steps in this embodiment is the same as that of the first embodiment, and is not repeated here.

参考图13，以所述掩膜层500为掩膜，刻蚀部分高度所述隔离层400，至露出部分所述第二鳍部202的侧壁表面。Referring to FIG. 13 , using themask layer 500 as a mask, a portion of theisolation layer 400 is etched to expose a portion of the sidewall surface of thesecond fin portion 202 .

本实施例中，刻蚀工艺为原子层刻蚀(ALE)工艺。所述原子层刻蚀工艺的参数为：刻蚀气体包括He、NH₃和NF₃，刻蚀腔室压强为2torr至10torr，NH₃流量为200sccm至500sccm，NF₃流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。In this embodiment, the etching process is an atomic layer etching (ALE) process. The parameters of the atomic layer etching process are: the etching gas includes He, NH₃ and NF₃ , the pressure of the etching chamber is 2torr to 10torr, the flow rate of NH₃ is 200sccm to 500sccm, the flow rate of NF₃ is 20sccm to 200sccm, and the flow rate of He The flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.

采用所述原子层刻蚀工艺在刻蚀所述隔离层400时，由于所述原子层刻蚀工艺高选择性、良好的定向刻蚀性以及等量刻蚀的性质，使得暴露出的所述第二鳍部202的高度相同，并且在垂直向下刻蚀的过程中，不会发生偏移。When theisolation layer 400 is etched by the atomic layer etching process, due to the high selectivity, good directional etching properties and the properties of equal etching of the atomic layer etching process, the exposed The heights of thesecond fins 202 are the same and will not be offset during the vertical downward etching process.

参考图14，去除所述掩膜层500(参考图13)以及所述第二鳍部202顶部表面的保护层300，并进一步刻蚀部分厚度所述第二鳍部202。Referring to FIG. 14 , the mask layer 500 (refer to FIG. 13 ) and theprotective layer 300 on the top surface of thesecond fins 202 are removed, and thesecond fins 202 are further etched by a partial thickness.

本实施例中，去除所述掩膜层500(参考图13)以及部分厚度的所述第二鳍部202顶部表面的保护层300的工艺为原子层刻蚀工艺。In this embodiment, the process of removing the mask layer 500 (refer to FIG. 13 ) and a partial thickness of theprotective layer 300 on the top surface of thesecond fin portion 202 is an atomic layer etching process.

在其他实施例中，先使用湿法或干法刻蚀工艺将所述第二鳍部202顶部表面的所述保护层300去除，由于在本实施例中，所述第二鳍部202顶部表面的保护层300的材料以及所述掩膜层500的材料为氮化硅，在刻蚀掉所述第二鳍部202顶部表面的保护层300时，所述掩膜层500的厚度会变薄。然后使用原子层刻蚀工艺的高选择刻蚀性，对所述第二鳍部202进行刻蚀。In other embodiments, theprotective layer 300 on the top surface of thesecond fin portion 202 is first removed by a wet or dry etching process, because in this embodiment, the top surface of thesecond fin portion 202 is The material of theprotective layer 300 and the material of themask layer 500 are silicon nitride. When theprotective layer 300 on the top surface of thesecond fin portion 202 is etched away, the thickness of themask layer 500 will become thinner. . Thesecond fin portion 202 is then etched using the highly selective etchability of the atomic layer etching process.

需要说明的是，所述掩膜层500最终要全部被去除掉，可以选择在形成所述开口401之前，也可以选择在形成所述开口401之后。It should be noted that, themask layer 500 should be completely removed in the end, which can be selected before theopening 401 is formed, or after theopening 401 is formed.

参考图15，重复上述步骤，使用所述原子层刻蚀工艺对氧化硅的选择刻蚀性对所述隔离层400进行部分厚度刻蚀，同时采用所述原子层刻蚀工艺对硅的选择刻蚀性对所述第二鳍部202进行部分厚度的刻蚀；如此循环，即采用所述原子层刻蚀工艺去除所述第二鳍部202与刻蚀所述隔离层400同步进行，去除掉所述第二鳍部202，以形成所述开口401。Referring to FIG. 15 , the above steps are repeated, and theisolation layer 400 is partially etched by the selective etching of silicon oxide using the atomic layer etching process, and the selective etching of silicon is simultaneously performed by the atomic layer etching process. Thesecond fin portion 202 is etched with a partial thickness; in this cycle, the atomic layer etching process is used to remove thesecond fin portion 202 and theisolation layer 400 is etched simultaneously to remove the thesecond fins 202 to form theopenings 401 .

本实施例中，刻蚀部分厚度的所述隔离层400使得刻蚀的定向效果更好，进一步避免对高深宽比的刻蚀情况下发生偏移的情况，更好的保障刻蚀方向；同理，在刻蚀掉部分厚度所述隔离层400后，再刻蚀部分厚度的所述第二鳍部202，同样能够保障对所述第二鳍部202刻蚀时的方向；如此反复，每一次都避免高深宽比刻蚀会出现偏移的情况，使得最终完全去除所述第二鳍部202，不会而对所述第一鳍部201造成损伤；并且所形成的所述开口401的形状也更加完美，利于后续工艺进行。In this embodiment, theisolation layer 400 with a partial thickness etched makes the directional effect of the etching better, further avoids the offset situation in the case of etching with a high aspect ratio, and better guarantees the etching direction; the same In principle, after etching a part of the thickness of theisolation layer 400, thesecond fin part 202 of a part thickness is etched again, which can also ensure the direction of the etching of thesecond fin part 202; The situation where the high aspect ratio etching will be offset is avoided at one time, so that thesecond fins 202 are finally completely removed without causing damage to thefirst fins 201; and the formedopenings 401 have The shape is also more perfect, which is conducive to the subsequent process.

本实施例中，所述原子层刻蚀工艺刻蚀所述隔离层400的工艺参数为：刻蚀气体包括He、NH₃和NF₃，刻蚀腔室压强为2torr至10torr，NH₃流量为200sccm至500sccm，NF₃流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。In this embodiment, the process parameters of the atomic layer etching process for etching theisolation layer 400 are: the etching gas includes He, NH₃ and NF₃ , the pressure of the etching chamber is 2 torr to 10 torr, and the flow rate of NH₃ is 200sccm to 500sccm, NF₃ flow rate is 20sccm to 200sccm, He flow rate is 600sccm to 2000sccm, and etching time is 20 seconds to 100 seconds.

本实施例中，所述原子层刻蚀工艺刻蚀所述第二鳍部202的工艺参数为：刻蚀气体为HBr、O₂和Cl₂，还向刻蚀腔室内通入He，刻蚀腔室压强为2毫托至50毫托，刻蚀的源功率为200瓦至2000瓦，刻蚀加偏压功率为10瓦至100瓦，HBr流量为50sccm至500sccm，O₂流量为2sccm至20sccm，Cl₂流量为10sccm至300sccm，He流量为50sccm至500sccm。In this embodiment, the process parameters for etching thesecond fin portion 202 by the atomic layer etching process are: the etching gas is HBr, O₂ and Cl₂ , and He is also introduced into the etching chamber to etch the The chamber pressure is 2 mTorr to 50 mTorr, the source power for etching is 200 watts to 2000 watts, the etch plus bias power is 10 watts to 100 watts, the HBr flow rate is 50sccm to 500sccm, and the O flow rate is_2sccm to 2000 watts. 20sccm, Cl flow 10sccm to_300sccm , He flow 50sccm to 500sccm.

请继续参考图10，以所述开口401为掩膜，刻蚀所述衬底200，形成凹槽402。Please continue to refer to FIG. 10 , using theopening 401 as a mask, thesubstrate 200 is etched to form agroove 402 .

形成所述凹槽402的工艺为干法刻蚀，工艺参数为：刻蚀气体包括He、NH₃和NF₃，刻蚀腔室压强为2torr至10torr，NH₃流量为200sccm至500sccm，NF₃流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。The process for forming thegroove 402 is dry etching, and the process parameters are: the etching gas includes He, NH₃ and NF₃ , the pressure of the etching chamber is 2torr to 10torr, the flow rate of NH₃ is 200sccm to 500sccm, and the NF₃ The flow rate is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.

请继续参考图11，继续以所述开口401为掩膜，沿所述凹槽402刻蚀所述衬底，加宽所述凹槽402。Please continue to refer to FIG. 11 , continue to use theopening 401 as a mask to etch the substrate along thegroove 402 to widen thegroove 402 .

采用回刻蚀的方法横向加宽所述凹槽，工艺参数为：刻蚀气体包括He、NH3和NF3，刻蚀腔室压强为2torr至10torr，NH3流量为200sccm至500sccm，NF3流量为20sccm至200sccm，He流量为600sccm至2000sccm，刻蚀时间为20秒至100秒。The groove is laterally widened by etching back, and the process parameters are: the etching gas includes He, NH3 and NF3, the etching chamber pressure is 2torr to 10torr, the flow rate of NH3 is 200sccm to 500sccm, and the flow rate of NF3 is 20sccm to 200sccm, the He flow rate is 600sccm to 2000sccm, and the etching time is 20 seconds to 100 seconds.

虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.