Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
The clock tree layout method of the chip provided by the embodiment of the application can be applied to electronic equipment such as mobile phones, tablet computers, wearable equipment, vehicle-mounted equipment, augmented reality (augmented reality, AR)/Virtual Reality (VR) equipment, notebook computers, ultra-mobile personal computer (UMPC), netbooks, personal digital assistants (personal DIGITAL ASSISTANT, PDA) and the like, and the embodiment of the application does not limit the specific types of the electronic equipment.
Fig. 2 shows a schematic flow chart of a clock tree layout method of a chip provided by the present application, which can be applied to the above-mentioned electronic device by way of example and not limitation. The clock tree layout method of the chip comprises the following steps:
s101: the chip is divided into a plurality of clock regions according to the size of the chip.
In specific implementation, the multiple clock areas are identical in size and are arranged in an array, and adjacent clock areas are spliced together.
Alternatively, the clock area may be rectangular, hexagonal, triangular.
When the chip is rectangular, as an example and not by way of limitation, step S101 may include steps A1 to D1.
A1. the quotient of the chip length divided by the preset length is taken as an integer to obtain a first coefficient n.
B1. And taking an integer of the quotient of the chip width divided by the preset width to obtain a second coefficient m.
C1. The chip is divided into rectangular arrays of n rectangles in the length direction and m rectangles in the width direction.
D1. a plurality of rectangles in a rectangular array are set as a plurality of clock regions.
S102: setting at least one control output circuit of the sub phase-locked loop in each clock area; the control output circuit of the sub phase-locked loop comprises a filter, a voltage-controlled oscillator, a charge pump and a frequency divider; the control output circuit of each sub-phase-locked loop provides a first clock signal for a plurality of logic circuits within a respective clock region.
The control output circuit of the sub-phase locked loop may be arranged at any position of the clock area, and preferably, the control output circuit of the sub-phase locked loop may be arranged at a central position of the clock area.
S103: the phase detectors of each sub-phase locked loop are arranged around the clock source.
In a specific implementation, through step S103, the distance between each clock source and the mother phase-locked loop may be minimized, so that the path delay when the second clock signal sent by the clock source reaches the phase detector of each sub phase-locked loop is reduced, and meanwhile, the path delay when the second clock signal sent by the clock source reaches the phase detector of each sub phase-locked loop is consistent.
Step S103 is divided into two cases.
In the first case, step S103 includes steps A2 to B2 when the clock source is disposed inside the chip.
A2. the mother phase-locked loop is arranged on the chip. Specifically, the female phase-locked loop is used as a clock source, and is arranged at any position on the chip.
B2. the phase detectors of each sub-phase-locked loop are arranged around the parent phase-locked loop.
In the second case, when the clock source is disposed outside the chip, step S103 is specifically: arranging phase detectors of all sub phase-locked loops around a second clock signal input end of the chip, wherein the second clock signal is output by a clock source;
The phase detectors of the sub-phase-locked loops are arranged around the second clock signal input end of the chip, so that the path delay when the second clock signal reaches the phase detectors of the sub-phase-locked loops is reduced.
S104: a phase detector and a clock source are connected to each sub-phase locked loop.
The phase detector of each sub phase-locked loop can receive a second clock signal sent by the clock source through connecting the phase detector of each sub phase-locked loop with the clock source, the phase detector compares the phase and the frequency difference of the output signals of the second clock signal and the frequency divider, and generates a control signal to the charge pump, the charge pump correspondingly charges and discharges the filter, the output frequency of the voltage-controlled oscillator is proportional to the control voltage on the filter, the frequency of the output signal of the oscillator is controlled, and the frequency and the phase of the output signal of the voltage-controlled oscillator are fed back to the phase detector through the frequency divider, so that each sub phase-locked loop outputs a synchronous first clock signal. The schematic structure of the sub-pll is shown in fig. 3.
Step S104 is also divided into two cases.
In the first case, when the clock source is disposed inside the chip, step S104 specifically includes: the phase detector of each sub-phase-locked loop is connected to the voltage-controlled oscillator of the parent phase-locked loop or the frequency divider of the parent phase-locked loop.
In the second case, when the clock source is disposed outside the chip, step S104 is specifically: the phase detector and the second clock signal input of each sub-phase locked loop are connected.
Optionally, as shown in fig. 4, step S102 may further include step S102-2, and step S104 may further include step S105 and step S106.
S102-2: and establishing a clock tree by taking the control output circuit of each sub-phase-locked loop as a source point and taking a plurality of logic circuits in a clock area where the control output circuit of each sub-phase-locked loop is positioned as an end point.
The control output circuit of each sub phase-locked loop can be used as a root clock node, a plurality of leaf clock nodes are arranged according to the layout of a plurality of logic circuits, the root clock node is connected to the plurality of leaf clock nodes, and finally each She Shizhong node is connected to the plurality of logic circuits.
S105: each sub-phase-locked loop and clock source is frequency and phase synchronized.
In the working process of the sub-phase-locked loop, when the frequency of an output signal reflects the frequency of an input signal in proportion, the output voltage and the input voltage keep a fixed phase difference value, so that the phases of the output voltage of the sub-phase-locked loop and the input voltage of the sub-phase-locked loop are locked, the unit delay of each sub-phase-locked loop is the same, and the path delay when a second clock signal sent by a clock source reaches a phase discriminator of each sub-phase-locked loop is consistent, thereby realizing the frequency synchronization and the phase synchronization of a first clock signal output by each sub-phase-locked loop.
S106: each sub-phase-locked loop transmits a first clock signal to a plurality of logic circuits in a clock area of each sub-phase-locked loop through a corresponding clock tree.
Since the frequency and phase of each first clock signal are synchronized and the clock tree is set only in a small area of the clock area to transmit the first clock signal, the transmission delay of the first clock signal received by each logic circuit is reduced.
For a better understanding of the present application, the clock tree layout method of the chip of the present application is described below by way of specific examples:
in the first example, as shown in fig. 5, a quotient obtained by dividing the chip length by the preset length is an integer to obtain a first coefficient n of 3; taking an integer of a quotient of the chip width divided by a preset width to obtain a second coefficient m which is 4; dividing the chip into a rectangular array with 3 rectangles in the length direction and 4 rectangles in the width direction; a plurality of rectangles in a rectangular array are set as a plurality of clock regions. Setting at least one control output circuit of the sub phase-locked loop in each clock area; the control output circuit of the sub phase-locked loop comprises a filter, a voltage-controlled oscillator, a charge pump and a frequency divider; the method comprises the steps of setting a master phase-locked loop on a chip; arranging phase detectors of each sub phase-locked loop around the parent phase-locked loop; and a voltage-controlled oscillator connecting the phase detector of each sub-phase-locked loop and the mother phase-locked loop.
In a second example, as shown in fig. 6, the quotient of the chip length divided by the preset length is taken as an integer to obtain a first coefficient n of 3; taking an integer of a quotient of the chip width divided by a preset width to obtain a second coefficient m which is 4; dividing the chip into a rectangular array with 3 rectangles in the length direction and 4 rectangles in the width direction; setting a plurality of rectangles in a rectangular array as a plurality of clock areas; setting at least one control output circuit of the sub phase-locked loop in each clock area; the control output circuit of the sub phase-locked loop comprises a filter, a voltage-controlled oscillator, a charge pump and a frequency divider; arranging phase detectors of all sub phase-locked loops around a second clock signal input end of the chip, wherein the second clock signal is output by a clock source; the phase detector and the second clock signal input of each sub-phase locked loop are connected.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
Corresponding to the clock tree layout method of the chip of the above embodiment, fig. 7 shows a block diagram of the clock tree layout device of the chip provided in the embodiment of the present application, and for convenience of explanation, only the portion related to the embodiment of the present application is shown.
Referring to fig. 7, the clock tree patterning device 30 of the chip includes a dividing module 310, a control output circuit setting module 320, a routing module 330, and a connecting module 340.
The dividing module 310 is configured to divide the chip into a plurality of clock areas according to the size of the chip.
A control output circuit setting module 320, configured to set a control output circuit of at least one sub phase locked loop in each clock area; the control output circuit of the sub phase-locked loop comprises a filter, a voltage-controlled oscillator, a charge pump and a frequency divider; the control output circuit of each sub-phase-locked loop provides a first clock signal for a plurality of logic circuits within a respective clock region.
And a configuration module 330, configured to configure the phase detectors of the respective sub-phase-locked loops around the clock source.
A connection module 340 is used to connect the phase detector and the clock source of each sub-phase locked loop.
As shown in FIG. 8, the clock tree layout apparatus 30 of the chip may further include a clock tree creation module 350.
The clock tree building module 350 is configured to build a clock tree with the control output circuit of each sub-pll as a source point and with a plurality of logic circuits in a clock area where the control output circuit of each sub-pll is located as an end point.
As shown in FIG. 9, the clock tree patterning device 30 of the chip may further include a synchronization module 360.
A synchronization module 360 is configured to perform frequency synchronization and phase synchronization on each sub-pll and the clock source.
As shown in fig. 10, the clock tree patterning device 30 of the chip may further include a clock signal transmitting module 370.
The clock signal sending module 370 is configured to send the first clock signal to a plurality of logic circuits in a clock area where each sub-phase-locked loop is located, through a respective corresponding clock tree.
Specifically, there are two cases of the arrangement module 330 and the connection module 340.
In the first case, when the clock source is disposed inside the chip, as shown in fig. 11, the arrangement module 330 includes:
The female phase-locked loop setting unit 331 is configured to set the female phase-locked loop on the chip.
And an arrangement unit 332, configured to arrange the phase detectors of the respective sub-phase-locked loops around the mother phase-locked loop.
The connection module 340 is specifically configured to: the phase detector of each sub-phase-locked loop is connected to the voltage-controlled oscillator of the parent phase-locked loop or the frequency divider of the parent phase-locked loop.
In the second case, when the clock source is disposed outside the chip, the arrangement module 330 is specifically configured to: arranging phase detectors of all sub phase-locked loops around a second clock signal input end of the chip, wherein the second clock signal is output by a clock source;
the connection module 340 is specifically configured to: the phase detector and the second clock signal input of each sub-phase locked loop are connected.
As shown in fig. 12, when the chip is rectangular, the division module 310 includes a first coefficient acquisition module 311, a second coefficient acquisition module 312, a rectangular array division module 313, and a setting module 314.
The first coefficient obtaining module 311 is configured to divide the chip length by a quotient of a preset length to obtain a first coefficient n.
The second coefficient obtaining module 312 is configured to obtain a second coefficient m by taking an integer of a quotient obtained by dividing the chip width by the preset width.
The rectangular array dividing module 313 is configured to divide the chip into rectangular arrays having n rectangles in the length direction and m rectangles in the width direction.
The setting module 314 is configured to set a plurality of rectangles in the rectangular array to a plurality of clock areas.
It should be noted that, because the content of information interaction and execution process between the above devices/units is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
The embodiment of the application also provides electronic equipment, which comprises: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, the processor implementing the steps in any of the various method embodiments described above when the computer program is executed.
The embodiments of the present application also provide a computer readable storage medium storing a computer program, which when executed by a processor implements steps of the above-described respective method embodiments.
Embodiments of the present application provide a computer program product which, when run on an electronic device, causes the electronic device to perform steps that may be carried out in the various method embodiments described above.
Fig. 13 is a schematic structural diagram of a clock tree layout device/electronic apparatus of a chip according to an embodiment of the present application. As shown in fig. 13, the clock tree patterning device/electronic apparatus 13 of the chip of this embodiment includes: at least one processor 130 (only one processor is shown in fig. 13), a memory 131, and a computer program 132 stored in the memory 131 and executable on the at least one processor 130, the processor 130 implementing the steps in the clock tree layout method embodiments of any of the individual chips described above when executing the computer program 132.
The clock tree patterning device/electronic device 13 of the chip may be a computing device such as a desktop computer, a notebook computer, a palm computer, or a cloud server. The clock tree patterning means/electronics of the chip may include, but is not limited to, a processor 130, a memory 131. It will be appreciated by those skilled in the art that fig. 13 is merely an example of the clock tree patterning device/electronic device 13 of the chip, and is not meant to limit the clock tree patterning device/electronic device 13 of the chip, and may include more or less components than illustrated, or may combine some components, or may include different components, such as input-output devices, network access devices, etc.
The Processor 130 may be a central processing unit (Central Processing Unit, CPU), and the Processor 130 may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, DSPs), application SPECIFIC INTEGRATED Circuits (ASICs), off-the-shelf Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 131 may in some embodiments be an internal memory unit of the clock tree patterning device/electronic device 13 of the chip, such as a hard disk or a memory of the clock tree patterning device/electronic device 13 of the chip. The memory 131 may in other embodiments also be an external memory device of the chip clock tree patterning device/electronic device 13, such as a plug-in hard disk provided on the chip clock tree patterning device/electronic device 13, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD), etc. Further, the memory 131 may also include both internal memory cells and external memory devices of the clock tree patterning means/electronic device 13 of the chip. The memory 131 is used to store an operating system, application programs, boot loader (BootLoader), data, and other programs and the like, such as program codes of computer programs and the like. The memory 131 may also be used to temporarily store data that has been output or is to be output.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above-described embodiments, and may be implemented by a computer program to instruct related hardware, and the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, executable files or in some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a terminal device, a recording medium, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other manners. For example, the apparatus/network device embodiments described above are merely illustrative, e.g., the division of modules or elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.