CN112072615B - Topological structure of motor high-side power supply control circuit and fault positioning method thereof - Google Patents

Abstract

The invention provides a topological structure of a high-side power supply control circuit of a motor and a fault positioning method thereof, which can meet the safety shutdown function of a load motor in an upper power output state, an overvoltage state, an overcurrent state and a system internal fault through the topological structure, and can monitor the running state of the load motor in real time. In addition, the motor control system has the advantages of simple circuit structure, less components, low cost, strong compatibility, high safety and reliability, and can meet the working requirements of motors with different loads by replacing components with different parameters, and can be suitable for motor control systems in the fields of industrial automation and vehicle-mounted motors.

Description

Topological structure of motor high-side power supply control circuit and fault positioning method thereof

Technical Field

The invention relates to the field of power supplies, in particular to a topological structure of a motor high-side power supply control circuit and a fault positioning method thereof.

Background

With the continuous development of society and the emergence of new technologies, the product design concept of green energy conservation, safety and reliability is continuously popularized, and a plurality of new energy technologies are rapidly developed to gradually replace fossil energy, such as the development of new energy automobiles. In addition, along with the development of new energy, higher and wider requirements are provided for the energy-saving safety of electric equipment.

The motor control technology developed by the green energy-saving, safe and reliable concepts goes deep into various fields of human life, and the stability and the safety of a high-side power supply control circuit of a motor influence the life and property safety of product users. However, the problems of single function and single fault safety monitoring and protecting function exist in the conventional motor high-side power supply control.

Disclosure of Invention

The invention aims to solve the defects in the prior art, and provides a topological structure of a motor high-side power supply control circuit and a fault positioning method thereof.

In order to achieve the purpose, the invention adopts the following technical scheme: a motor high-side power supply control circuit topological structure is characterized in that a main circuit module is used for supplying power to a load, an overvoltage protection and release module is used for realizing power-off protection when voltage is overhigh and releasing the power-off protection function after the voltage is normal, and an overcurrent protection and release module is used for power-off protection when current is overhigh and releasing the power-off protection function after the voltage is normal;

the main circuit module comprises a resistor R11, an N-channel field effect transistor Q4, a voltage stabilizing diode Z3, a resistor R12, a P-channel field effect transistor Q5, a resistor R7, a triode Q3, a resistor R5, a resistor R6, a resistor R4, an AND logic chip U1, a sampling resistor RS, a resistor R15, a resistor R16, a resistor R17 and a resistor R18; theport 1 and theport 2 of the resistor R11 are respectively connected with the port D and the port G of an N-channel field effect transistor Q4, the port S of the N-channel field effect transistor Q4, theport 1 of a voltage-regulator diode Z3, theport 1 of a resistor R12 and the port D of a P-channel field effect transistor Q5, theport 2 of the voltage-regulator diode Z3, theport 2 of the resistor R12, the port G of the P-channel field effect transistor Q5 and theport 2 of the resistor R7 are connected, theport 1 of the resistor R7 is connected with the port C of a triode Q3, theport 2 of the resistor R6 is connected with the port B of the triode Q3, the port E of the triode Q3 is grounded, theport 1 of the resistor R5, theport 1 of the resistor R6 and theport 1 of the resistor R4 are connected, theport 2 of the resistor R5 is grounded, theport 2 of the resistor R4 is connected with the port 3 of an AND gate logic chip U1, the port S of the P-channel field effect transistor Q5, theport 1 of the sampling resistor RS, theport 1 of the resistor R17, theport 2 of the resistor R17 and theport 2 of the resistor R17, the port 15 of the port R15 and the port N-channel field effect transistor Q15;

the overvoltage protection and release module comprises a diode D1, a voltage stabilizing diode Z1, a resistor R1, a capacitor C1, a resistor R2, a resistor R3 and a triode Q1; theport 1 of the diode D1 is connected with the port D of the N-channel field effect transistor Q4, theport 2 of the diode D1 is connected with theport 2 of the voltage-stabilizing diode Z1, theport 1 of the voltage-stabilizing diode Z1 is connected with theport 1 of the resistor R1, theport 2 of the capacitor C1, theport 2 of the resistor R2 and theport 2 of the resistor R3 are connected, theport 1 of the capacitor C1 and theport 1 of the resistor R2 are grounded, theport 1 of the resistor R3 is connected with the port B of the triode Q1, the port E of the triode Q1 is grounded, and the port C of the triode Q1 is connected with theport 1 of the resistor R4 in the main circuit module;

the overcurrent protection and release module comprises a resistor R13, a resistor R14, a differential operational amplifier U2, a resistor R10, a voltage stabilizing diode Z2, a resistor R8, a resistor R9 and a triode Q2; theport 2 of the resistor R13 is connected with theport 1 of the sampling resistor RS in the main circuit module, theport 2 of the resistor R14 is connected with theport 2 of the sampling resistor RS in the main circuit module, theport 1 of the resistor R13 and theport 1 of the resistor R14 are respectively connected with theport 1 and theport 2 of the differential operational amplifier U2, the port 3 of the differential operational amplifier U2, theport 1 of the resistor R10 and theport 1 of the zener diode Z2 are connected, theport 2 of the zener diode Z2, theport 2 of the resistor R8 and theport 2 of the resistor R9 are connected, theport 1 of the resistor R9 is grounded, theport 1 of the resistor R8 is connected with the port B of the triode Q2, the port E of the triode Q2 is grounded, and the port C of the triode Q2 is connected with theport 1 of the resistor R4 in the main circuit module.

The main circuit module and the overvoltage protection and release module are connected through an input end Vin and a No. 1 end of a diode D1, the No. 1 end of a resistor R4 and the No. 1 end of a resistor R6 of the main circuit module are connected with an overvoltage protection and release module triode Q1 and an overcurrent protection and release module triode Q2 to be switched on and off, and the No. 1 end and the No. 2 end of a sampling resistor RS of the main circuit module are respectively connected with a No. 2 end of an overcurrent protection and release module resistor R13 and a No. 2 end of a resistor R14, so that the connection of three functional modules is realized;

the No. 2 end of the main circuit module resistor R5, the No. 1 end of the overvoltage protection and release module capacitor device C1, the E end of the overvoltage protection and release module triode Q1, the E end of the overcurrent protection and release module triode Q2 and the No. 1 end of the overcurrent protection and release module resistor R9 are all grounded.

Further, when the inside of the main circuit module and the power management chip are in fault, the load needs to be subjected to emergency power-off processing, when one of the MCU control output end and the power management fault function output end outputs a low level in such a situation, the output end 3 of the and gate logic chip U1 outputs a low level, since no potential difference is formed between the resistors R4 and R5, the potential of theport 1 acting on the resistor R6 is low, the potential connected to the port B of the triode Q3 through theport 2 of the resistor R6 is a low potential, the triode Q3 is in a closed state, so that the port E and the port C of the triode Q3 are not connected, and since a current loop is not formed, the potentials of the port D and the port G of the P-channel field effect transistor Q5 are equal and do not reach the turn-on voltage of the P-channel field effect transistor Q5, the P-channel transistor Q5 is turned off, and the load current cannot act on the load resistor RL through the P-channel field effect transistor Q5, so that the load cannot work normally.

Further, the overvoltage protection and release module comprises a voltage stabilizing diode Z1 which is in a conducting state when the voltage of an input end Vin exceeds a specified voltage value, and current forms a loop passing through D1, Z1, R1 and R2, and because the current flows through R2 and forms a potential difference between aport 1 and aport 2 of a resistor R2 to act on a port 3 of a resistor R3, the voltage of a port B connected with a triode Q1 through theport 1 of the resistor R3 is larger than the starting voltage of the triode Q1, the port E of the triode Q1 is conducted with the port C, so that theport 1 of a resistor R6 connected with the port C of the triode Q1 is pulled down, the triode Q3 is in a closing state, the port E and the port C of the triode Q3 are not conducted, and the potential of the port D and the port G of the P-channel field effect transistor Q5 is equal to the potential of the port C due to the fact that a current loop is not formed, the starting voltage of the P-channel field effect transistor Q5 is not equal to reach the starting voltage of the P-channel field effect transistor Q5, the P-channel field effect transistor Q5 is closed, and the load current cannot act on the load resistor RL, so that the load cannot work normally;

when the voltage of the input terminal Vin returns to the normal state from the abnormal state, the voltage stabilizing diode Z1 is not conducted, and the triode Q1 is in the off state.

Further, the overcurrent protection and release module comprises a voltage stabilizing diode Z2 which is conducted when a current signal passes through the sampling resistor RS, the resistors R13 and R14 and a voltage signal converted by the differential operational amplifier U2 exceeds a specified value, the triode Q2 is conducted, the P-channel field effect transistor Q5 is closed, and a load current cannot act on the load resistor RL through the P-channel field effect transistor Q5, so that the load cannot work normally.

Further, an RC filter circuit is formed by the resistor R1, the capacitor C1 and the resistor R2, and the influence of the false triggering phenomenon of Vin caused by transient voltage interference on the stability of the product is eliminated.

Further, reverse connection prevention is carried out through a diode D1 and a body diode inside the N-channel field effect transistor Q4, and reverse connection protection of the circuit topology is achieved.

The structure circuit fault positioning method comprises the following steps: on the basis of the circuit topological structure, a resistor R15, a resistor R16 and a powersupply voltage acquisition 1 are connected at an input end Vin, a resistor R17, a resistor R18 and a powersupply voltage acquisition 2 are connected at an S end of a P-channel field effect transistor Q5, a resistor R10 and a power supply line current acquisition are connected at a voltage stabilizing diode Z2, and on the basis, the powersupply voltage acquisition 1, the powersupply voltage acquisition 2, the power supply current acquisition and MCU control output and power supply management fault function safety output are compared to jointly locate a fault area. The fault area is co-located by comparing powersupply voltage acquisition 1, powersupply voltage acquisition 2, power supply current acquisition and MCU control output and power supply management fault function safety output.

(1) When the short-circuit fault occurs to the Z1 voltage-stabilizing tube:

the voltage collected by the powersupply voltage collection 1 can be analyzed to be lower than the normal range by the norton current theorem. When a short circuit occurs in Z1, the voltage of the port B of the triode Q1 reaches the starting voltage of the triode, the port E of the triode Q1 is conducted with the port C, the voltage of theport 1 side of the resistor R4 is pulled down, although the power current collection, MCU control output and power management fault function safety output are high at the moment, the port AND gate logic chip U1 and the port AND output port are high, the port B of the triode Q3 is still pulled down, the port C and the port E of the triode Q3 are not conducted, the potential of the electrode G of the P-channel field effect tube Q5 is equal to the potential of the electrode S, the power current collection device is in a closed state, the voltage collected by the powervoltage collection device 2 is 0, the current cannot form a loop due to the closing of the P-channel field effect tube Q5, the power current collection device is 0, and the fault of the Z1 device is positioned.

(2) The port B and the port C of the triode Q2 have short-circuit faults:

at the moment, the power current acquisition and MCU control output and the power management fault function safety output are high, the U1 and the gate output port are high, the voltage of theport 1 acting on the resistor R4 is high, and theport 1 acting on the R8 through the port C and the port B of the triode Q2 is high level. The voltage is divided by the voltage of R8 and R9 and acts on the No. 2 port of the voltage-stabilizing tube Z2, and the voltage of the No. 1 port acting on the resistor R10 through the voltage-stabilizing tube Z2 is larger than the voltage in the normal range. At this time, since theport 1 of the R6 is always at a high level, the voltage at the port B of the triode Q3 is greater than the start voltage, the port C of the triode Q3 is conducted with the port E, the P-channel field effect transistor Q5 is conducted, and the powersupply voltage acquisition 2 outputs a high level.

(3) If the chip of the AND logic chip U1 breaks down, the output end of the No. 3 is always at a low level, so that the P-channel field effect transistor Q5 is closed;

if the D pole and the S pole of the P-channel field effect transistor Q5 have short circuit faults, although the powersupply voltage acquisition 1, the powersupply voltage acquisition 2 and the power supply current acquisition are in normal ranges, the P-channel field effect transistor Q5 cannot be controlled through the MCU control output and the power supply management fault function safety output.

Compared with the prior art, the invention has the advantages and positive effects that: the problem of present motor high side power control have the function singleness, fail safe monitoring and protect function singleness is improved, realized cutting off the high side power under the power supply is unusual, motor operation is unusual, the inside abnormal condition of control unit, effectively prevent the later stage load because the short circuit causes the power consumption to increase even the accident of starting a fire to take place, also improve product maintenance efficiency and reduction product single point monitoring fault rate simultaneously greatly.

Drawings

FIG. 1 is a block diagram of a high-side power control circuit of the motor of the present invention;

FIG. 2 is a block diagram of a high-side power control circuit of the motor in a reverse connection state according to the present invention;

FIG. 3 is a fault partition block diagram of the motor high side power control circuit of the present invention;

illustration of the drawings: R1-R18 are resistance devices, C1 is a capacitance device, D1 is a diode device, Z1-Z3 are voltage-stabilizing diode devices, Q1-Q3 are NPN type triode devices, Q4 is an N enhancement type channel field effect transistor, Q5 is a P channel enhancement type field effect transistor, U1 is an AND logic chip, RS is a sampling resistor, RL is a load resistor, and U2 is a differential operational amplifier (a differential operational amplifier with the model number of INA195AQDBVRQ1 is used in the topology).

Detailed Description

In order that the above objects, features and advantages of the present invention can be more clearly understood, the present invention will be further described with reference to the accompanying drawings and examples. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced otherwise than as specifically described herein and, therefore, the present invention is not limited to the specific embodiments disclosed in the following description.

Embodiment 1, as shown in fig. 1 to 3, the present invention provides a topology structure of a high-side power control circuit of a motor and a fault location method thereof, where a main circuit module is used for supplying power to a load, an overvoltage protection and release module is used to implement power-off protection when voltage is too high and release a power-off protection function when voltage is normal, and an overcurrent protection and release module is used to perform power-off protection when current is too high and release a power-off protection function when voltage is normal;

the main circuit module and the overvoltage protection and release module are connected through an input end Vin and a No. 1 end of a diode D1, the No. 1 end of a resistor R4 and the No. 1 end of a resistor R6 of the main circuit module are connected with an overvoltage protection and release module triode Q1 and an overcurrent protection and release module triode Q2 to be switched on and off, and the No. 1 end and the No. 2 end of a sampling resistor RS of the main circuit module are respectively connected with a No. 2 end of an overcurrent protection and release module resistor R13 and a No. 2 end of a resistor R14, so that the connection of three functional modules is realized;

the No. 2 end of the main circuit module resistor R5, the No. 1 end of the overvoltage protection and release module capacitor device C1, the E end of the overvoltage protection and release module triode Q1, the E end of the overcurrent protection and release module triode Q2 and the No. 1 end of the overcurrent protection and release module resistor R9 are all grounded.

Further, when the inside of the main circuit module and the power management chip are in fault, the load needs to be subjected to emergency power-off processing, when one of the MCU control output end and the power management fault function output end outputs a low level in such a situation, the output end 3 of the and gate logic chip U1 outputs a low level, since no potential difference is formed between the resistors R4 and R5, the potential of theport 1 acting on the resistor R6 is low, the potential connected to the port B of the triode Q3 through theport 2 of the resistor R6 is a low potential, the triode Q3 is in a closed state, so that the port E and the port C of the triode Q3 are not connected, and since a current loop is not formed, the potentials of the port D and the port G of the P-channel field effect transistor Q5 are equal and do not reach the turn-on voltage of the P-channel field effect transistor Q5, the field effect transistor Q5 is turned off, and the load current cannot act on the load resistor RL through the P-channel field effect transistor Q5, so that the load cannot work normally.

Further, the overvoltage protection and release module comprises a voltage stabilizing diode Z1 which is in a conducting state when the voltage of an input end Vin exceeds a specified voltage value, and current forms a loop passing through D1, Z1, R1 and R2, and because the current flows through R2 and forms a potential difference between aport 1 and aport 2 of a resistor R2 to act on a port 3 of a resistor R3, the voltage of a port B connected with a triode Q1 through theport 1 of the resistor R3 is larger than the starting voltage of the triode Q1, the port E of the triode Q1 is conducted with the port C, so that theport 1 of a resistor R6 connected with the port C of the triode Q1 is pulled down, the triode Q3 is in a closing state, the port E and the port C of the triode Q3 are not conducted, and the potential of the port D and the port G of the P-channel field effect transistor Q5 is equal to the potential of the port C due to the fact that a current loop is not formed, the starting voltage of the P-channel field effect transistor Q5 is not equal to reach the starting voltage of the P-channel field effect transistor Q5, the P-channel field effect transistor Q5 is closed, and the load current cannot act on the load resistor RL, so that the load cannot work normally;

when the voltage of the input terminal Vin returns to the normal state from the abnormal state, the voltage stabilizing diode Z1 is not conducted, and the triode Q1 is in the off state.

Further, the overcurrent protection and release module comprises a voltage stabilizing diode Z2 which is conducted when a current signal passes through the sampling resistor RS, the resistors R13 and R14 and a voltage signal converted by the differential operational amplifier U2 exceeds a specified value, the triode Q2 is conducted, the field effect transistor Q5 is closed, and a load current cannot act on the load resistor RL through the P-channel field effect transistor Q5, so that the load cannot normally work.

Further, an RC filter circuit is formed by the resistor R1, the capacitor C1 and the resistor R2, and the influence of the false triggering phenomenon of Vin caused by transient voltage interference on the stability of the product is eliminated.

Further, reverse connection prevention is carried out through a diode D1 and a body diode inside the N-channel field effect transistor Q4, and reverse connection protection of the circuit topology is achieved.

Aiming at the circuit structure diagram, the fault location method can be further explained by combining a fault location table in table 1 and a fault location table in fig. 3, on the basis of the circuit topology structure, a resistor R15, a resistor R16 and a powersupply voltage acquisition 1 are connected at an input end Vin, a resistor R17, a resistor R18 and a powersupply voltage acquisition 2 are connected at an S end of a P-channel field effect transistor Q5, a resistor R10 and a power supply line current acquisition are connected at a voltage stabilizing diode Z2, and on the basis, the powersupply voltage acquisition 1, the powersupply voltage acquisition 2, the power supply current acquisition and MCU control output and the power supply management fault function safety output are compared to jointly locate a fault area.

(1) When the short-circuit fault occurs to the Z1 voltage-stabilizing tube:

the voltage collected by the powersupply voltage collection 1 can be analyzed to be lower than the normal range by the norton current theorem. When Z1 is in short circuit, the voltage of the port B of the triode Q1 reaches the starting voltage of the triode, the port E of the triode Q1 is conducted with the port C, the voltage of theport 1 side of the resistor R4 is pulled down, although the power current collection, the MCU control output and the power management fault function safety output are high at the moment, the output port of the AND gate logic chip U1 is high, the port B of the triode Q3 is still pulled down, the port C and the port E of the triode Q3 are not conducted, the potential of the electrode G of the P-channel field effect transistor Q5 is equal to the potential of the electrode S, the power current collection device is in a closed state, the voltage collected by the powervoltage collection device 2 is 0, the current cannot form a loop due to the closing of the P-channel field effect transistor Q5, the power current collection device is 0, and the Z1 device is positioned to generate faults.

(2) The port B and the port C of the triode Q2 have short-circuit faults:

at the moment, the power supply current acquisition and MCU control output and the power supply management fault function safety output are high, the AND gate logic chip U1 and the AND gate output port are high, the voltage of theport 1 of the acting and resistor R4 is high, and theport 1 acting on the R8 through the port C and the port B of the triode Q2 is high level. The voltage is divided by the voltage of R8 and R9 and acts on the No. 2 port of the voltage-stabilizing tube Z2, and the voltage of the No. 1 port acting on the resistor R10 through the voltage-stabilizing tube Z2 is larger than the voltage in the normal range. At this time, since theport 1 of the R6 is always at a high level, the voltage at the port B of the triode Q3 is greater than the start voltage, the port C of the triode Q3 is conducted with the port E, the P-channel field effect transistor Q5 is conducted, and the output of the powersupply voltage acquisition 2 is at a high level.

(3) Failure of zone 4:

if the chip of the AND logic chip U1 breaks down, the output end of the No. 3 is always at a low level, so that the P-channel field effect transistor Q5 is closed;

if the D pole and the S pole of the P-channel field effect transistor Q5 have short circuit faults, although the powersupply voltage acquisition 1, the powersupply voltage acquisition 2 and the power supply current acquisition are in normal ranges, the P-channel field effect transistor Q5 cannot be controlled through the MCU control output and the power supply management fault function safety output.

In conclusion, the method can accurately judge the fault area of the topological structure of the high-side power supply control circuit of the motor.

Table 1: fault area table for circuit topology

The above description is only a preferred embodiment of the present invention, and not intended to limit the present invention in other forms, and any person skilled in the art may apply the above modifications or changes to the equivalent embodiments with equivalent changes, without departing from the technical spirit of the present invention, and any simple modification, equivalent change and change made to the above embodiments according to the technical spirit of the present invention still belong to the protection scope of the technical spirit of the present invention.

Claims (8)

1. A topological structure of a high-side power supply control circuit of a motor comprises a main circuit module, an overvoltage protection and release module and an overcurrent protection and release module, and is characterized in that the main circuit module is used for supplying power to a load, the overvoltage protection and release module is used for realizing power-off protection when the voltage is overhigh and releasing the power-off protection function when the voltage is normal, and the overcurrent protection and release module is used for realizing the power-off protection when the current is overhigh and releasing the power-off protection function when the voltage is normal;

the main circuit module comprises a resistor R11, an N-channel field effect transistor Q4, a voltage stabilizing diode Z3, a resistor R12, a P-channel field effect transistor Q5, a resistor R7, a triode Q3, a resistor R5, a resistor R6, a resistor R4, an AND logic chip U1, a sampling resistor RS, a resistor R15, a resistor R16, a resistor R17 and a resistor R18; the port 1 and the port 2 of the resistor R11 are respectively connected with the port D and the port G of an N-channel field effect transistor Q4, the port S of the N-channel field effect transistor Q4, the port 1 of a voltage-regulator diode Z3, the port 1 of a resistor R12 and the port D of a P-channel field effect transistor Q5, the port 2 of the voltage-regulator diode Z3, the port 2 of the resistor R12, the port G of the P-channel field effect transistor Q5 and the port 2 of the resistor R7 are connected, the port 1 of the resistor R7 is connected with the port C of a triode Q3, the port 2 of the resistor R6 is connected with the port B of the triode Q3, the port E of the triode Q3 is grounded, the port 1 of the resistor R5, the port 1 of the resistor R6 and the port 1 of the resistor R4 are connected, the port 2 of the resistor R5 is grounded, the port 2 of the resistor R4 is connected with the port 3 of an AND gate logic chip U1, the port S of the P-channel field effect transistor Q5, the port 1 of the sampling resistor RS, the port 1 of the resistor R17, the port 2 of the resistor R17 and the port 2 of the resistor R17, the port 15 of the port R15 and the port N-channel field effect transistor Q15;

the overvoltage protection and release module comprises a diode D1, a voltage stabilizing diode Z1, a resistor R1, a capacitor C1, a resistor R2, a resistor R3 and a triode Q1; the port 1 of the diode D1 is connected with the port D of the N-channel field effect transistor Q4, the port 2 of the diode D1 is connected with the port 2 of the voltage-stabilizing diode Z1, the port 1 of the voltage-stabilizing diode Z1 is connected with the port 1 of the resistor R1, the port 2 of the capacitor C1, the port 2 of the resistor R2 and the port 2 of the resistor R3 are connected, the port 1 of the capacitor C1 and the port 1 of the resistor R2 are grounded, the port 1 of the resistor R3 is connected with the port B of the triode Q1, the port E of the triode Q1 is grounded, and the port C of the triode Q1 is connected with the port 1 of the resistor R4 in the main circuit module;

the overcurrent protection and release module comprises a resistor R13, a resistor R14, a differential operational amplifier U2, a resistor R10, a voltage stabilizing diode Z2, a resistor R8, a resistor R9 and a triode Q2; the port 2 of the resistor R13 is connected with the port 1 of the sampling resistor RS in the main circuit module, the port 2 of the resistor R14 is connected with the port 2 of the sampling resistor RS in the main circuit module, the port 1 of the resistor R13 and the port 1 of the resistor R14 are respectively connected with the port 1 and the port 2 of the differential operational amplifier U2, the port 3 of the differential operational amplifier U2, the port 1 of the resistor R10 and the port 1 of the voltage-regulator diode Z2 are connected, the port 2 of the voltage-regulator diode Z2, the port 2 of the resistor R8 and the port 2 of the resistor R9 are connected, the port 1 of the resistor R9 is grounded, the port 1 of the resistor R8 is connected with the port B of the triode Q2, the port E of the triode Q2 is grounded, and the port C of the triode Q2 is connected with the port 1 of the resistor R4 in the main circuit module;

the main circuit module and the overvoltage protection and release module are connected with a port 1 of a diode D1 through an input end Vin, a port 1 of a resistor R4 and a port 1 of a resistor R6 of the main circuit module are connected with an overvoltage protection and release module triode Q1 and an overcurrent protection and release module triode Q2 to be connected and disconnected, and a port 1 and a port 2 of a sampling resistor RS of the main circuit module are respectively connected with a port 2 of an overcurrent protection and release module resistor R13 and a port 2 of a resistor R14 to realize the connection of the three functional modules;

the port 2 of the main circuit module resistor R5, the port 1 of the overvoltage protection and release module capacitor C1, the port E of the overvoltage protection and release module triode Q1, the port E of the overcurrent protection and release module triode Q2 and the port 1 of the overcurrent protection and release module resistor R9 are all grounded.

2. The motor high-side power control circuit topology of claim 1, wherein: when the main circuit module normally operates, when the MCU control output end and the power management fault function output end are set to be high, the output end 3 of the AND logic chip U1 is in a high level and is connected with the port 2 of the resistor R4, so that the potential after voltage division through the resistor R4 and the resistor R5 acts on the port 1 of the resistor R6, the port 2 of the resistor R6 is connected with the port B of the triode Q3, the voltage input to the port B of the triode Q3 is greater than the starting voltage of the triode Q3, the port E and the port C of the triode Q3 are conducted, the port E is connected with the port G of the P-channel field effect tube Q5 through the resistor R7, the voltage difference between the port D and the port G of the P-channel field effect tube Q5 is greater than the starting voltage of the P-channel field effect tube Q5, the port D of the P-channel field effect tube Q5 is conducted with the port S, the current acts on the port 2 of the load resistor RL through the input end Vin, and the load can work.

3. The topology of the high-side power control circuit of claim 1, wherein: when the inside of the main circuit module and the power management chip have faults, the load needs to be subjected to emergency power-off processing, when the MCU controls one of the output end and the power management fault function output end to output low level, the output end 3 of the AND gate logic chip U1 outputs low level, because no potential difference is formed between the resistors R4 and R5, the potential of the port 1 acting on the resistor R6 is low, the potential connected with the port B of the triode Q3 through the port 2 of the resistor R6 is low, the triode Q3 is in a closed state, so that the port E and the port C of the triode Q3 are not conducted, because a current loop is not formed, the potential of the port D and the port G of the P-channel field effect transistor Q5 are equal, the potential does not reach the starting voltage of the P-channel field effect transistor Q5, the P-channel field effect transistor Q5 is closed, and the load current cannot act on the load resistor RL through the P-channel field effect transistor Q5, so that the load cannot work normally.

4. The motor high-side power control circuit topology of claim 1, wherein: the overvoltage protection and release module comprises a voltage stabilizing diode Z1 which is in a conducting state when the voltage of an input end Vin exceeds a specified voltage value, and current forms a loop passing through D1, Z1, R1 and R2, and because the current flows through R2 and forms potential difference between a port 1 and a port 2 of a resistor R2 to act on a port 3 of a resistor R3, the voltage of a port B connected with a triode Q1 through the port 1 of the resistor R3 is larger than the starting voltage of the triode Q1, the port E of the triode Q1 is conducted with the port C, the port 1 of a resistor R6 connected with the port C of the triode Q1 is pulled down, the triode Q3 is in a closing state, so that the port E and the port C of the triode Q3 are not conducted, and the potential of the port D and the port G of the P-channel field effect transistor Q5 is equal due to the fact that a current loop is not formed, the starting voltage of the port Q5 of the P-channel field effect transistor Q5 is not reached, the P-channel field effect transistor Q5 is turned on, the P-channel field effect transistor Q5 is turned off, and the load current cannot act on a load resistor RL, so that the load cannot normally work;

when the voltage of the input terminal Vin returns to the normal state from the abnormal state, the voltage stabilizing diode Z1 is not conducted, and the triode Q1 is in the off state.

5. The topology of the high-side power control circuit of claim 1, wherein: the overcurrent protection and release module comprises a voltage stabilizing diode Z2 which is conducted when a current signal passes through a sampling resistor RS, resistors R13 and R14 and a voltage signal converted by a differential operational amplifier U2 exceeds a specified value, a triode Q2 is conducted, a P-channel field effect transistor Q5 is closed, and a load current cannot act on a load resistor RL through the P-channel field effect transistor Q5, so that the load cannot work normally.

6. The motor high-side power supply control circuit topology structure of claim 1 or 4, characterized in that: the resistor R1, the capacitor C1 and the resistor R2 form an RC filter circuit, and the influence of a false triggering phenomenon of the input end Vin due to transient voltage interference on the stability of a product is eliminated.

7. The motor high-side power control circuit topology of claim 1, 2, 3 or 4, wherein: and reverse connection prevention is carried out on the diode D1 and a body diode in the N-channel field effect transistor Q4, so that reverse connection protection of the circuit topology is realized.

8. The method for locating the fault of the topological structure of the high-side power supply control circuit of the motor according to claim 1, characterized in that: on the basis of the circuit topological structure, the end No. 2 of the resistor R15 is connected at the input end Vin, the end No. 1 of the resistor R16 is connected with a power supply voltage acquisition 1, the end No. 1 of the resistor R18 is connected with a power supply voltage acquisition 2, and the end No. 2 of the resistor R10 is connected with a power supply line current acquisition, and on the basis, the power supply voltage acquisition 1, the power supply voltage acquisition 2, the power supply current acquisition and MCU control output and the power supply management fault function safety output are compared to jointly position a fault area;

(1) When the short-circuit fault occurs to the Z1 voltage-stabilizing tube:

the norton current theorem can analyze that the voltage acquired by the power supply voltage acquisition 1 is lower than a normal range, when Z1 is in short circuit, the voltage of a port B of the triode Q1 reaches the starting voltage of the triode, a port E of the triode Q1 is conducted with a port C, the voltage of a port 1 side of the resistor R4 is pulled down, although the power supply current acquisition and MCU control output and power supply management fault function safety output are high, the U1 and gate output port is high, the port B of the triode Q3 is pulled down, the port C and the port E of the triode Q3 are not conducted, the G pole potential of the P-channel field effect tube Q5 is equal to the S pole potential and in a closed state, the voltage acquired by the power supply voltage acquisition 2 is 0, and the current cannot form a loop due to the closing of the P-channel field effect tube Q5, so that the power supply current acquisition is 0, and the Z1 device is positioned to generate faults;

(2) The port B and the port C of the triode Q2 have short-circuit faults:

at the moment, the power current acquisition and MCU control output and the power management fault function safety output are high, the U1 and the gate output port are high, the voltage of the port 1 of the acting and resistor R4 is high, and the port 1 of the acting and resistor R8 is at a high level through the port C and the port B of the triode Q2; the voltage of the voltage regulator tube Z2 acts on the port No. 2 through voltage division of R8 and R9, and the voltage of the voltage regulator tube Z2 acting on the port No. 1 of the resistor R10 is larger than the voltage in a normal range; at the moment, because the port 1 of the R6 is always in a high level, the voltage of the port B of the triode Q3 is greater than the starting voltage, the port C of the triode Q3 is communicated with the port E, the P-channel field effect transistor Q5 is communicated, and the power supply voltage acquisition 2 outputs a high level;

(3) If the chip of the AND logic chip U1 breaks down, the output end of the No. 3 is always at a low level, so that the P-channel field effect transistor Q5 is closed;

if the D pole and the S pole of the P-channel field effect transistor Q5 have short circuit faults, although the power supply voltage acquisition 1, the power supply voltage acquisition 2 and the power supply current acquisition are in normal ranges, the P-channel field effect transistor Q5 cannot be controlled through the MCU control output and the power supply management fault function safety output.

Images