CN111785619A - Process method for shielding trench of gate trench type MOSFET - Google Patents

Abstract

Translated fromChinese

本发明公开了一种屏蔽栅沟槽型MOSFET的沟槽的工艺方法,包含：步骤一，在半导体基板上淀积形成硬掩模层，再刻蚀形成多个沟槽，在所述沟槽中形成介质层并淀积填充多晶硅，完成回刻后形成沟槽中的下部电极；步骤二，在沟槽的上半部淀积形成保护介质层；步骤三，在沟槽内整体淀积一层多晶硅层间氧化层；步骤四，对淀积的多晶硅层间氧化层进行CMP工艺；步骤五，继续对多晶硅层间氧化层进行刻蚀工艺，使沟槽内剩余的多晶硅层间氧化层达到设计厚度，成为上部多晶硅与下部多晶硅之间的隔离介质层。本发明工艺方法通过一层保护氧化层，对沟槽侧壁尤其是沟槽顶部拐角处进行保护，能够得到近乎垂直的沟槽侧壁形貌，改善沟槽短沟道的问题。

The invention discloses a process method for shielding a trench of a gate trench type MOSFET, comprising: step 1, depositing a hard mask layer on a semiconductor substrate, then etching to form a plurality of trenches, In step 2, a protective dielectric layer is deposited on the upper half of the trench to form a protective dielectric layer; in step 3, a whole layer is deposited in the trench. layer polysilicon interlayer oxide layer; step 4, perform CMP process on the deposited polysilicon interlayer oxide layer; step 5, continue to perform etching process on the polysilicon interlayer oxide layer, so that the remaining polysilicon interlayer oxide layer in the trench reaches The designed thickness becomes the isolation dielectric layer between the upper polysilicon and the lower polysilicon. The process method of the invention protects the trench sidewalls, especially the top corners of the trenches, through a protective oxide layer, so that a nearly vertical trench sidewall morphology can be obtained, and the problem of short trenches can be improved.

Description

Translated fromChinese

屏蔽栅沟槽型MOSFET的沟槽的工艺方法Process method for shielding trench of gate trench type MOSFET

技术领域technical field

本发明涉及半导体集成电路制造领域，特别涉及一种屏蔽栅沟槽型MOSFET的沟槽的工艺方法。The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a process method for shielding a trench of a gate trench type MOSFET.

背景技术Background technique

沟槽型双层栅MOS，作为一种功率器件，具有击穿电压高，导通电阻低，开关速度快的特点。屏蔽栅沟槽型MOSFET的结构其沟槽分为上下两部分，沟槽下半部填充多晶硅为源极，沟槽上半部的多晶硅为栅极，栅极、源极以及沟槽之间均以氧化层隔离。其特点是源极沟槽内填充的多晶硅仅占沟槽内部空间的一半左右，使得源极接触孔需要做得较深才能与沟槽下部填充的多晶硅接触。该器件的工艺方法是，先在硅衬底上淀积一层氧化层作为硬掩膜，然后利用光刻胶对硬掩膜进行定义图形，再去除光刻胶，以硬掩膜定义的图形刻蚀衬底形成沟槽，对沟槽进行倒角之后再淀积一层氧化层，将沟槽内填充满第一层多晶硅，并进行回刻蚀形成源极，再淀积厚的氧化层，CMP及湿法工艺刻蚀之后形成多晶硅间氧化膜；淀积多晶硅并刻蚀形成栅极，最后再进行体区注入及推进、源极注入及推进、层间介质淀积等后续工艺。Trench-type double-gate MOS, as a power device, has the characteristics of high breakdown voltage, low on-resistance and fast switching speed. The structure of the shielded gate trench MOSFET is divided into upper and lower parts. The lower half of the trench is filled with polysilicon as the source, and the upper half of the trench is filled with polysilicon as the gate. Isolated with oxide layer. Its characteristic is that the polysilicon filled in the source trench only occupies about half of the inner space of the trench, so that the source contact hole needs to be made deeper to be in contact with the polysilicon filled in the lower part of the trench. The process method of the device is to first deposit an oxide layer on the silicon substrate as a hard mask, then use photoresist to define the pattern of the hard mask, then remove the photoresist, and use the hard mask to define the pattern Etch the substrate to form a trench, chamfer the trench and then deposit an oxide layer, fill the trench with the first layer of polysilicon, etch back to form the source, and then deposit a thick oxide layer , After CMP and wet process etching, an oxide film between polysilicon is formed; polysilicon is deposited and etched to form a gate, and finally body region implantation and advancement, source implantation and advancement, interlayer dielectric deposition and other subsequent processes are performed.

100V屏蔽栅沟槽型MOSFET产品在制作多晶硅间介质层的时候，由于沟槽侧壁上的衬垫氧化层较薄，在多晶硅间介质层淀积后沟槽的顶部边沿会变圆化，即沟槽内壁向上会逐渐平滑过渡到沟槽顶部的硅表面，如图1中所示，是现有技术工艺下形成的沟槽剖面显微示意图，图中虚线框内显示沟槽顶部拐角圆化，垂直的形貌被破坏。这种形貌在后续进行沟道源区注入时注入结深偏深，从而引起短沟道等问题，在后段进行探针测试时显示器件的饱和漏电流I_DSS偏大以及阈值电压V_th不稳定等问题。因此，我们需要沟槽的顶部拐角尽量接近90°的理想状态。When the 100V shielded gate trench type MOSFET product is made of the inter-polysilicon dielectric layer, due to the thin liner oxide layer on the sidewall of the trench, the top edge of the trench will become rounded after the inter-polysilicon dielectric layer is deposited, that is, The inner wall of the trench will gradually and smoothly transition upward to the silicon surface at the top of the trench. As shown in Figure 1, it is a microscopic schematic diagram of the trench cross-section formed under the prior art process. The dotted box in the figure shows that the corners of the top of the trench are rounded , the vertical topography is destroyed. This kind of morphology is deeply implanted into the junction when the channel source region is implanted later, which causes problems such as short channel. The probe test in the later stage shows that the saturated leakage current I_DSS of the device is too large and the threshold voltage V_th instability, etc. Therefore, we need the top corners of the trenches to be as close as possible to the ideal state of 90°.

发明内容SUMMARY OF THE INVENTION

本发明所要解决的技术问题是提供一种屏蔽栅沟槽型MOSFET的沟槽的工艺方法，避免沟槽顶部削角的问题。The technical problem to be solved by the present invention is to provide a process method for shielding the trench of the gate trench MOSFET, so as to avoid the problem of chamfering at the top of the trench.

为解决上述问题，本发明所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，包含如下的工艺步骤：In order to solve the above problems, the process method for shielding the trench of the gate trench MOSFET according to the present invention includes the following process steps:

步骤一，在半导体基板上淀积形成硬掩模层，对硬掩模层进行刻蚀图案化后，以图案化的硬掩模层作为遮挡对半导体基板进行刻蚀形成多个沟槽，在所述沟槽中形成介质层并淀积填充多晶硅，完成回刻后形成沟槽中的下部电极；Step 1, depositing a hard mask layer on the semiconductor substrate, etching and patterning the hard mask layer, using the patterned hard mask layer as a shield to etch the semiconductor substrate to form a plurality of grooves, A dielectric layer is formed in the trench, and polysilicon is deposited and filled, and the lower electrode in the trench is formed after the etching back is completed;

步骤二，在沟槽的上半部淀积形成保护介质层；Step 2, depositing a protective dielectric layer on the upper half of the trench;

步骤三，在沟槽内整体淀积一层多晶硅层间氧化层；Step 3, depositing a polysilicon interlayer oxide layer in the trench as a whole;

步骤四，对淀积的多晶硅层间氧化层进行CMP工艺；Step 4, performing CMP process on the deposited polysilicon interlayer oxide layer;

步骤五，继续对多晶硅层间氧化层进行刻蚀工艺，使沟槽内剩余的多晶硅层间氧化层达到设计厚度，成为上部多晶硅与下部多晶硅之间的隔离介质层。Step 5: Continue to perform the etching process on the polysilicon interlayer oxide layer, so that the remaining polysilicon interlayer oxide layer in the trench reaches the designed thickness and becomes an isolation dielectric layer between the upper polysilicon and the lower polysilicon.

进一步的改进是，步骤一中所述的半导体基板为硅衬底或者是硅外延；所述硬掩模层为ONO层。A further improvement is that the semiconductor substrate described instep 1 is a silicon substrate or a silicon epitaxy; the hard mask layer is an ONO layer.

进一步的改进是，步骤二中所述的保护介质层采用APCVD法进行淀积，所述形成的保护介质层附着于沟槽上部包括硬掩模层的侧壁及沟槽内下部的多晶硅上表面。A further improvement is that the protective dielectric layer described instep 2 is deposited by APCVD method, and the formed protective dielectric layer is attached to the upper part of the trench including the sidewall of the hard mask layer and the upper surface of the polysilicon in the lower part of the trench. .

进一步的改进是，步骤二中形成保护介质层厚度为

淀积完成之后还包括热退火步骤。A further improvement is that the thickness of the protective dielectric layer formed instep 2 is

A thermal annealing step is also included after the deposition is complete.

进一步的改进是，所述步骤三中淀积的多晶硅层间氧化层填充满沟槽并在半导体基板表面整体淀积，以覆盖硬掩模层。A further improvement is that the polysilicon interlayer oxide layer deposited in the third step fills the trenches and is integrally deposited on the surface of the semiconductor substrate to cover the hard mask layer.

进一步的改进是，所述步骤四中对淀积的多晶硅层间氧化层进行CMP，以硬掩模层中的氮化层为研磨终止点，研磨至ONO层中的氮化层表面。A further improvement is that in the fourth step, CMP is performed on the deposited polysilicon interlayer oxide layer, and the nitride layer in the hard mask layer is used as the grinding termination point to grind to the surface of the nitride layer in the ONO layer.

进一步的改进是，所述步骤五中，采用湿法刻蚀工艺，对硬掩模中剩余的氮化硅层及氧化层，以及淀积的多晶硅层间氧化层进行刻蚀，包括去除沟槽侧壁的保护介质层；最终是沟槽内下部多晶硅上方剩余的多晶硅层间氧化层达到预定厚度。A further improvement is that in the fifth step, a wet etching process is used to etch the remaining silicon nitride layer and oxide layer in the hard mask, as well as the deposited polysilicon interlayer oxide layer, including removing the trenches. The protective dielectric layer of the sidewall; finally, the remaining polysilicon interlayer oxide layer above the lower polysilicon in the trench reaches a predetermined thickness.

进一步的改进是，还包括后续工艺步骤，在沟槽内淀积第二层多晶硅并回刻，以形成沟槽上部电极。A further improvement is that a subsequent process step is also included, and a second layer of polysilicon is deposited in the trench and etched back to form the upper electrode of the trench.

本发明所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，在进行多晶硅层间介质氧化层淀积之前，先形成一层保护氧化层，对沟槽侧壁尤其是沟槽顶部拐角处进行保护，避免在后续工艺中沟槽顶部拐角被削角而变得圆化，能够得到近乎垂直的沟槽侧壁形貌，改善沟槽短沟道的问题。In the process method for shielding the trench of the gate trench type MOSFET according to the present invention, before the deposition of the inter-polysilicon dielectric oxide layer, a protective oxide layer is first formed, and the sidewalls of the trench, especially the corners of the top of the trench are formed. The protection is performed to prevent the corners of the top of the trench from being rounded due to chamfering in the subsequent process, so that a nearly vertical topography of the trench sidewall can be obtained, and the problem of short trenches can be improved.

附图说明Description of drawings

图1是现有工艺形成的沟槽顶部显微图。Figure 1 is a micrograph of the top of a trench formed by a prior art process.

图2～6是本发明涉及的工艺步骤示意图。2 to 6 are schematic diagrams of process steps involved in the present invention.

图7是本发明工艺形成的沟槽顶部显微图。Figure 7 is a micrograph of the top of the trench formed by the process of the present invention.

图8是本发明工艺步骤流程图。Figure 8 is a flow chart of the process steps of the present invention.

附图标记说明Description of reference numerals

1是半导体基板，2是沟槽底部介质层，3是沟槽下部多晶硅，4是硬掩模层，5是保护介质层，6是多晶硅层间介质层。1 is the semiconductor substrate, 2 is the dielectric layer at the bottom of the trench, 3 is the polysilicon at the bottom of the trench, 4 is the hard mask layer, 5 is the protective dielectric layer, and 6 is the polysilicon interlayer dielectric layer.

具体实施方式Detailed ways

本发明所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，主要针对屏蔽栅沟槽型MOSFET的沟槽的多晶硅填充工艺，主要是沟槽的多晶硅层间介质层淀积之后避免出现沟槽顶部被削角的问题，本发明工艺方法能改善沟槽侧壁顶部拐角的问题，使得沟槽顶部拐角近乎垂直。The process method for the trench of the shielded gate trench MOSFET of the present invention is mainly aimed at the polysilicon filling process of the trench of the shielded gate trench MOSFET, mainly to avoid the occurrence of trenches after the polysilicon interlayer dielectric layer of the trench is deposited. The problem that the top corner of the trench is chamfered, the process method of the present invention can improve the problem of the top corner of the trench sidewall, so that the top corner of the trench is nearly vertical.

本发明所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，包含如下的工艺步骤：The process method for shielding the trench of the gate trench type MOSFET according to the present invention includes the following process steps:

步骤一，如图2所示，在半导体基板上，比如硅衬底或者是外延层上，淀积形成硬掩模层，本实施例硬掩模层以ONO层为例，即在半导体基板表面依次淀积氧化层-氮化层-氧化层，形成ONO的复合层。对硬掩模层进行刻蚀图案化后，以图案化的硬掩模层作为遮挡对半导体基板进行刻蚀形成多个沟槽(本实施例图中仅示意一个沟槽)，在所述沟槽中形成介质层并淀积填充多晶硅，完成回刻后形成沟槽中的下部电极；Step 1, as shown in FIG. 2, a hard mask layer is deposited on a semiconductor substrate, such as a silicon substrate or an epitaxial layer. In this embodiment, the hard mask layer takes the ONO layer as an example, that is, on the surface of the semiconductor substrate. The oxide layer - the nitride layer - the oxide layer are sequentially deposited to form a composite layer of ONO. After the hard mask layer is etched and patterned, the semiconductor substrate is etched with the patterned hard mask layer as a shield to form a plurality of trenches (only one trench is shown in the figure in this embodiment). A dielectric layer is formed in the groove, and polysilicon is deposited and filled, and the lower electrode in the groove is formed after the etching back is completed;

步骤二，如图3所示，在沟槽的上半部淀积形成保护介质层；优选的是采用APCVD法进行淀积，所述形成的保护介质层附着于沟槽上部包括硬掩模层的侧壁及沟槽内下部的多晶硅上表面。形成保护介质层厚度为

比如

Step 2, as shown in FIG. 3 , a protective dielectric layer is deposited on the upper half of the trench; preferably, APCVD is used for deposition, and the formed protective dielectric layer is attached to the upper part of the trench and includes a hard mask layer sidewalls and the upper surface of polysilicon in the lower part of the trench. The thickness of the protective dielectric layer is formed as

for example

淀积完成之后还进行一些热退火步骤。Some thermal annealing steps are also performed after the deposition is complete.

步骤三，如图4所示，在沟槽内整体淀积一层多晶硅层间氧化层；淀积的多晶硅层间氧化层填充满沟槽并在半导体基板表面整体淀积，将ONO硬掩模层也整体覆盖住。Step 3, as shown in FIG. 4, deposit a layer of polysilicon interlayer oxide layer in the trench as a whole; the deposited polysilicon interlayer oxide layer fills the trench and is deposited on the surface of the semiconductor substrate as a whole, and the ONO hard mask is applied. The layers are also covered in their entirety.

步骤四，如图5所示，对淀积的多晶硅层间氧化层进行CMP工艺；从淀积的膜表面向下研磨，以硬掩模层中的氮化层为研磨终止点，研磨至ONO层中的氮化层表面。Step 4, as shown in Figure 5, perform CMP process on the deposited polysilicon interlayer oxide layer; grind down from the deposited film surface, take the nitride layer in the hard mask layer as the grinding termination point, and grind to ONO The surface of the nitride layer in the layer.

步骤五，继续对多晶硅层间氧化层进行湿法刻蚀工艺，对硬掩模中剩余的氮化硅层及氧化层，以及淀积的多晶硅层间氧化层进行刻蚀，包括去除沟槽侧壁的保护介质层，如图6所示；使沟槽内剩余的多晶硅层间氧化层达到设计厚度，成为上部多晶硅与下部多晶硅之间的隔离介质层。Step 5: Continue to perform wet etching process on the polysilicon interlayer oxide layer, etch the remaining silicon nitride layer and oxide layer in the hard mask, and the deposited polysilicon interlayer oxide layer, including removing the trench side The protective dielectric layer of the wall is shown in Figure 6; the remaining polysilicon interlayer oxide layer in the trench reaches the designed thickness, and becomes the isolation dielectric layer between the upper polysilicon and the lower polysilicon.

本发明上述工艺在多晶硅层间氧化层淀积之前，先在沟槽内壁形成一层保护氧化层，放置后续的多晶硅层间氧化层淀积工艺导致沟槽顶部拐角圆化，由于圆化的拐角会导致源区注入时，注入结深过深从而引发短沟道效应。本发明淀积保护层对沟槽侧壁进行保护，保证了沟槽顶部形貌不受影响，从而得到近乎直角的沟槽顶部，提高了器件的性能。The above-mentioned process of the present invention first forms a protective oxide layer on the inner wall of the trench before the deposition of the polysilicon interlayer oxide layer, and the subsequent polysilicon interlayer oxide layer deposition process causes the top corner of the trench to be rounded. When the source region is implanted, the implanted junction is too deep to cause a short channel effect. In the present invention, the protective layer is deposited to protect the sidewall of the trench, ensuring that the top shape of the trench is not affected, thereby obtaining a trench top with a nearly right angle, and improving the performance of the device.

如图7所示，是采用本发明工艺后形成的沟槽的剖面显微图，图中虚线框内的显示沟槽顶部拐角接近90°直角，与图1相比顶部形貌得到明显改善。As shown in FIG. 7 , it is a cross-sectional micrograph of the trench formed by the process of the present invention. The top corner of the trench in the dotted frame is close to a right angle of 90°, and the top shape is significantly improved compared with FIG. 1 .

在本发明所述的工艺之后，还包括后续传统的工艺步骤，即在沟槽内淀积第二层多晶硅并回刻，以形成沟槽上部电极，然后进行离子注入形成源区等工艺，是为公知技术，在此不再赘述。After the process of the present invention, it also includes the following traditional process steps, that is, depositing a second layer of polysilicon in the trench and etching back to form the upper electrode of the trench, and then performing ion implantation to form the source region and other processes. It is a well-known technology and will not be repeated here.

以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention are possible for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (8)

Translated fromChinese

1.一种屏蔽栅沟槽型MOSFET的沟槽的工艺方法，其特征在于：包含如下的工艺步骤：1. a process method of shielding the trench of gate trench type MOSFET, is characterized in that: comprise following process steps:步骤一，在半导体基板上淀积形成硬掩模层，对硬掩模层进行刻蚀图案化后，以图案化的硬掩模层作为遮挡对半导体基板进行刻蚀形成多个沟槽，在所述沟槽中形成介质层并淀积填充多晶硅，完成回刻后形成沟槽中的下部电极；Step 1, depositing a hard mask layer on the semiconductor substrate, etching and patterning the hard mask layer, using the patterned hard mask layer as a shield to etch the semiconductor substrate to form a plurality of grooves, A dielectric layer is formed in the trench, and polysilicon is deposited and filled, and the lower electrode in the trench is formed after the etching back is completed;步骤二，在沟槽的上半部淀积形成保护介质层；Step 2, depositing a protective dielectric layer on the upper half of the trench;步骤三，在沟槽内整体淀积一层多晶硅层间氧化层；Step 3, depositing a polysilicon interlayer oxide layer in the trench as a whole;步骤四，对淀积的多晶硅层间氧化层进行CMP工艺；Step 4, performing CMP process on the deposited polysilicon interlayer oxide layer;步骤五，继续对多晶硅层间氧化层进行刻蚀工艺，使沟槽内剩余的多晶硅层间氧化层达到设计厚度，成为上部多晶硅与下部多晶硅之间的隔离介质层。Step 5: Continue to perform the etching process on the polysilicon interlayer oxide layer, so that the remaining polysilicon interlayer oxide layer in the trench reaches the designed thickness and becomes an isolation dielectric layer between the upper polysilicon and the lower polysilicon.2.如权利要求1所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，其特征在于：步骤一中所述的半导体基板为硅衬底或者是硅外延；所述硬掩模层为ONO层。2 . The method of claim 1 , wherein the semiconductor substrate described in step 1 is a silicon substrate or a silicon epitaxy; the hard mask layer is ONO layer.3.如权利要求1所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，其特征在于：步骤二中所述的保护介质层采用APCVD法进行淀积，所述形成的保护介质层附着于沟槽上部包括硬掩模层的侧壁及沟槽内下部的多晶硅上表面。3. The method of claim 1, wherein the protective dielectric layer described in step 2 is deposited by APCVD method, and the formed protective dielectric layer is adhered to The upper part of the trench includes the sidewall of the hard mask layer and the upper surface of polysilicon in the lower part of the trench.4.如权利要求1所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，其特征在于：步骤二中形成保护介质层厚度为

淀积完成之后还包括热退火步骤。4. The process method for shielding the trench of the gate trench MOSFET as claimed in claim 1, wherein the thickness of the protective dielectric layer formed in step 2 is

A thermal annealing step is also included after the deposition is complete.5.如权利要求1所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，其特征在于：所述步骤三中淀积的多晶硅层间氧化层填充满沟槽并在半导体基板表面整体淀积，以覆盖硬掩模层。5. The method of claim 1, wherein the polysilicon interlayer oxide layer deposited in the step 3 fills the trench and is integrally deposited on the surface of the semiconductor substrate product to cover the hard mask layer.6.如权利要求1或2的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，其特征在于：所述步骤四中对淀积的多晶硅层间氧化层进行CMP，以硬掩模层中的氮化层为研磨终止点，研磨至ONO层中的氮化层表面。6. The process method for the trench of the shielded gate trench type MOSFET according to claim 1 or 2, wherein in the step 4, CMP is performed on the deposited polysilicon interlayer oxide layer, with the The nitride layer is the grinding termination point, and is ground to the surface of the nitride layer in the ONO layer.7.如权利要求1所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，其特征在于：所述步骤五中，采用湿法刻蚀工艺，对硬掩模中剩余的氮化硅层及氧化层，以及淀积的多晶硅层间氧化层进行刻蚀，包括去除沟槽侧壁的保护介质层；最终是沟槽内下部多晶硅上方剩余的多晶硅层间氧化层达到预定厚度。7 . The method of claim 1 , wherein in the step 5, a wet etching process is used to remove the remaining silicon nitride layer in the hard mask. 8 . And the oxide layer, and the deposited polysilicon interlayer oxide layer are etched, including removing the protective dielectric layer on the trench sidewall; finally, the remaining polysilicon interlayer oxide layer above the polysilicon in the lower part of the trench reaches a predetermined thickness.8.如权利要求1所述的屏蔽栅沟槽型MOSFET的沟槽的工艺方法，其特征在于：还包括后续工艺步骤，在沟槽内淀积第二层多晶硅并回刻，以形成沟槽上部电极。8. The method of claim 1, further comprising a subsequent process step of depositing a second layer of polysilicon in the trench and etching back to form the trench upper electrode.

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