CN111755409A - Semiconductor packaging substrate and its manufacturing method and electronic package and its manufacturing method - Google Patents

Abstract

A method for preparing semiconductor package substrate includes forming solder-proof structure with open hole on circuit structure to expose circuit structure to open hole for forming cup-shaped soldering seat on exposed circuit layer and hole wall of open hole.

Description

Translated fromChinese

半导体封装基板及其制法与电子封装件及其制法Semiconductor packaging substrate and its manufacturing method and electronic package and its manufacturing method

技术领域technical field

本发明涉及一种封装基材，尤其涉及一种能提升产品可靠度的半导体封装基板及其电子封装件。The invention relates to a packaging substrate, in particular to a semiconductor packaging substrate and an electronic package thereof which can improve product reliability.

背景技术Background technique

随着产业应用的发展，近年来逐渐朝着如人工智能(AI)芯片、高阶芯片或堆叠芯片等大尺寸芯片的封装规格的趋势进行研发，如3D或2.5D IC工艺，以应用于高密度线路/高传输速度/高叠层数/大尺寸设计的高阶产品，如人工智能(AI)芯片、GPU等。With the development of industrial applications, in recent years, it has gradually moved towards the trend of packaging specifications for large-scale chips such as artificial intelligence (AI) chips, high-end chips or stacked chips, such as 3D or 2.5D IC processes, to be applied to high-end chips. High-end products such as artificial intelligence (AI) chips, GPUs, etc., with dense lines/high transmission speed/high stack count/large size design.

因此，业界遂改用大尺寸板面的倒装芯片封装基板，如40*40、70*70或其它更厚且大结构的板型，以承载如人工智能(AI)芯片、高阶芯片或堆叠芯片等大尺寸芯片。Therefore, the industry has switched to flip-chip packaging substrates with large-sized boards, such as 40*40, 70*70 or other thicker and larger-structure board types, to carry artificial intelligence (AI) chips, high-end chips or Large-sized chips such as stacked chips.

如图1A所示，该电子装置1包括：一电路板18、一设于该电路板18上的封装基板1a以及一结合于该封装基板1a上的半导体芯片19。具体地，如图1B所示，该封装基板1a包括一核心层10、设于该核心层10上的线路增层部11及设于该线路增层部11上的防焊层12a,12b，且令该防焊层12a,12b外露出该线路增层部11最外侧的线路层，以供作为接点(即I/O)11a,11b，以于上侧(如图1C所示的置晶侧)借由焊锡凸块13a接置半导体芯片19及于下侧(如图1D所示的植球侧或BGA)借由焊锡球13b接置电路板18，而制成电子封装产品。As shown in FIG. 1A , the electronic device 1 includes: acircuit board 18 , apackage substrate 1 a disposed on thecircuit board 18 , and asemiconductor chip 19 bonded to thepackage substrate 1 a . Specifically, as shown in FIG. 1B , thepackage substrate 1 a includes acore layer 10 , a circuit build-up portion 11 disposed on thecore layer 10 , andsolder resist layers 12 a and 12 b disposed on the circuit build-upportion 11 , And thesolder mask layers 12a, 12b are exposed to the outermost circuit layers of the circuit build-upportion 11 for serving as contacts (ie, I/O) 11a, 11b, so as to be placed on the upper side (as shown in FIG. 1C ). Thesemiconductor chip 19 is connected with the solder bumps 13a and thecircuit board 18 is connected with thesolder balls 13b on the lower side (the ball-mounted side or BGA as shown in FIG. 1D ) to form an electronic package product.

公知核心层10的制作中，采用玻纤配合环氧树酯所组成的基材，如BT(Bismaleimide Triazine)、FR4或FR5等，再于其上进行导通孔工艺，如机械钻孔、激光钻孔或双锥状盲孔等成孔步骤，再于孔中电镀形成导电材及填充树脂(plugin)。此外，线路增层部11的增层方法还使用ABF种类的材料作为介电层，且该防焊层12a,12b的材质选择为使用绿漆或油墨等材料。In the production of the knowncore layer 10, a substrate composed of glass fiber and epoxy resin, such as BT (Bismaleimide Triazine), FR4 or FR5, is used, and then a via process is performed on it, such as mechanical drilling, laser Hole-forming steps such as drilling or double-tapered blind holes, and then electroplating in the holes to form conductive materials and fill resin (plugin). In addition, the build-up method of the line build-up portion 11 also uses an ABF type material as the dielectric layer, and the material of thesolder resist layers 12a, 12b is selected to use materials such as green paint or ink.

然而，公知焊锡球13b与接点11b的金属接触面仅为单一表面(如该接点11b的顶面)，因而金属接触面积极小，致使该焊锡球13b容易于该接点11b之处发生断裂，甚至因结合力差而发生掉球或脱落的情况(如该焊锡球13”的顶面)。However, the metal contact surface of the knownsolder ball 13b and thecontact 11b is only a single surface (such as the top surface of thecontact 11b), so the metal contact surface is actively small, so that thesolder ball 13b is prone to break at thecontact 11b, or even Dropped or dropped balls due to poor bonding (such as the top surface of thesolder ball 13").

此外，如图1A所示，公知电子装置1于封装过程中，当该封装基板1a应用于大尺寸时，该封装基板1a的刚性不足，造成于封装高温工艺时，因该封装基板1a于各层间材料的热膨胀系数(Coefficient of thermal expansion，简称CTE)不一致而会发生弯翘(warpage)，导致其与该半导体芯片19之间连接不良(如焊锡材料13’未接合)、或于焊接时，其与该电路板18之间会发生连接不良(如焊锡球13”未接合)，更严重者，可能因为应力关系会造成该半导体芯片19本身的电性失效或破裂。In addition, as shown in FIG. 1A , when thepackaging substrate 1 a is applied to a large size in the packaging process of the conventional electronic device 1 , the rigidity of thepackaging substrate 1 a is insufficient, resulting in high temperature packaging process, because thepackaging substrate 1 a is in each The coefficient of thermal expansion (CTE) of the interlayer materials is inconsistent and warpage occurs, resulting in poor connection with the semiconductor chip 19 (for example, the solder material 13' is not joined), or when soldering , there will be poor connection between it and the circuit board 18 (for example, thesolder balls 13 ″ are not joined), and more seriously, thesemiconductor chip 19 itself may be electrically failed or broken due to stress.

另一方面，若将该核心层10的厚度增加，以增加该封装基板1a的刚性强度而降低该封装基板1a的弯翘程度，但却会产生其它缺点，例如，加厚该核心层10的方式，不符合朝薄型化或微小化的封装设计的需求。具体地，为了防止该封装基板1a发生弯翘，进而增加该核心层10的厚度，导致整个该封装基板1a变厚，不利于基板的制作，且加工成本提高。On the other hand, if the thickness of thecore layer 10 is increased to increase the rigidity of thepackage substrate 1a and reduce the warping degree of thepackage substrate 1a, other disadvantages will occur, for example, the thickness of thecore layer 10 will be increased. This method does not meet the needs of thinning or miniaturized package design. Specifically, in order to prevent thepackaging substrate 1a from warping, and further increase the thickness of thecore layer 10, theentire packaging substrate 1a becomes thicker, which is not conducive to the manufacture of the substrate and increases the processing cost.

因此，如何克服上述公知技术的种种问题，实已成为目前业界亟待克服的难题。Therefore, how to overcome the above-mentioned various problems of the prior art has actually become a difficult problem to be overcome in the current industry.

发明内容SUMMARY OF THE INVENTION

鉴于上述公知技术的缺陷，本发明提供一种半导体封装基板及其制法与电子封装件及其制法，能有效避免该焊锡球发生断裂或脱落的情况。In view of the above-mentioned defects of the prior art, the present invention provides a semiconductor package substrate and a manufacturing method thereof, an electronic package and a manufacturing method thereof, which can effectively prevent the solder balls from breaking or falling off.

本发明的半导体封装基板，包括线路结构、防焊结构及焊座。线路结构具有线路层；防焊结构设于该线路结构上，且该防焊结构具有开孔，以令该线路层部分外露于该开孔；焊座呈杯状结构，其以电镀形成并自该线路层外露的表面延伸到该开孔的孔壁上，该焊座的材质与该线路层相同，例如为铜。The semiconductor package substrate of the present invention includes a circuit structure, a solder resist structure and a solder seat. The circuit structure has a circuit layer; the solder mask structure is arranged on the circuit structure, and the solder mask structure has an opening, so that the circuit layer is partially exposed to the opening; the solder seat is a cup-shaped structure, which is formed by electroplating and is self-contained. The exposed surface of the circuit layer extends to the hole wall of the opening, and the material of the solder pad is the same as that of the circuit layer, such as copper.

本发明还提供一种半导体封装基板的制法，包括：提供一具有线路层的线路结构；形成防焊结构于该线路结构上，且在该防焊结构形成有开孔，以令该线路层部分外露于该开孔；以及形成焊座于该外露的线路层与该开孔的孔壁上。The present invention also provides a method for manufacturing a semiconductor package substrate, which includes: providing a circuit structure with a circuit layer; forming a solder mask structure on the circuit structure, and forming an opening in the solder mask structure to make the circuit layer part is exposed in the opening; and a solder pad is formed on the exposed circuit layer and the hole wall of the opening.

前述的半导体封装基板及其制法中，该防焊结构为单一绝缘层。In the aforementioned semiconductor package substrate and its manufacturing method, the solder resist structure is a single insulating layer.

前述的制法中，该焊座呈杯状结构，其以电镀形成自该线路层外露的表面并延伸到该开孔的孔壁上，该焊座的材质与该线路层相同，例如为铜。In the aforesaid manufacturing method, the soldering seat has a cup-shaped structure, which is formed from the exposed surface of the circuit layer by electroplating and extends to the hole wall of the opening. The material of the soldering seat is the same as that of the circuit layer, such as copper .

前述的半导体封装基板及其制法中，该防焊结构还包括金属支撑层与包覆该金属支撑层的绝缘层，该金属支撑层以结合材结合该线路结构。In the aforementioned semiconductor package substrate and its manufacturing method, the solder mask structure further includes a metal support layer and an insulating layer covering the metal support layer, and the metal support layer is combined with the circuit structure by a bonding material.

前述的半导体封装基板及其制法中，还包括设于该焊座上的导电元件。In the aforementioned semiconductor package substrate and its manufacturing method, a conductive element disposed on the soldering seat is also included.

前述的半导体封装基板及其制法中，还包括设于该焊座上的导接块，该导接块为一体积小于该开孔的焊锡球。The aforementioned semiconductor package substrate and the manufacturing method thereof further include a conducting block disposed on the soldering seat, and the conducting block is a solder ball with an area smaller than that of the opening.

前述的半导体封装基板及其制法中，该焊座与线路层的接触部位形成有具适当厚度的凸块底部。In the aforementioned semiconductor package substrate and its manufacturing method, a bump bottom with an appropriate thickness is formed at the contact portion between the solder pad and the circuit layer.

本发明还提供一种电子封装件，包括前述的半导体封装基板以及电子元件。其中，该线路结构具有相对的第一侧与第二侧，且该线路层配置于该第一侧与第二侧，并使该防焊结构设于该线路结构的第二侧上；电子元件，其设于该线路结构的第一侧上并电性连接该线路结构的第一侧的线路层。The present invention also provides an electronic package, comprising the aforementioned semiconductor package substrate and electronic components. Wherein, the circuit structure has opposite first side and second side, and the circuit layer is arranged on the first side and the second side, and the solder mask structure is arranged on the second side of the circuit structure; electronic component , which is arranged on the first side of the circuit structure and is electrically connected to the circuit layer on the first side of the circuit structure.

本发明又提供一种电子封装件的制法，包括：提供一前述的半导体封装基板，其中，该线路结构具有相对的第一侧与第二侧，且该线路层配置于该第一侧与第二侧，并使该防焊结构设于该线路结构的第二侧上；以及设置电子元件于该线路结构的第一侧上，且该电子元件电性连接该线路结构的第一侧的线路层。The present invention further provides a method for manufacturing an electronic package, comprising: providing the aforementioned semiconductor package substrate, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit layer is disposed on the first side and the second side. and disposing the solder mask structure on the second side of the circuit structure; and disposing an electronic component on the first side of the circuit structure, and the electronic component is electrically connected to the first side of the circuit structure circuit layer.

前述的电子封装件及其制法中，还包括封装层，其设于该半导体封装基板上，以结合该电子元件和半导体封装基板。The aforementioned electronic package and its manufacturing method further include an encapsulation layer disposed on the semiconductor package substrate to combine the electronic element and the semiconductor package substrate.

前述的电子封装件及其制法中，该电子元件以多个导电凸块设于该线路结构的第一侧上。In the aforementioned electronic package and its manufacturing method, the electronic component is disposed on the first side of the circuit structure with a plurality of conductive bumps.

由上可知，本发明的半导体封装基板及其制法与电子封装件及其制法，主要借由于该外露的线路层与该防焊结构的开孔的孔壁上形成焊座，以增加该导电元件的金属接触面积，进而提升导电元件(焊锡球)与焊座间的结合力，故相较于公知技术，本发明能有效避免该导电元件发生断裂，还能避免发生掉球或脱落的情况。As can be seen from the above, the semiconductor package substrate and its manufacturing method and the electronic package and its manufacturing method of the present invention are mainly due to the exposed circuit layer and the soldering seat formed on the hole wall of the opening of the solder mask structure, so as to increase the The metal contact area of the conductive element improves the bonding force between the conductive element (solder ball) and the solder seat. Therefore, compared with the known technology, the present invention can effectively prevent the conductive element from breaking, and can also avoid the occurrence of falling balls or falling off. Happening.

附图说明Description of drawings

图1A为公知电子装置的剖视示意图。FIG. 1A is a schematic cross-sectional view of a conventional electronic device.

图1B为公知倒装芯片式封装基板的剖视示意图。FIG. 1B is a schematic cross-sectional view of a conventional flip-chip packaging substrate.

图1C为图1B的上视示意图。FIG. 1C is a schematic top view of FIG. 1B .

图1D为图1B的下视示意图。FIG. 1D is a schematic bottom view of FIG. 1B .

图2A至图2B为本发明的半导体封装基板的第一实施例的制法的剖视示意图。2A to 2B are schematic cross-sectional views of a method for manufacturing a semiconductor package substrate according to a first embodiment of the present invention.

图2C为本发明的电子封装件的第一实施例的剖视示意图。2C is a schematic cross-sectional view of the first embodiment of the electronic package of the present invention.

图3A至图3C为本发明的半导体封装基板的第二实施例的制法的剖视示意图。3A to 3C are schematic cross-sectional views of a method for manufacturing a semiconductor package substrate according to a second embodiment of the present invention.

图3A’为图3A的另一方式。Fig. 3A' is another mode of Fig. 3A.

图3C’及图3C”为图3C的其它实施例。Fig. 3C' and Fig. 3C" are other embodiments of Fig. 3C.

图3D为本发明的电子封装件的第二实施例的剖视示意图。3D is a schematic cross-sectional view of the second embodiment of the electronic package of the present invention.

图3D’为图3D的其它实施例。Fig. 3D' is another embodiment of Fig. 3D.

附图标记如下：The reference numbers are as follows:

1 电子装置1 Electronic device

1a 封装基板1a Package substrate

10 核心层10 core layers

11 线路增层部11 Line build-up section

11a,11b 接点11a, 11b contacts

12a,12b 防焊层12a, 12b Soldermask

13a 焊锡凸块13a Solder bumps

13b,13” 焊锡球13b, 13” solder balls

13’ 焊锡材料13' Solder Material

18 电路板18 circuit boards

19 半导体芯片19 Semiconductor chips

2,3 半导体封装基板2,3 Semiconductor packaging substrate

2a 线路结构2a Line structure

20 核心层20 core layer

20a 第一侧20a First side

20b 第二侧20b Second side

200 导电部200 Conductive part

21 增层部21 Build-up Department

210 介电层210 Dielectric layer

211 线路层211 Line layer

212 焊垫212 pads

22a,22b,32a,32b 防焊结构22a, 22b, 32a, 32b Solder mask structure

220 开孔220 opening

23,36,36’ 焊座23,36,36’ Solder Socket

32 绝缘层32 Insulation layer

320 第二开孔320 Second opening

33 金属支撑层33 Metal Support Layer

330 第一开孔330 first opening

34 结合材34 Bonding material

361’ 凸块底部361’ bump bottom

37 导接块37 Lead block

4,4’,4” 电子封装件4,4’,4” Electronic Package

40 电子元件40 Electronic Components

400 导电凸块400 conductive bumps

41 封装层41 Encapsulation layer

42 导电元件。42 Conductive elements.

具体实施方式Detailed ways

以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所公开的内容轻易地了解本发明的其他优点及技术效果。The embodiments of the present invention are described below by means of specific specific embodiments, and those skilled in the art can easily understand other advantages and technical effects of the present invention from the contents disclosed in this specification.

须知，本说明书附图所示出的结构、比例、大小等，均仅用以配合说明书所公开的内容，以本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的技术效果及所能实现的目的下，均应仍落在本发明所公开的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当视为本发明可实施的范畴。It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of this specification are only used to cooperate with the contents disclosed in the specification, and are not used to limit the conditions for the implementation of the present invention with the understanding and reading of those skilled in the art. Therefore, without technical substantive significance, any structural modification, proportional relationship change or size adjustment, without affecting the technical effect that the present invention can produce and the achievable purpose, should still fall within the scope of the disclosure of the present invention. The technical content must be able to cover the scope. At the same time, the terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and clarity, and are not used to limit the scope of the present invention. Changes or adjustments of their relative relationships, without substantial changes to the technical content, should be regarded as the scope of the present invention.

图2A至图2B为本发明的半导体封装基板2的第一实施例的制法的剖视示意图。2A to 2B are schematic cross-sectional views of the manufacturing method of thesemiconductor package substrate 2 according to the first embodiment of the present invention.

如图2A所示，提供一线路结构2a，该线路结构2a具有相对的第一侧20a与第二侧20b，两侧均可用于置放电子元件(如半导体芯片、无源元件等)，且将置放半导体芯片的外接侧称为置晶侧，故为了方便以下说明，将该第一侧20a作为置晶侧。As shown in FIG. 2A, acircuit structure 2a is provided, thecircuit structure 2a has oppositefirst sides 20a andsecond sides 20b, both sides can be used for placing electronic components (such as semiconductor chips, passive components, etc.), and The external side on which the semiconductor chip is placed is referred to as the die placement side, so for the convenience of the following description, thefirst side 20a is referred to as the die placement side.

于本实施例中，该线路结构2a具有一核心层20，其内形成有多个导电部200。例如，形成该核心层20的材质采用含玻纤及有机树脂的基材，如BT(Bismaleimide Triazine)、FR4或FR5等，亦或采用高刚性无玻纤但含有填充材(filler)(如SiO₂)的有机基材，再于其上进行导通孔工艺，如机械钻孔或激光钻孔等成孔步骤，并于孔中形成导电材。或者，于另一实施例中，形成该核心层20的材质为有机绝缘材，该有机绝缘材可为ABF(AjinomotoBuild-up Film)、有玻纤或无玻纤的预浸材(Prepreg)、铸模化合物(Molding Compound)，如环氧模压树脂(Epoxy Molding Compound，简称EMC)形成的核心基材，较佳者，采用高刚性及低热膨胀系数(CTE)的EMC，此时该导电部200可由单一导电柱体或由多个相互接触堆叠的导电柱体所组成。In this embodiment, thecircuit structure 2a has acore layer 20 in which a plurality ofconductive parts 200 are formed. For example, the material for forming thecore layer 20 is a base material containing glass fiber and organic resin, such as BT (Bismaleimide Triazine), FR4 or FR5, etc., or a high rigidity material without glass fiber but containing filler (such as SiO₂ ) the organic substrate, and then perform a via hole process on it, such as a hole forming step such as mechanical drilling or laser drilling, and form a conductive material in the hole. Or, in another embodiment, the material for forming thecore layer 20 is an organic insulating material, and the organic insulating material may be ABF (Ajinomoto Build-up Film), a prepreg with or without glass fiber, Molding compound (Molding Compound), such as the core substrate formed by epoxy molding compound (Epoxy Molding Compound, referred to as EMC), preferably, EMC with high rigidity and low coefficient of thermal expansion (CTE) is used, at this time, theconductive portion 200 can be made of A single conductive column or a plurality of conductive columns stacked in contact with each other.

此外，该线路结构2a还包括设于该核心层20上的增层部21，其具有至少一介电层210及多个结合该介电层210的线路层211。例如，该介电层210可为液状环氧树脂、膜状ABF、预浸材、模压树脂(EMC)或感光型树脂形成。应可理解地，有关该线路层211的布设层数可依需求设计。In addition, thecircuit structure 2 a further includes a build-upportion 21 disposed on thecore layer 20 , which has at least onedielectric layer 210 and a plurality of circuit layers 211 combined with thedielectric layer 210 . For example, thedielectric layer 210 may be formed of liquid epoxy resin, film ABF, prepreg, embossing resin (EMC) or photosensitive resin. It should be understood that the layout layers of thecircuit layer 211 can be designed according to requirements.

另外，于该线路结构2a的增层部21上可形成一具有多个开孔220的绝缘层，以作为防焊结构22a，防焊结构22b，并令该线路结构2a的最外层的线路层211外露于多个开孔220，以供作为焊垫212。具体地，形成该防焊结构22a，防焊结构22b的材质可为石墨烯、油墨、绿漆、ABF或非感光型介电材(如EMC)或其它适当材质，并无特别限制。In addition, an insulating layer with a plurality ofopenings 220 can be formed on the build-upportion 21 of thecircuit structure 2a to serve as thesolder mask structure 22a and thesolder mask structure 22b, and the outermost circuit of thecircuit structure 2a can be formed Thelayer 211 is exposed to the plurality ofopenings 220 for serving as thebonding pads 212 . Specifically, the material for forming the solder resiststructure 22a and the solder resiststructure 22b can be graphene, ink, green paint, ABF or non-photosensitive dielectric material (eg EMC) or other suitable materials, which are not particularly limited.

另外，于其它实施例中，该核心层20可改为硅基材，以令该增层部21设于该硅基材上，使该线路结构2a成为硅中介板(silicon interposer)形式。或者，于其它实施例中，该线路结构2a可为无核心层(coreless)形式。In addition, in other embodiments, thecore layer 20 can be changed to a silicon substrate, so that the build-upportion 21 is disposed on the silicon substrate, so that thecircuit structure 2a is in the form of a silicon interposer. Alternatively, in other embodiments, thecircuit structure 2a may be in a coreless form.

如图2B所示，形成焊座23于该线路结构2a的第二侧20b上的焊垫212与该防焊结构22b的开孔220的孔壁上。As shown in FIG. 2B ,solder pads 23 are formed on thesolder pads 212 on thesecond side 20b of thecircuit structure 2a and on the hole walls of theopenings 220 of thesolder mask structure 22b.

于本实施例中，形成该焊座23的材质与该焊垫212的材质为相同，如铜材。例如，以电镀方式形成于该线路层211外露的焊垫212表面上并延伸到该开孔220的孔壁上。In this embodiment, the material for forming thesoldering seat 23 is the same as the material for thesoldering pad 212 , such as copper material. For example, it is formed on the surface of the exposedpad 212 of thecircuit layer 211 by electroplating and extends to the hole wall of theopening 220 .

此外，于后续应用该半导体封装基板2时，如图2C所示的电子封装件4，可于该线路结构2a的第一侧20a的外露焊垫212上设置至少一电子元件40，并形成封装层41于该线路结构2a的第一侧20a上以结合该电子元件40，且于该线路结构2a的第二侧20b的焊座23上接置如焊锡球的导电元件42以结合至一电路板(图略)上。In addition, in the subsequent application of thesemiconductor package substrate 2, as shown in theelectronic package 4 shown in FIG. 2C, at least oneelectronic component 40 can be disposed on the exposedpad 212 of thefirst side 20a of thecircuit structure 2a to form a package Thelayer 41 is on thefirst side 20a of thecircuit structure 2a for bonding theelectronic component 40, and on thesolder pads 23 on thesecond side 20b of thecircuit structure 2aconductive elements 42 such as solder balls are attached for bonding to a circuit board (figure omitted).

所述的电子元件40为有源元件、无源元件或其二者组合，其中，该有源元件为例如半导体芯片，且该无源元件为例如电阻、电容及电感。例如，该电子元件40为半导体芯片，其借由多个含焊锡的导电凸块400以倒装芯片方式电性连接多个焊垫212。或者，该电子元件40也可借由多个焊线(图略)以打线方式电性连接该焊垫212。然而，有关该电子元件电性连接该半导体封装基板2的方式不限于上述，且该电子元件也可设于该线路结构2a的第二侧20b上或嵌埋于该增层部21中。Theelectronic element 40 is an active element, a passive element, or a combination of both, wherein the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor. For example, theelectronic component 40 is a semiconductor chip, which is electrically connected to the plurality ofbonding pads 212 in a flip-chip manner through a plurality ofconductive bumps 400 containing solder. Alternatively, theelectronic component 40 can also be electrically connected to thebonding pad 212 by a plurality of bonding wires (not shown) in a wire bonding manner. However, the manner in which the electronic component is electrically connected to thesemiconductor package substrate 2 is not limited to the above, and the electronic component may also be disposed on thesecond side 20b of thecircuit structure 2a or embedded in the build-upportion 21 .

所述的封装层41可为底胶，其形成于该线路结构2a的第一侧20a与该电子元件40之间以包覆多个导电凸块400。或者，该封装层41可为压合工艺用的薄膜、模压工艺用的封装胶体或印刷工艺用的胶材等以包覆该电子元件40与多个导电凸块400，且形成该封装层41的材质为聚酰亚胺(PI)、环氧树脂(epoxy)或模封的封装材。应可理解地，有关该电子元件40的封装方式并不限于上述。Theencapsulation layer 41 may be a primer, which is formed between thefirst side 20 a of thecircuit structure 2 a and theelectronic device 40 to encapsulate the plurality ofconductive bumps 400 . Alternatively, theencapsulation layer 41 may be a film for lamination process, an encapsulant for a molding process, or an adhesive for a printing process, etc. to encapsulate theelectronic element 40 and the plurality ofconductive bumps 400 and form theencapsulation layer 41 The material is polyimide (PI), epoxy resin (epoxy) or molded packaging material. It should be understood that the packaging method of theelectronic component 40 is not limited to the above.

所述的导电元件42形成于多个焊座23上。Theconductive elements 42 are formed on the plurality ofsolder pads 23 .

于本实施例中，该导电元件42包含焊锡材料，如焊锡球。In this embodiment, theconductive element 42 includes solder material, such as solder balls.

因此，本实施例的半导体封装基板2的制法于植球侧(该线路结构2a的第二侧20b)的焊垫212与防焊结构22b的开孔220的孔壁上镀覆一层材质与线路层211、焊垫212相同的铜材(即该焊座23)，以于后续封装植球作业中，该导电元件42(焊锡球)会接触该焊座23的底面与侧壁，因而增加该导电元件42与该焊座23间的金属接触面积，进而提升该导电元件42(焊锡球)与该焊座23间的结合力，故相较于公知技术，本发明的导电元件42不会于其与该焊座23的结合之处发生断裂，更能避免掉球或脱落的情况发生者。Therefore, in the manufacturing method of thesemiconductor package substrate 2 of the present embodiment, a layer of material is plated on thepads 212 on the ball-mounting side (thesecond side 20b of thecircuit structure 2a ) and the hole walls of theopenings 220 of thesolder mask structure 22b The same copper material as thecircuit layer 211 and the solder pads 212 (ie the solder pads 23 ) is used, so that the conductive element 42 (solder balls) will contact the bottom surface and sidewalls of thesolder pads 23 in the subsequent packaging and ball-mounting operations. The metal contact area between theconductive element 42 and thesoldering seat 23 is increased, thereby enhancing the bonding force between the conductive element 42 (solder ball) and thesoldering seat 23. Therefore, compared with the prior art, theconductive element 42 of the present invention does not It will be broken at the joint with thesolder seat 23, which can avoid the occurrence of ball dropping or falling off.

图3A至图3C为本发明的半导体封装基板3的第二实施例的制法的剖视示意图。本实施例与第一实施例的差异在于防焊结构，其它构造大致相同，故以下仅说明相异处。3A to 3C are schematic cross-sectional views of a method for manufacturing asemiconductor package substrate 3 according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment lies in the solder mask structure, and other structures are substantially the same, so only the differences will be described below.

如图3A所示，于该线路结构2a的第二侧20b上借由结合材34结合一金属支撑层33，且于该金属支撑层33上形成多个第一开孔330，并使多个第一开孔330延伸穿过该结合材34，以令多个焊垫212外露于多个第一开孔330。接着，形成一绝缘层32于该焊垫212、该金属支撑层33上及该第一开孔330中。As shown in FIG. 3A , ametal support layer 33 is bonded on thesecond side 20b of thecircuit structure 2a through abonding material 34, and a plurality offirst openings 330 are formed on themetal support layer 33, and a plurality of Thefirst openings 330 extend through thebonding material 34 so that thebonding pads 212 are exposed to thefirst openings 330 . Next, an insulatinglayer 32 is formed on thebonding pad 212 , themetal support layer 33 and thefirst opening 330 .

于本实施例中，该金属支撑层33为钢板、镍合金(alloy 42)片体等，且该结合材34为粘着胶材，而形成该绝缘层32的材质可为石墨烯、油墨、绿漆、ABF或非感光型介电材(如EMC)或其它适当材质，并无特别限制。In this embodiment, themetal supporting layer 33 is a steel plate, a nickel alloy (alloy 42) sheet, etc., and thebonding material 34 is an adhesive material, and the material forming the insulatinglayer 32 can be graphene, ink, green Paint, ABF or non-photosensitive dielectric material (such as EMC) or other suitable materials are not particularly limited.

此外，该绝缘层32沿该第一开孔330的侧壁布设。或者，该绝缘层32可填满该第一开孔330，如图3A’所示。In addition, the insulatinglayer 32 is arranged along the sidewall of thefirst opening 330 . Alternatively, the insulatinglayer 32 may fill thefirst opening 330, as shown in FIG. 3A'.

另外，该绝缘层32也形成于该线路结构2a的第一侧20a上。In addition, the insulatinglayer 32 is also formed on thefirst side 20a of thecircuit structure 2a.

如图3B所示，于该线路结构2a的第二侧20b上的绝缘层32上形成多个第二开孔320，以令多个焊垫212外露于多个第二开孔320，使该绝缘层32与该金属支撑层33作为防焊结构32a，且该绝缘层32包覆该金属支撑层33。As shown in FIG. 3B, a plurality ofsecond openings 320 are formed on the insulatinglayer 32 on thesecond side 20b of thecircuit structure 2a, so that thebonding pads 212 are exposed to thesecond openings 320, so that theThe insulating layer 32 and themetal support layer 33 serve as the solder resiststructure 32 a, and the insulatinglayer 32 covers themetal support layer 33 .

如图3C所示，形成焊座36于该线路结构2a的第二侧20b上的焊垫212与该防焊结构32b的第二开孔320的孔壁上，以利于增加其与该导电元件42的结合接触面积，进而有效提升二者的结合力。As shown in FIG. 3C , thesoldering pads 36 are formed on thesoldering pads 212 on thesecond side 20b of thecircuit structure 2a and the hole walls of thesecond openings 320 of the soldering resiststructure 32b, so as to facilitate the connection between thesoldering pads 212 and the conductive elements. 42 combined contact area, thereby effectively improving the binding force of the two.

于其它实施例中，也可依需求于该杯状焊座36上再形成一导接块37，且形成该导接块37的材质为例如锡或其它金属材。具体地，如图3C’所示，于该杯状焊座36上接置一体积小于该第二开孔320的焊锡球，借以形成为导接块37，据此即能有效缩小后续接置的导电元件42的尺寸(请参酌后续图3D所示)，以满足细间距封装的需求。In other embodiments, a conductingblock 37 can also be formed on the cup-shapedsolder seat 36 as required, and the material for forming the conductingblock 37 is, for example, tin or other metal materials. Specifically, as shown in FIG. 3C ′, a solder ball with a volume smaller than thesecond opening 320 is attached to the cup-shapedsoldering seat 36 to form aconductive block 37 , which can effectively reduce the subsequent connection The size of the conductive element 42 (please refer to the subsequent illustration in FIG. 3D ) is to meet the requirements of fine-pitch packaging.

于其它实施例中，也可依需求于该第二开孔320中的焊垫212上先电镀形成适当厚度(例如可为该第二开孔320的1/2深度)的凸块底部361’(请详图3C”所示)，然后再继续延伸电镀到第二开孔320的剩余孔壁上，进而形成具有凸块底部361’的杯状焊座36’(其材质与该线路层211、焊垫212相同，例如为铜)，据此可以有效缩小后续接置的导电元件42的尺寸(请参酌图3D’所示)，以满足细间距封装的需求，且能更进一步优化电性品质(借由电性品质佳的铜材料凸块底部361’替代部分的锡材料导电元件42)。In other embodiments, abump bottom 361 ′ with an appropriate thickness (for example, 1/2 of the depth of the second opening 320 ) can be formed by electroplating on thepads 212 in thesecond opening 320 as required. (Please refer to Fig. 3C" for details), and then continue to extend electroplating to the remaining hole walls of thesecond opening 320, thereby forming a cup-shaped solder pad 36' with a bump bottom 361' (the material of which is the same as that of the circuit layer 211). , the same as thesolder pad 212, such as copper), according to which the size of theconductive element 42 to be connected subsequently (please refer to FIG. 3D') can be effectively reduced to meet the requirements of fine-pitch packaging and further optimize the electrical properties Quality (part of theconductive elements 42 made of tin material are replaced bybump bottoms 361 ′ made of copper material with good electrical quality).

另外，于后续应用中，若采用图3C及图3C’所示的半导体封装基板3时，将形成如图3D所示的电子封装件4’。具体地，于该线路结构2a的第一侧20a的外露焊垫212上设置该电子元件40，并形成该封装层41于该第一侧20a上以结合该电子元件40，且于该半导体封装基板3的第二侧20b的具有导接块37的焊座36上接置多个导电元件42。In addition, in subsequent applications, if thesemiconductor package substrate 3 shown in FIG. 3C and FIG. 3C' is used, the electronic package 4' shown in FIG. 3D will be formed. Specifically, theelectronic component 40 is disposed on the exposedpad 212 of thefirst side 20a of thecircuit structure 2a, and theencapsulation layer 41 is formed on thefirst side 20a to bond theelectronic component 40, and theelectronic component 40 is formed on the semiconductor package. A plurality ofconductive elements 42 are mounted on thesolder pads 36 with theconductive blocks 37 on thesecond side 20b of thesubstrate 3 .

另一方面，若采用图3C”所示的半导体封装基板3时，将形成如图3D’所示的电子封装件4”，其中，于该具有凸块底部361’的焊座36’上接置多个导电元件42。On the other hand, if thesemiconductor package substrate 3 shown in FIG. 3C ″ is used, theelectronic package 4 ″ shown in FIG. 3D ′ will be formed, wherein thesolder pads 36 ′ with thebump bottoms 361 ′ are connected A plurality ofconductive elements 42 are arranged.

因此，本实施例的半导体封装基板3的制法于植球侧(该线路结构2a的第二侧20b)的该焊垫212与该防焊结构32b的第二开孔320的孔壁上镀覆一层铜材(即形成为该杯状焊座36，焊座36’)，以于后续封装植球作业中令该导电元件42(焊锡球)接触该焊座36，焊座36’的底面与侧壁，因而增加金属接触面积，进而提升该导电元件42(焊锡球)与该焊座36，焊座36’间的结合力。故相较于公知技术，本发明的导电元件42与焊座36，焊座36’间的结合力更加强固，促使该导电元件42不会于其与焊座36，焊座36’的结合之处发生断裂，还能避免发生掉球或脱落的情况。Therefore, in the manufacturing method of thesemiconductor package substrate 3 of the present embodiment, thebonding pad 212 on the ball-mounting side (thesecond side 20b of thecircuit structure 2a) and the hole wall of thesecond opening 320 of thesolder mask structure 32b are plated Coating a layer of copper material (that is, forming the cup-shapedsolder seat 36, the solder seat 36'), so that the conductive element 42 (solder ball) contacts thesolder seat 36, the solder seat 36' in the subsequent packaging and ball-mounting operations. The bottom surface and the side wall thus increase the metal contact area, thereby enhancing the bonding force between the conductive element 42 (solder ball) and thesolder seat 36 and thesolder seat 36 ′. Therefore, compared with the prior art, the bonding force between theconductive element 42 and thesoldering seat 36 and the soldering seat 36' of the present invention is stronger, so that theconductive element 42 will not be in the bonding with thesoldering seat 36 and the soldering seat 36'. It can also prevent the ball from falling off or falling off.

此外，借由将该金属支撑层33设于该线路结构2a的第二侧20b上，以增加该半导体封装基板3的刚性强度，故相较于公知技术，当该半导体封装基板3用于大封装尺寸时，即使薄化该半导体封装基板3，该半导体封装基板3仍具有高的刚性，因而于后续封装高温工艺时或于产品使用时，能避免该电子封装件4’，电子封装件4”发生弯翘，进而能避免其与电子元件40或电路板之间发生连接不良的问题。In addition, by disposing themetal support layer 33 on thesecond side 20b of thecircuit structure 2a to increase the rigidity of thesemiconductor packaging substrate 3, compared with the prior art, when thesemiconductor packaging substrate 3 is used for large In the package size, even if thesemiconductor package substrate 3 is thinned, thesemiconductor package substrate 3 still has high rigidity, so theelectronic package 4 ′, theelectronic package 4 can be avoided in the subsequent high temperature process of packaging or when the product is used. ” warping occurs, thereby avoiding the problem of poor connection between it and theelectronic component 40 or the circuit board.

另外，由于该半导体封装基板3用于大封装尺寸时，该线路结构2a的增层部21的层数可依需求设计，故该线路结构2a可能产生各种程度的翘曲变化，因而可借由调整该金属支撑层33的厚度或该金属支撑层33的构成材质，即可控制该半导体封装基板3的刚性。故而无需增加该核心层20的厚度，甚至可降低该核心层20的厚度或无需配置该核心层20，即能避免该半导体封装基板3弯翘的问题。In addition, when thesemiconductor package substrate 3 is used for a large package size, the number of layers of the build-upportion 21 of thecircuit structure 2a can be designed according to requirements, so thecircuit structure 2a may have various degrees of warpage change, so it can be The rigidity of thesemiconductor package substrate 3 can be controlled by adjusting the thickness of themetal support layer 33 or the constituent material of themetal support layer 33 . Therefore, there is no need to increase the thickness of thecore layer 20 , or even reduce the thickness of thecore layer 20 or configure thecore layer 20 , which can avoid the warping problem of thesemiconductor package substrate 3 .

另外，借由该具有凸块底部361’(其材质与线路层211、焊垫212相同，例如为铜)的杯状焊座36’的设计，能有效缩减导电元件42的尺寸与用料，借以满足细间距封装需求，且进而能优化该半导体封装基板3的电性品质(借由电性品质佳的铜材料凸块底部361’替代部分的锡材料导电元件42)。In addition, by virtue of the design of the cup-shapedsolder pad 36 ′ having thebump bottom 361 ′ (the material of which is the same as that of thecircuit layer 211 and thesolder pad 212 , such as copper), the size and material of theconductive element 42 can be effectively reduced. In order to meet the requirements of fine-pitch packaging, and further optimize the electrical quality of the semiconductor package substrate 3 (replacing part of the tin materialconductive elements 42 by the coppermaterial bump bottoms 361 ′ with good electrical quality).

综上所述，本发明的半导体封装基板及借此封装完成的电子封装件，利用该焊座23，焊座36，焊座36’的设计，以增加该导电元件42与金属接触的面积，进而提升该导电元件42(焊锡球)与该焊座23，焊座36，焊座36’间的结合力，故本发明能有效避免该导电元件42于其与焊座23，焊座36，焊座36’的结合之处发生断裂，还能避免发生掉球或脱落的情况。To sum up, the semiconductor package substrate of the present invention and the electronic package packaged therewith utilize the design of thesolder pads 23 , thesolder pads 36 , and thesolder pads 36 ′ to increase the contact area between theconductive element 42 and the metal. Furthermore, the bonding force between the conductive element 42 (solder ball) and thesoldering seat 23, thesoldering seat 36, and the soldering seat 36' is improved, so the present invention can effectively prevent theconductive element 42 from being in contact with thesoldering seat 23, thesoldering seat 36, and the soldering seat 36'. The bonding of the solder pads 36' is fractured, and it is also possible to avoid the occurrence of dropped balls or falling off.

上述实施例仅用以例示性说明本发明的原理及其技术效果，而非用于限制本发明。本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。The above embodiments are only used to illustrate the principles and technical effects of the present invention, but not to limit the present invention. Those skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as listed in the claims.

Claims (18)

1. A semiconductor package substrate, comprising:

a line structure having a line layer;

the welding-proof structure is arranged on the circuit structure and is provided with an opening so that the circuit layer is partially exposed out of the opening; and

and the welding seat is of a cup-shaped structure, is formed by electroplating and extends to the hole wall of the opening from the exposed surface of the circuit layer, wherein the material for forming the welding seat is the same as the material for forming the circuit layer.

2. The semiconductor package substrate of claim 1, wherein the solder mask structure is a single insulating layer.

3. The semiconductor package substrate of claim 1, wherein the solder mask structure further comprises a metal support layer and an insulating layer covering the metal support layer, the metal support layer being bonded to the circuit structure with a bonding material.

4. The semiconductor package substrate of claim 1, further comprising a conductive element disposed on the solder pad, wherein the conductive element is a solder ball.

5. The semiconductor package substrate of claim 1, further comprising a solder bump disposed on the solder socket, wherein the solder bump is a solder ball having a volume smaller than the opening.

6. The substrate of claim 1, wherein the contact portion of the pad and the circuit layer is formed with a bottom bump having a suitable thickness, and the suitable thickness is not greater than or greater than the depth 1/2 of the opening.

7. An electronic package, comprising:

the semiconductor package substrate according to one of claims 1 to 6, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit layer is disposed on the first side and the second side, such that the solder mask structure is disposed on the second side of the circuit structure; and

and the electronic element is arranged on the first side of the circuit structure and is electrically connected with the circuit layer on the first side of the circuit structure.

8. The electronic package according to claim 7, further comprising a packaging layer disposed on the semiconductor package substrate for bonding the electronic component and the semiconductor package substrate.

9. The electronic package of claim 7, wherein the electronic component is disposed on the first side of the circuit structure with a plurality of conductive bumps.

10. A method for manufacturing a semiconductor package substrate, the method comprising:

providing a circuit structure with a circuit layer;

forming a solder mask structure on the circuit structure, wherein the solder mask structure has an opening to expose the circuit layer out of the opening; and

and forming a welding seat in the opening, wherein the welding seat is of a cup-shaped structure, is formed by electroplating and extends to the hole wall of the opening from the exposed surface of the circuit layer, and the material for forming the welding seat is the same as the material for forming the circuit layer.

11. The method of claim 10, wherein the solder mask structure is a single insulating layer.

12. The method of claim 10, wherein the solder mask structure further comprises a metal supporting layer and an insulating layer covering the metal supporting layer, and the metal supporting layer is bonded to the circuit structure by a bonding material.

13. The method of claim 10, further comprising forming conductive elements on the solder pad, wherein the conductive elements are solder balls.

14. The method of claim 10, further comprising forming a solder bump on the pad, wherein the solder bump is a solder ball having a volume smaller than the opening.

15. The method of claim 10, wherein the contact portion of the solder pad and the circuit layer is electroplated with a bump bottom having a suitable thickness, and the suitable thickness is not greater than or greater than the 1/2 depth of the opening.

16. A method of fabricating an electronic package, the method comprising:

providing a semiconductor package substrate according to one of claims 1 to 6, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit layer is disposed on the first side and the second side, and the solder mask structure is disposed on the second side of the circuit structure; and

an electronic element is arranged on the first side of the circuit structure and electrically connected with the circuit layer on the first side of the circuit structure.

17. The method of claim 16, further comprising forming an encapsulation layer on the semiconductor package substrate to bond the electronic component and the semiconductor package substrate.

18. The method of claim 16, wherein the electronic component is disposed on the first side of the circuit structure with a plurality of conductive bumps.

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