CN111696465A - Driving circuit of display panel - Google Patents

Abstract

A driving circuit of a display panel, comprising: the circuit comprises a first output buffer, a second output buffer and a first current source. The first current source is used for providing a first bias current to the first output buffer, and the first current source is an adjustable current source. In the calibration state, the driving circuit is used for adjusting the first bias current output by the first current source so that the conversion rate of the first output buffer and the conversion rate of the second output buffer are different from each other. Thus, the adjuster can try to adjust the noise.

Description

Translated fromChinese

显示面板的驱动电路Display panel driver circuit

技术领域technical field

本发明涉及一种电子电路；具体而言，本发明涉及一种显示装置的驱动电路。The present invention relates to an electronic circuit; in particular, the present invention relates to a driving circuit of a display device.

背景技术Background technique

随着电子科技的快速发展，显示装置已被广泛地应用在人们的生活当中，诸如行动电话或电脑等。With the rapid development of electronic technology, display devices have been widely used in people's lives, such as mobile phones or computers.

一般而言，显示装置包括源极驱动电路，用以提供数据电压至显示面板中的像素矩阵。然而，源极驱动电路所提供的数据电压可能与显示装置之中或之外的其它电子元件彼此干扰，而造成负面影响。因此，一种解决方案当被提出。Generally speaking, a display device includes a source driving circuit for providing data voltages to a pixel matrix in a display panel. However, the data voltage provided by the source driving circuit may interfere with other electronic components in or outside the display device, thereby causing adverse effects. Therefore, a solution should be proposed.

发明内容SUMMARY OF THE INVENTION

本发明一实施方式涉及一种驱动电路。根据本发明一实施例，驱动电路包括：第一输出缓冲器、第二输出缓冲器、以及第一电流源。第一电流源，用以提供第一偏压电流至第一输出缓冲器，且第一电流源为可调电流源。其中，在调校状态下，驱动电路用以调整第一电流源输出的第一偏压电流，以使第一输出缓冲器的转换率与第二输出缓冲器的转换率彼此不同。An embodiment of the present invention relates to a driving circuit. According to an embodiment of the present invention, the driving circuit includes: a first output buffer, a second output buffer, and a first current source. The first current source is used for providing the first bias current to the first output buffer, and the first current source is an adjustable current source. Wherein, in the adjustment state, the driving circuit is used to adjust the first bias current output by the first current source, so that the slew rate of the first output buffer and the slew rate of the second output buffer are different from each other.

于一实施例中，该驱动电路还包括：一第二电流源，用以提供一第二偏压电流至该第二输出缓冲器，其中该第二偏压电流源为一可调电流源；且其中在该调校状态下，该驱动电路还用以调整该第二电流源输出的该第二偏压电流，以使该第一输出缓冲器的转换率与该第二输出缓冲器的转换率彼此不同。In one embodiment, the driving circuit further includes: a second current source for providing a second bias current to the second output buffer, wherein the second bias current source is an adjustable current source; And wherein in the adjustment state, the driving circuit is also used to adjust the second bias current output by the second current source, so as to make the conversion ratio of the first output buffer and the conversion of the second output buffer rates are different from each other.

于一实施例中，该驱动电路还包括：一第二电流源，用以提供一第二偏压电流至该第二输出缓冲器，其中该第二偏压电流源为一固定电流源。In one embodiment, the driving circuit further includes: a second current source for providing a second bias current to the second output buffer, wherein the second bias current source is a fixed current source.

本发明一实施方式涉及一种驱动电路。根据本发明一实施例，驱动电路包括：第一输出缓冲器。第一输出缓冲器包括：输出级。输出级包括：第一开关电路与第二开关电路。第一开关电路，电性连接于一输出锁存器与一第一供应电源之间。第二开关电路，电性连接于该输出锁存器与一第二供应电源之间。其中该第一开关电路的开关宽度是可调整的。An embodiment of the present invention relates to a driving circuit. According to an embodiment of the present invention, the driving circuit includes: a first output buffer. The first output buffer includes: an output stage. The output stage includes: a first switch circuit and a second switch circuit. The first switch circuit is electrically connected between an output latch and a first power supply. The second switch circuit is electrically connected between the output latch and a second power supply. The switch width of the first switch circuit is adjustable.

于一实施例中，该第二开关电路的开关宽度是可调整的。In one embodiment, the switch width of the second switch circuit is adjustable.

于一实施例中，在一调校状态下，该驱动电路通过调整该第一开关电路的开关宽度，以使该第一输出缓冲器的一输出电压的一上升变化率不同于一下降变化率。In one embodiment, in an adjustment state, the driving circuit adjusts the switching width of the first switching circuit so that a rising rate of change of an output voltage of the first output buffer is different from a falling rate of change .

于一实施例中，该第一开关电路包括：多个工作开关，该些工作开关的多个第一端彼此电性连接；及多个控制开关，该些控制开关的多个第一端分别电性连接该些工作开关的多个第二端，且该些控制开关的多个第二端彼此电性连接；其中该些控制开关分别根据多个控制信号选择性导通及关断，以调整该第一开关电路的开关宽度。In one embodiment, the first switch circuit includes: a plurality of working switches, a plurality of first ends of the working switches are electrically connected to each other; and a plurality of control switches, the first ends of the control switches are respectively A plurality of second ends of the working switches are electrically connected, and a plurality of second ends of the control switches are electrically connected to each other; wherein the control switches are selectively turned on and off according to a plurality of control signals, so as to The switch width of the first switch circuit is adjusted.

本发明一实施方式涉及一种驱动电路。根据本发明一实施例，驱动电路包括：输出缓冲器。输出缓冲器包括：输出级。输出级包括：第一开关电路，且第一开关电路的开关宽度是可调整的。在调校状态下，驱动电路通过调整开关电路的开关宽度，以使输出缓冲器的输出电压的上升变化率不同于下降变化率。An embodiment of the present invention relates to a driving circuit. According to an embodiment of the present invention, the driving circuit includes: an output buffer. The output buffer includes: an output stage. The output stage includes: a first switch circuit, and the switch width of the first switch circuit is adjustable. In the adjustment state, the driving circuit adjusts the switching width of the switching circuit so that the rising change rate of the output voltage of the output buffer is different from the falling change rate.

于一实施例中，该输出级还包括：一第二开关电路，其中该第二开关电路的开关宽度是可调整的。In one embodiment, the output stage further includes: a second switch circuit, wherein the switch width of the second switch circuit is adjustable.

于一实施例中，该第一开关电路包括：多个工作开关，该些工作开关的多个第一端彼此电性连接；及多个控制开关，该些控制开关的多个第一端分别电性连接该些工作开关的多个第二端，且该些控制开关的多个第二端彼此电性连接；其中该些控制开关分别根据多个控制信号选择性导通及关断，以调整该第一开关电路的开关宽度。In one embodiment, the first switch circuit includes: a plurality of working switches, a plurality of first ends of the working switches are electrically connected to each other; and a plurality of control switches, the first ends of the control switches are respectively A plurality of second ends of the working switches are electrically connected, and a plurality of second ends of the control switches are electrically connected to each other; wherein the control switches are selectively turned on and off according to a plurality of control signals, so as to The switch width of the first switch circuit is adjusted.

通过应用本案一实施例，在调校状态下可使第一输出缓冲器的转换率与第二输出缓冲器的转换率彼此不同。通过调校第一输出缓冲器与第二输出缓冲器的转换率，调校人员即可设法对噪声进行调整。By applying an embodiment of the present invention, the slew rate of the first output buffer and the slew rate of the second output buffer can be made different from each other in the tuning state. By adjusting the slew rate of the first output buffer and the second output buffer, the tuner can try to adjust the noise.

附图说明Description of drawings

图1为根据本发明一实施例所绘示的显示装置的示意图；FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention;

图2为根据本发明一实施例所绘示的驱动电路的示意图；FIG. 2 is a schematic diagram of a driving circuit according to an embodiment of the present invention;

图3为根据本发明一实施例所绘示的驱动电路的输出缓冲器的示意图；3 is a schematic diagram of an output buffer of a driving circuit according to an embodiment of the present invention;

图4为根据本发明一实施例所绘示的开关电路的示意图；4 is a schematic diagram of a switch circuit according to an embodiment of the present invention;

图5为根据本发明一操作例所绘示的信号图；FIG. 5 is a signal diagram according to an operation example of the present invention;

图6为根据本发明另一实施例所绘示的驱动电路的示意图；6 is a schematic diagram of a driving circuit according to another embodiment of the present invention;

图7为根据本发明另一实施例所绘示的驱动电路的示意图；7 is a schematic diagram of a driving circuit according to another embodiment of the present invention;

图8为根据本发明另一实施例所绘示的驱动电路的示意图；8 is a schematic diagram of a driving circuit according to another embodiment of the present invention;

图9为根据本发明另一操作例所绘示的信号图；FIG. 9 is a signal diagram according to another operation example of the present invention;

图10为根据本发明另一实施例所绘示的驱动电路的示意图；10 is a schematic diagram of a driving circuit according to another embodiment of the present invention;

图11为根据本发明另一实施例所绘示的驱动电路的示意图。FIG. 11 is a schematic diagram of a driving circuit according to another embodiment of the present invention.

主要元件符号说明：Description of main component symbols:

10：输入级10: Input stage

20：增益级20: Gain Stage

30：输出级30: Output stage

100：显示面板100: Display panel

101：像素阵列101: Pixel array

110：栅极驱动电路110: Gate drive circuit

120：源极驱动电路120: Source drive circuit

121：电源晶片121: Power chip

122：时序控制晶片122: Timing control chip

123：触控晶片123: Touch Chip

200、250：输出缓冲器200, 250: output buffer

200a、250a：输出缓冲器200a, 250a: output buffer

201、202、203、204：开关电路201, 202, 203, 204: Switching Circuits

CTL1、CTL2、CTL3、CTL4：控制开关CTL1, CTL2, CTL3, CTL4: Control switches

D(1)-D(M)：数据电压D(1)-D(M): Data voltage

G(1)-G(N)：扫描信号G(1)-G(N): scan signal

GND：接地端GND: ground terminal

I1、I2：偏压电流I1, I2: bias current

OS1、OS2：输出开关OS1, OS2: Output switch

OB1、OB2：前级电路OB1, OB2: front-end circuit

VDD1、VDD2：供应电压VDD1, VDD2: Supply voltage

VIN1、VIN2：输入端VIN1, VIN2: input terminal

M01、M02、M03、M04：工作开关M01, M02, M03, M04: work switch

IS1、IS2：电流源IS1, IS2: current source

ADS1、ADS2：调整信号ADS1, ADS2: adjust the signal

SC1、SC2：波形SC1, SC2: waveform

t1-t2：时间t1-t2: time

具体实施方式Detailed ways

以下将以附图及详细叙述清楚说明本公开内容的精神，任何本领域技术人员在了解本公开内容的实施例后，当可由本公开内容所教示的技术，加以改变及修饰，其并不脱离本公开内容的精神与范围。The following will clearly illustrate the spirit of the present disclosure with the accompanying drawings and detailed descriptions. After understanding the embodiments of the present disclosure, any person skilled in the art can make changes and modifications by the techniques taught in the present disclosure without departing from it. spirit and scope of the present disclosure.

关于本文中所使用的“第一”、“第二”、…等，并非特别指称次序或顺位的意思，也非用以限定本发明，其仅为了区别以相同技术用语描述的元件或操作。Regarding the "first", "second", ... etc. used in this document, it does not specifically refer to the order or order, nor is it used to limit the present invention, it is only used to distinguish elements or operations described in the same technical terms. .

关于本文中所使用的“电性连接”，可指二或多个元件相互直接作实体或电性接触，或是相互间接作实体或电性接触，而“电性连接”还可指二或多个元件相互操作或动作。As used herein, "electrically connected" may refer to two or more elements in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "electrically connected" may also refer to two or more elements. Multiple elements operate or act upon each other.

关于本文中所使用的“包含”、“包括”、“具有”、“含有”等等，均为开放性的用语，即意指包含但不限于。As used herein, "comprising," "including," "having," "containing," and the like, are open-ended terms, meaning including but not limited to.

关于本文中所使用的“及/或”，包括所述事物的任一或全部组合。As used herein, "and/or" includes any and all combinations of the stated things.

关于本文中所使用的用语“大致”、“约”等，用以修饰任何可些微变化的数量或误差，但这种些微变化或误差并不会改变其本质。As used herein, the terms "approximately", "about" and the like are used to modify any quantity or error that may vary slightly, but which does not alter its essence.

关于本文中所使用的术语(terms)，除有特别注明外，通常具有每个术语使用在此领域中、在此公开的内容中与特殊内容中的平常意义。某些用以描述本公开的术语将于下或在此说明书的别处讨论，以提供本领域技术人员在有关本公开的描述上额外的引导。With respect to the terms used herein, unless otherwise noted, each term generally has its ordinary meaning as it is used in the art, in the context of this disclosure, and in particular contexts. Certain terms used to describe the present disclosure are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in the description of the present disclosure.

图1为根据本发明实施例所绘示的显示装置100的示意图。显示装置100可包括栅极驱动电路110、源极驱动电路120、电源晶片121、时序控制晶片(timing control IC)122、触控晶片123、以及像素阵列101。电源晶片121用以提供显示装置100电源，时序控制晶片122用以控制显示装置100的时序，触控晶片123用以通过感测触控电极上的电性变化，以进行触控感测。栅极驱动电路110可依序产生并提供多笔扫描信号G(1)、…、G(N)给像素阵列101，以开启像素阵列101中的多个开关，其中N为自然数。源极驱动电路120可产生多笔数据电压D(1)、…、D(M)，并提供此些数据电压D(1)、…、D(M)给像素阵列101，以使像素阵列101根据数据电压D(1)、…、D(M)进行显示操作，其中M为自然数。由此，显示装置100即可显示影像并进行触碰感测。FIG. 1 is a schematic diagram of adisplay device 100 according to an embodiment of the present invention. Thedisplay device 100 may include agate driving circuit 110 , asource driving circuit 120 , apower chip 121 , atiming control IC 122 , atouch chip 123 , and apixel array 101 . Thepower chip 121 is used to provide power to thedisplay device 100 , thetiming control chip 122 is used to control the timing of thedisplay device 100 , and thetouch chip 123 is used for touch sensing by sensing electrical changes on the touch electrodes. Thegate driving circuit 110 can sequentially generate and provide multiple scan signals G(1), . . . , G(N) to thepixel array 101 to turn on multiple switches in thepixel array 101, wherein N is a natural number. Thesource driving circuit 120 can generate a plurality of data voltages D(1), . . . , D(M), and provide these data voltages D(1), . The display operation is performed according to the data voltages D(1), . . . , D(M), where M is a natural number. Thus, thedisplay device 100 can display images and perform touch sensing.

应注意到，在不同实施例中，电源晶片121可用晶片以外的电源模块实现，时序控制晶片122可用晶片以外的时序控制模块实现、且触控晶片123可用晶片以外的触控模块实现。另一方面，虽然本案以触控功能的显示装置100为例进行说明，然而在不同实施例中，显示装置100也可不具触控功能，且触控晶片123及触控电极可相应地省略。It should be noted that, in different embodiments, thepower chip 121 can be implemented by an off-chip power module, thetiming control chip 122 can be implemented by an off-chip timing control module, and thetouch chip 123 can be implemented by an off-chip touch module. On the other hand, although the present application takes thedisplay device 100 with touch function as an example, in different embodiments, thedisplay device 100 may not have the touch function, and thetouch chip 123 and the touch electrodes may be omitted accordingly.

参照图2与图3，图2与图3为根据本发明实施例所绘示的源极驱动电路120(以下简称驱动电路120)的示意图。应注意到，此处虽仅以源极驱动电路120中相应于数据电压D(1)、…、D(M)中的两数据电压(例如数据电压D(1)、D(2))的电路为例进行说明，然源极驱动电路120当可包括相应于数据电压D(1)、…、D(M)中的其它数据电压的电路，故本案并不以图2与图3中所绘示的电路为限。Referring to FIGS. 2 and 3 , FIGS. 2 and 3 are schematic diagrams of a source driving circuit 120 (hereinafter referred to as a driving circuit 120 ) according to an embodiment of the present invention. It should be noted that although only two data voltages (eg, data voltages D(1), D(2)) in thesource driving circuit 120 corresponding to the data voltages D(1), . . . , D(M) are used here The circuit is taken as an example for description. However, thesource driving circuit 120 may include circuits corresponding to other data voltages in the data voltages D(1), . . . , D(M). The circuit shown is limited.

在一实施例中，驱动电路120包括输出缓冲器200、输出开关OS1、输出缓冲器250、及输出开关OS2。在一实施例中，输出缓冲器200的输出端电性连接于输出开关OS1，且输出缓冲器250的输出端电性连接输出开关OS2。在一实施例中，输出缓冲器200、250彼此相邻设置。在一实施例中，输出缓冲器200、250用以输出数据电压(如分别用以输出数据电压D(1)、D(2))。在一实施例中，输出开关OS1、OS2用以相应于锁存信号(latchsignal)(未示出)将数据电压提供至像素阵列101。In one embodiment, the drivingcircuit 120 includes anoutput buffer 200, an output switch OS1, anoutput buffer 250, and an output switch OS2. In one embodiment, the output terminal of theoutput buffer 200 is electrically connected to the output switch OS1, and the output terminal of theoutput buffer 250 is electrically connected to the output switch OS2. In one embodiment, the output buffers 200, 250 are arranged adjacent to each other. In one embodiment, the output buffers 200 and 250 are used for outputting data voltages (eg, for outputting data voltages D(1) and D(2), respectively). In one embodiment, the output switches OS1 and OS2 are used to provide data voltages to thepixel array 101 corresponding to latch signals (not shown).

在一实施例中，输出缓冲器200包括前级电路OB1以及输出级30(参照图3)。在一实施例中，前级电路OB1包括输入级10以及增益级20。输出级30包括开关电路201以及开关电路202。在一实施例中，开关电路201、202可为由一或多个晶体管所组成的电路。In one embodiment, theoutput buffer 200 includes a pre-stage circuit OB1 and an output stage 30 (refer to FIG. 3 ). In one embodiment, the pre-stage circuit OB1 includes an input stage 10 and again stage 20 . Theoutput stage 30 includes aswitch circuit 201 and aswitch circuit 202 . In one embodiment, theswitch circuits 201 and 202 may be circuits composed of one or more transistors.

在一实施例中，前级电路OB1的输入级10电性连接于输入端VIN1与增益级20之间。增益级20的正极性输出端电性连接于输出级30的开关电路201的控制端。增益级20的负极性输出端电性连接于输出级30的开关电路202的控制端。开关电路201的一端用以接收供应电压VDD1，开关电路201的另一端电性连接于输出开关OS1。开关电路202的一端电性连接于输出开关OS1，开关电路202的另一端电性连接至接地端GND。In one embodiment, the input stage 10 of the pre-stage circuit OB1 is electrically connected between the input terminal VIN1 and thegain stage 20 . The positive output terminal of thegain stage 20 is electrically connected to the control terminal of theswitch circuit 201 of theoutput stage 30 . The negative output terminal of thegain stage 20 is electrically connected to the control terminal of theswitch circuit 202 of theoutput stage 30 . One end of theswitch circuit 201 is used for receiving the supply voltage VDD1, and the other end of theswitch circuit 201 is electrically connected to the output switch OS1. One end of theswitch circuit 202 is electrically connected to the output switch OS1, and the other end of theswitch circuit 202 is electrically connected to the ground terminal GND.

类似地，在本实施例中，输出缓冲器250包括前级电路OB2以及输出级，其中输出级包括开关电路203、开关电路204。关于前级电路OB2的结构大致相同于前述前级电路OB1的结构，故在此不赘述。在一实施例中，开关电路201、202可为由一或多个晶体管所组成的电路。Similarly, in this embodiment, theoutput buffer 250 includes a front-end circuit OB2 and an output stage, wherein the output stage includes aswitch circuit 203 and aswitch circuit 204 . The structure of the pre-stage circuit OB2 is substantially the same as the structure of the previous-stage circuit OB1, so it is not repeated here. In one embodiment, theswitch circuits 201 and 202 may be circuits composed of one or more transistors.

在一实施例中，前级电路OB2的输入端电性连接于输入端VIN2，前级电路OB2的正极性输出端电性连接于输出级30的开关电路203的控制端，且前级电路OB2的负极性输出端电性连接于输出级30的开关电路204的控制端。开关电路203的一端用以接收供应电压VDD2，开关电路203的另一端电性连接于输出开关OS2。开关电路204的一端电性连接于输出开关OS2，开关电路204的另一端电性连接至接地端GND。在一实施例中，供应电压VDD2可相同或不同于供应电压VDD1。In one embodiment, the input terminal of the pre-stage circuit OB2 is electrically connected to the input terminal VIN2, the positive output terminal of the pre-stage circuit OB2 is electrically connected to the control terminal of theswitch circuit 203 of theoutput stage 30, and the pre-stage circuit OB2 is electrically connected to the control terminal of theswitch circuit 203 of theoutput stage 30. The negative output terminal of theoutput stage 30 is electrically connected to the control terminal of theswitch circuit 204 of theoutput stage 30 . One end of theswitch circuit 203 is used for receiving the supply voltage VDD2, and the other end of theswitch circuit 203 is electrically connected to the output switch OS2. One end of theswitch circuit 204 is electrically connected to the output switch OS2, and the other end of theswitch circuit 204 is electrically connected to the ground terminal GND. In one embodiment, the supply voltage VDD2 may be the same or different from the supply voltage VDD1.

在一实施例中，开关电路201的开关宽度是可调整的。举例而言，参照图4，图4为根据本案一实施例所绘示的开关电路201的示意图。在本实施例中，开关电路201包括工作开关M01、工作开关M02、工作开关M03、工作开关M04、控制开关CTL1、控制开关CTL2、控制开关CTL3、控制开关CTL4。在一实施例中，工作开关M01的一端、工作开关M02的一端、工作开关M03的一端、工作开关M04的一端彼此电性连接。在一实施例中，工作开关M01的另一端、工作开关M02的另一端、工作开关M03的另一端、及工作开关M04的另一端分别电性连接于控制开关CTL1的一端、控制开关CTL2的一端、控制开关CTL3的一端、及控制开关CTL4。在一实施例中，控制开关CTL1的另一端、控制开关CTL2的另一端、控制开关CTL3的另一端、控制开关CTL4的另一端为彼此电性连接。在一实施例中，工作开关M01的控制端、工作开关M02的控制端、工作开关M03的控制端、工作开关M04的控制端彼此电性连接于增益级20的正极性输出端。In one embodiment, the switch width of theswitch circuit 201 is adjustable. For example, referring to FIG. 4 , FIG. 4 is a schematic diagram of theswitch circuit 201 according to an embodiment of the present invention. In this embodiment, theswitch circuit 201 includes a work switch M01, a work switch M02, a work switch M03, a work switch M04, a control switch CTL1, a control switch CTL2, a control switch CTL3, and a control switch CTL4. In one embodiment, one end of the work switch M01, one end of the work switch M02, one end of the work switch M03, and one end of the work switch M04 are electrically connected to each other. In one embodiment, the other end of the work switch M01, the other end of the work switch M02, the other end of the work switch M03, and the other end of the work switch M04 are respectively electrically connected to one end of the control switch CTL1 and one end of the control switch CTL2. , one end of the control switch CTL3, and the control switch CTL4. In one embodiment, the other end of the control switch CTL1, the other end of the control switch CTL2, the other end of the control switch CTL3, and the other end of the control switch CTL4 are electrically connected to each other. In one embodiment, the control terminal of the work switch M01 , the control terminal of the work switch M02 , the control terminal of the work switch M03 , and the control terminal of the work switch M04 are electrically connected to the positive output terminal of thegain stage 20 .

在一实施例中，控制开关CTL1-CTL4可分别根据多个控制信号选择性导通或关断。举例而言，在一操作状态下，当控制开关CTL1导通、控制开关CTL2-CTL4关断时，相应于增益级20的正极性输出端的输出信号，具有电流量I的电流可经由开关电路201提供至输出级30的输出端。在另一操作状态下，当控制开关CTL1-CTL2导通、控制开关CTL3-CTL4关断时，相应于增益级20的正极性输出端的输出信号，具有电流量2I的电流可经由开关电路201提供至输出级30的输出端。In one embodiment, the control switches CTL1-CTL4 can be selectively turned on or off according to a plurality of control signals, respectively. For example, in an operating state, when the control switch CTL1 is turned on and the control switches CTL2-CTL4 are turned off, corresponding to the output signal of the positive output terminal of thegain stage 20, the current having the current amount I can pass through theswitch circuit 201 Provided to the output ofoutput stage 30 . In another operating state, when the control switches CTL1-CTL2 are turned on and the control switches CTL3-CTL4 are turned off, corresponding to the output signal of the positive output terminal of thegain stage 20, a current having the current amount 2I can be provided via theswitch circuit 201 to the output ofoutput stage 30 .

由此即可对流过开关电路201的电流的电流量进行调整。换言之，通过控制信号控制控制开关CTL1-CTL4的导通或关断，即可使开关电路201的开关宽度得以调整，进而使得输出缓冲器200的输出电压的上升变化率为可调整的。Thereby, the amount of current flowing through theswitching circuit 201 can be adjusted. In other words, the switching width of theswitching circuit 201 can be adjusted by controlling the on or off of the control switches CTL1 - CTL4 by the control signal, thereby making the rising rate of change of the output voltage of theoutput buffer 200 adjustable.

在一实施例中，上述控制信号可由控制信号产生器(未示出)提供。在一实施例中，控制信号产生器可设置于源极驱动电路120中，然本案不以此为限。另外，应注意到，虽然在上述实施例中，是以工作开关M01-M04的宽度彼此相同为例进行说明，然而在不同实施例中，工作开关M01-M04的宽度也可彼此不同。In one embodiment, the aforementioned control signals may be provided by a control signal generator (not shown). In one embodiment, the control signal generator may be disposed in thesource driving circuit 120, but the present application is not limited to this. In addition, it should be noted that although in the above embodiments, the widths of the working switches M01-M04 are the same as each other for illustration, but in different embodiments, the widths of the working switches M01-M04 may also be different from each other.

应注意到，本公开内容所述的控制开关CTL1-CTL4及工作开关M01-M04皆可用晶体管实现，然而本案不以此为限。It should be noted that the control switches CTL1-CTL4 and the operating switches M01-M04 described in the present disclosure can be implemented by transistors, but the present application is not limited to this.

应注意到，上述实施例中，虽以具有4个控制开关与4个工作开关的开关电路201为例进行说明，然而在不同实施例中，控制开关与控制开关的数量也可有所不同，故本案并不以图4中所绘示的开关电路201为限。It should be noted that in the above embodiments, although theswitch circuit 201 having 4 control switches and 4 working switches is used as an example for description, in different embodiments, the number of control switches and control switches may also be different. Therefore, the present case is not limited to theswitch circuit 201 shown in FIG. 4 .

类似地，在本实施例中，输出缓冲器250的开关电路203相似于前述输出缓冲器200的开关电路201，故相关细节在此不赘述。Similarly, in this embodiment, theswitch circuit 203 of theoutput buffer 250 is similar to theswitch circuit 201 of theoutput buffer 200 described above, so the related details are not repeated here.

参照图5，图5为根据本发明一操作例所绘示的信号图。在本操作例中，波形SC1为对应输出缓冲器200输出的数据电压，波形SC2为对应输出缓冲器250输出的数据电压。在本操作例中，由于输出缓冲器200与输出缓冲器250分别用以输出彼此极性相反的数据电压，故波形SC1与波形SC2彼此大致相反。在本操作例，噪声Noise表示触控元件上量测到的噪声。Referring to FIG. 5 , FIG. 5 is a signal diagram according to an operation example of the present invention. In this operation example, the waveform SC1 corresponds to the data voltage output from theoutput buffer 200 , and the waveform SC2 corresponds to the data voltage output from theoutput buffer 250 . In this operation example, since theoutput buffer 200 and theoutput buffer 250 are respectively used for outputting data voltages with opposite polarities to each other, the waveform SC1 and the waveform SC2 are substantially opposite to each other. In this operating example, Noise represents the noise measured on the touch element.

在时间点t1时，触控元件量测到一负向噪声。此时，若使输出缓冲器200输出的数据电压的上升变化率增加，则可抵销或减缓此一负向噪声。另外，类似地，在时间点t2时，触控元件量测到一正向噪声。此时，若使输出缓冲器200输出的数据电压的上升变化率减低，则可抵销或减缓此一正向噪声。At time point t1, the touch element measures a negative noise. At this time, if the rising rate of change of the data voltage output from theoutput buffer 200 is increased, the negative noise can be offset or slowed down. In addition, similarly, at the time point t2, the touch element measures a forward noise. At this time, if the rate of rise and change of the data voltage output from theoutput buffer 200 is reduced, the forward noise can be offset or reduced.

通过上述的操作，驱动电路120即可通过调整开关电路201、203的开关宽度，以使输出缓冲器200、250输出的数据电压的上升变化率与下降变化率彼此不同，以对触控元件量测到的噪声进行调整。Through the above-mentioned operations, the drivingcircuit 120 can adjust the switching widths of the switchingcircuits 201 and 203 so that the rising change rate and the falling change rate of the data voltage output by the output buffers 200 and 250 are different from each other, so as to adjust the amount of touch elements. The measured noise is adjusted.

应注意到，虽然在上述实施例中，是以对触控元件量测到的噪声进行调整为例进行说明，然而本案不以此为限。通过上述的操作，也可调整其它相关元件上的噪声。It should be noted that although in the above embodiments, the adjustment of the noise measured by the touch element is used as an example for description, but the present application is not limited to this. Through the above operations, the noise on other related components can also be adjusted.

图6为根据本发明另一实施例所绘示的驱动电路120的示意图。在本实施例中，开关电路202、204的开关宽度是可调整的。由此，驱动电路120即可通过调整开关电路202、204的开关宽度，以使输出缓冲器200、205输出的数据电压的上升变化率与下降变化率彼此不同，以对噪声进行调整。FIG. 6 is a schematic diagram of adriving circuit 120 according to another embodiment of the present invention. In this embodiment, the switch widths of theswitch circuits 202 and 204 are adjustable. In this way, the drivingcircuit 120 can adjust the noise by adjusting the switching widths of the switchingcircuits 202 and 204 so that the rising change rate and the falling change rate of the data voltage output from the output buffers 200 and 205 are different from each other.

图7为根据本发明另一实施例所绘示的驱动电路120的示意图。在本实施例中，开关电路201-204的开关宽度是可调整的。由此，驱动电路120即可通过调整开关电路201-204的开关宽度，以使输出缓冲器200、205输出的数据电压的上升变化率与下降变化率彼此不同，以对噪声进行调整。FIG. 7 is a schematic diagram of adriving circuit 120 according to another embodiment of the present invention. In this embodiment, the switch widths of the switch circuits 201-204 are adjustable. Therefore, the drivingcircuit 120 can adjust the noise by adjusting the switching widths of the switchingcircuits 201 to 204 so that the rising change rate and the falling change rate of the data voltages output by the output buffers 200 and 205 are different from each other.

图8为根据本发明另一实施例所绘示的驱动电路120的示意图。在本实施例中，驱动电路120包括输出缓冲器200a、输出开关OS1、输出缓冲器250a、输出开关OS2、及电流源IS1、IS2。在一实施例中，输出缓冲器200a的输出端电性连接于输出开关OS1，且输出缓冲器250a的输出端电性连接输出开关OS2。在一实施例中，输出缓冲器200a、250a彼此相邻设置。在一实施例中，电流源IS1电性连接于输出缓冲器200a，且电流源IS2电性连接于输出缓冲器250a。在一实施例中，输出缓冲器200a、250a用以输出数据电压(如分别用以输出数据电压D(1)、D(2))。在一实施例中，输出开关OS1、OS2用以相应于锁存信号(未示出)将数据电压提供至像素阵列101。在一实施例中，电流源IS1用以提供偏压电流I1至输出缓冲器200a，且电流源IS2用以提供偏压电流I2至输出缓冲器250a。FIG. 8 is a schematic diagram of adriving circuit 120 according to another embodiment of the present invention. In this embodiment, the drivingcircuit 120 includes anoutput buffer 200a, an output switch OS1, anoutput buffer 250a, an output switch OS2, and current sources IS1 and IS2. In one embodiment, the output terminal of theoutput buffer 200a is electrically connected to the output switch OS1, and the output terminal of theoutput buffer 250a is electrically connected to the output switch OS2. In one embodiment, theoutput buffers 200a, 250a are arranged adjacent to each other. In one embodiment, the current source IS1 is electrically connected to theoutput buffer 200a, and the current source IS2 is electrically connected to theoutput buffer 250a. In one embodiment, theoutput buffers 200a and 250a are used for outputting data voltages (eg, for outputting data voltages D(1) and D(2), respectively). In one embodiment, the output switches OS1, OS2 are used to provide data voltages to thepixel array 101 in response to latch signals (not shown). In one embodiment, the current source IS1 is used to provide the bias current I1 to theoutput buffer 200a, and the current source IS2 is used to provide the bias current I2 to theoutput buffer 250a.

在一实施例中，电流源IS1为可调电流源。在一实施例中，电流源IS1提供至输出缓冲器200a的偏压电流I1的电流量是可调整的，以调整输出缓冲器200a的转换率(slewrate)。在一实施例中，电流源IS1是根据调整信号ADS1调整偏压电流I1的电流量。另外，在一实施例中，电流源IS2为固定电流源，然本案不以此为限。In one embodiment, the current source IS1 is an adjustable current source. In one embodiment, the amount of bias current I1 provided by the current source IS1 to theoutput buffer 200a is adjustable to adjust the slewrate of theoutput buffer 200a. In one embodiment, the current source IS1 adjusts the current amount of the bias current I1 according to the adjustment signal ADS1. In addition, in one embodiment, the current source IS2 is a fixed current source, but the present application is not limited to this.

参照图9，图9为根据本发明另一操作例所绘示的信号图。在本操作例中，波形SC1为对应输出缓冲器200a输出的数据电压，波形SC2为对应输出缓冲器250a输出的数据电压。在本操作例中，由于输出缓冲器200a与输出缓冲器250a分别用以输出彼此极性相反的数据电压，故波形SC1与波形SC2彼此大致相反。在本操作例，噪声Noise表示触控元件上量测到的噪声。Referring to FIG. 9 , FIG. 9 is a signal diagram according to another operation example of the present invention. In this operation example, the waveform SC1 corresponds to the data voltage output from theoutput buffer 200a, and the waveform SC2 corresponds to the data voltage output from theoutput buffer 250a. In this operation example, since theoutput buffer 200a and theoutput buffer 250a are respectively used for outputting data voltages with opposite polarities to each other, the waveform SC1 and the waveform SC2 are substantially opposite to each other. In this operating example, Noise represents the noise measured on the touch element.

在时间点t1时，触控元件量测到一负向噪声。此时，若使偏压电流I1增加，以令输出缓冲器200a的转换率增加，则可抵销或减缓此一负向噪声。另外，类似地，在时间点t2时，触控元件量测到一正向噪声。此时，若使偏压电流I1减少，以令输出缓冲器200a的转换率减低，则可抵销或减缓此一正向噪声。At time point t1, the touch element measures a negative noise. At this time, if the bias current I1 is increased to increase the slew rate of theoutput buffer 200a, the negative noise can be offset or reduced. In addition, similarly, at the time point t2, the touch element measures a forward noise. At this time, if the bias current I1 is reduced to reduce the slew rate of theoutput buffer 200a, the forward noise can be offset or reduced.

通过上述的操作，驱动电路120即可通过调整偏压电流I1，以使输出缓冲器200a、250a的转换率彼此不同，以对触控元件量测到的噪声进行调整。Through the above operations, the drivingcircuit 120 can adjust the noise measured by the touch element by adjusting the bias current I1 so that the conversion ratios of theoutput buffers 200a and 250a are different from each other.

应注意到，虽然在上述实施例中，是以对触控元件量测到的噪声进行调整为例进行说明，然而本案不以此为限。通过上述的操作，也可调整其它相关元件上的噪声。It should be noted that although in the above embodiments, the adjustment of the noise measured by the touch element is used as an example for description, but the present application is not limited to this. Through the above operations, the noise on other related components can also be adjusted.

图10为根据本发明另一实施例所绘示的驱动电路120的示意图。在本实施例中，电流源IS2可根据调整信号ADS2调整偏压电流I2的电流量。由此，驱动电路120即可通过调整偏压电流I2，以使输出缓冲器200a、250a的转换率彼此不同，以对噪声进行调整。FIG. 10 is a schematic diagram of adriving circuit 120 according to another embodiment of the present invention. In this embodiment, the current source IS2 can adjust the current amount of the bias current I2 according to the adjustment signal ADS2. Accordingly, the drivingcircuit 120 can adjust the noise by adjusting the bias current I2 so that the conversion ratios of theoutput buffers 200a and 250a are different from each other.

图11为根据本发明另一实施例所绘示的驱动电路120的示意图。在本实施例中，电流源IS1、IS2可分别根据调整信号ADS1、ADS2调整偏压电流I1、I2的电流量。由此，驱动电路120即可通过调整偏压电流I1、I2，以使输出缓冲器200a、250a的转换率彼此不同，以对噪声进行调整。FIG. 11 is a schematic diagram of adriving circuit 120 according to another embodiment of the present invention. In this embodiment, the current sources IS1 and IS2 can respectively adjust the current amounts of the bias currents I1 and I2 according to the adjustment signals ADS1 and ADS2 . Therefore, the drivingcircuit 120 can adjust the noise by adjusting the bias currents I1 and I2 so that the conversion ratios of the output buffers 200 a and 250 a are different from each other.

虽然本发明已以实施例公开如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，可当作各种的更动与润饰，因此本发明的保护范围当视权利要求为准。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the claims.

Claims (10)

1. A driving circuit of a display panel, comprising:

a first output buffer;

a second output buffer; and

a first current source for providing a first bias current to the first output buffer;

wherein, the first current source is an adjustable current source;

in an adjustment state, the driving circuit is used for adjusting the first bias current output by the first current source so that the conversion rate of the first output buffer and the conversion rate of the second output buffer are different from each other.

2. The driving circuit of a display panel according to claim 1, further comprising:

a second current source for providing a second bias current to the second output buffer, wherein the second bias current source is an adjustable current source;

and in the adjustment state, the driving circuit is further configured to adjust the second bias current output by the second current source so that the slew rate of the first output buffer and the slew rate of the second output buffer are different from each other.

3. The driving circuit of a display panel according to claim 1, further comprising:

a second current source for providing a second bias current to the second output buffer, wherein the second bias current source is a fixed current source.

4. A driving circuit of a display panel, comprising:

a first output buffer comprising an output stage, the output stage comprising:

a first switch circuit electrically connected between an output latch and a first power supply; and

a second switch circuit electrically connected between the output latch and a second power supply;

wherein the switching width of the first switching circuit is adjustable.

5. The display panel driving circuit according to claim 4, wherein a switching width of the second switching circuit is adjustable.

6. The driving circuit of claim 4, wherein in an aligned state, the driving circuit adjusts a switching width of the first switching circuit such that a rising rate of change of an output voltage of the first output buffer is different from a falling rate of change.

7. The display panel driving circuit according to claim 4, wherein the first switching circuit comprises:

a plurality of working switches, a plurality of first ends of which are electrically connected with each other; and

a plurality of control switches, wherein a plurality of first ends of the control switches are respectively electrically connected with a plurality of second ends of the working switches, and the plurality of second ends of the control switches are electrically connected with each other;

the control switches are selectively switched on and off according to a plurality of control signals respectively to adjust the switching width of the first switching circuit.

8. A driving circuit of a display panel, comprising:

an output buffer comprising an output stage, the output stage comprising:

a first switching circuit, wherein a switching width of the first switching circuit is adjustable;

in an adjustment state, the driving circuit adjusts the switching width of the switching circuit so that a rising change rate of an output voltage of the output buffer is different from a falling change rate.

9. The driving circuit of the display panel according to claim 8, wherein the output stage further comprises:

a second switching circuit, wherein the switching width of the second switching circuit is adjustable.

10. The display panel driving circuit according to claim 8, wherein the first switching circuit comprises:

a plurality of working switches, a plurality of first ends of which are electrically connected with each other; and

a plurality of control switches, wherein a plurality of first ends of the control switches are respectively electrically connected with a plurality of second ends of the working switches, and the plurality of second ends of the control switches are electrically connected with each other;

the control switches are selectively switched on and off according to a plurality of control signals respectively to adjust the switching width of the first switching circuit.

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