CN111584639B - Thin film transistor substrate and preparation method thereof - Google Patents
Thin film transistor substrate and preparation method thereofDownload PDFInfo
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- CN111584639B CN111584639BCN202010388320.4ACN202010388320ACN111584639BCN 111584639 BCN111584639 BCN 111584639BCN 202010388320 ACN202010388320 ACN 202010388320ACN 111584639 BCN111584639 BCN 111584639B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/871—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group I-VI materials, e.g. Cu2O; being Group I-VII materials, e.g. CuI
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
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- Thin Film Transistor (AREA)
Abstract
Translated fromChinese
Description
Technical Field
The present disclosure relates to the field of panel display technologies, and in particular, to a thin film transistor substrate and a method for manufacturing the thin film transistor substrate.
Background
With the development of display technology, display devices have been widely used in various fields.
Meanwhile, with the development of display technology and the improvement of differentiation requirements, the market puts more demands on the performance of the panel. In the existing display panel, a polysilicon active layer of a thin film transistor needs to have higher mobility during preparation, but the higher mobility causes higher leakage current of the thin film transistor, and also causes higher power consumption of a thin film transistor substrate under low-frequency driving, so that a static black picture during panel display is difficult to well maintain, and the picture quality of equipment is poor. In addition, the obtained polysilicon active layer has a large hysteresis, and thus has a problem of image sticking during display. Therefore, the existing products cannot utilize the lower leakage current of the oxide thin film transistor, and simultaneously ensure the characteristic of higher mobility, and finally achieve the purpose of improving the display quality and the comprehensive performance of the display panel.
In summary, in the existing products such as the thin film transistor in the display panel, it is impossible to achieve the dual characteristics of the thin film transistor with a relatively high mobility under the condition of relatively low leakage current, and the improvement of the comprehensive performance of the product is not facilitated.
Disclosure of Invention
The present disclosure provides a thin film transistor substrate and a method for manufacturing the thin film transistor substrate, so as to solve the problems that the thin film transistor in the conventional display panel cannot achieve the dual characteristics of higher mobility and unsatisfactory display quality of the display panel under the condition of lower leakage current.
To solve the above technical problem, the technical solution provided by the embodiment of the present disclosure is as follows:
according to a first aspect of embodiments of the present disclosure, there is provided a thin film transistor substrate including:
a substrate; and
an active layer disposed on the substrate;
the active layer comprises a first metal oxide and a second metal oxide, the first metal oxide is arranged at two ends of the active layer, and the first metal oxide is a P-type semiconductor material.
According to an embodiment of the disclosure, the non-display area includes a frame area and a bendable area, the frame area and the bendable area are disposed adjacent to each other, and the bendable area is close to an edge of the touch panel.
According to an embodiment of the present disclosure, the P-type semiconductor material includes CuO and Cu2O。
According to an embodiment of the present disclosure, the second metal oxide is an N-type semiconductor material, and the N-type semiconductor material includes IGZO, ITO, and IZO.
According to an embodiment of the present disclosure, the thin film transistor substrate further includes:
a gate disposed on the substrate;
a gate insulating layer disposed on the substrate and covering the gate; and
and a source electrode and a drain electrode disposed on the gate insulating layer and forming a channel region with the active layer.
The first metal oxide is attached to one side face, close to the substrate, of the source electrode and the drain electrode.
According to a second aspect of the embodiments of the present disclosure, there is also provided a method for manufacturing a thin film transistor substrate, including the steps of:
s100: providing a substrate, and preparing a grid electrode of a thin film transistor on the substrate;
s101: depositing a gate insulating layer, forming an active layer on the gate insulating layer, wherein the active layer is made of a second metal oxide material, repairing defects of the active layer at high temperature, and patterning the active layer by using an etching process;
s102: depositing a source electrode and a drain electrode of the thin film transistor, wherein the source electrode and the drain electrode comprise a Cu electrode and a metal electrode which can form a P-type oxide semiconductor material, and the metal electrode is in direct contact with the second metal oxide;
s103: high-temperature annealing is carried out, so that a first metal oxide is formed in a region where the metal electrode is in contact with the second metal oxide, and the first metal oxide is a P-type semiconductor material;
s104: depositing a passivation layer, opening holes by using an etching process, and finally completing the preparation of the thin film transistor substrate
According to an embodiment of the present disclosure, the material of the gate includes metal MO and metal AL, and the thickness of the gate is 2000 angstroms to 5500 angstroms.
According to an embodiment of the present disclosure, the gate insulating layer is prepared by a plasma enhanced chemical vapor deposition process, and the thickness of the gate insulating layer is 1500 to 4000 angstroms.
According to an embodiment of the present disclosure, in the step S101, the defect repair is performed on the active layer at a temperature of 200 ℃ to 400 ℃ for 0.5 hour to 4 hours.
According to an embodiment of the present disclosure, in the step S102, a material of a side of the metal electrode away from the active layer is Mo, MoTi, or a material capable of protecting the metal electrode from oxidation.
According to an embodiment of the present disclosure, in the step S103, a high temperature annealing process is performed at a temperature of 200 ℃ to 450 ℃ under an atmosphere of a protective gas.
In summary, the beneficial effects of the embodiment of the present disclosure are:
the disclosed embodiments provide a thin film transistor substrate and a method of manufacturing the sameThe preparation method comprises selecting a second metal oxide material as the active layer material when preparing the active layer of the thin film transistor, and adopting a Cu electrode material when preparing the source electrode and the drain electrode, wherein the Cu electrode material of the contact region of the drain electrode, the source electrode and the active layer is interacted with the second metal oxide material to form a first metal oxide layer, such as CuO and Cu2The thin film transistor substrate obtained by the method in the embodiment of the disclosure has not only higher mobility, but also lower leakage current, and the comprehensive performance of the thin film transistor substrate is superior.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some of the disclosed embodiments, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic structural diagram of a thin film transistor substrate according to an embodiment of the disclosure;
fig. 2 is a schematic process flow diagram of a method for manufacturing a thin film transistor substrate according to an embodiment of the disclosure;
fig. 3A to 3D are schematic structural diagrams of a thin film transistor substrate corresponding to a process of manufacturing the thin film transistor substrate according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of another tft substrate according to an embodiment of the disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are merely illustrative of some, but not all embodiments of the disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any inventive step, are intended to be within the scope of the present disclosure.
With the variety of display panel types and performances, people have higher and higher requirements on the display panel, and the embodiment of the disclosure provides a thin film transistor substrate, wherein a thin film transistor in the thin film transistor substrate has high electron mobility, low leakage current and good comprehensive performance.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a thin film transistor substrate according to an embodiment of the disclosure.
The thin film transistor substrate includes asubstrate 100, agate electrode 101, and agate insulating layer 102.
Thegate 101 is disposed on thesubstrate 100, thegate insulating layer 102 is disposed on thesubstrate 100 and completely covers thegate 101, and when thegate 101 is fabricated, thegate 101 may be fabricated by a physical vapor deposition process, and after the deposition, thegate 101 may be etched by an etching process such as a yellow light process, and after the deposition, thegate 101 with a thickness of 2000 angstroms to 5500 angstroms is finally obtained.
The material of thegate 101 may be MO or Al, or other metal materials with good electrical conductivity.
Thegate insulating layer 102 may be formed by a pecvd process, and the material of thegate insulating layer 102 may be selected from SiOx or a composite layer of SiNx and SiOx.
After deposition, thegate insulating layer 102 may be etched by using an etching process such as a yellow light process, and thegate insulating layer 102 having a thickness of 1500 to 4000 angstroms is finally obtained after the deposition.
Preferably, the thin film transistor substrate further includes anactive layer 106 and adrain electrode 104 and asource electrode 105 of the thin film transistor.
Theactive layer 106 is disposed on thegate insulating layer 102, thedrain electrode 104 and thesource electrode 105 are both disposed on thegate insulating layer 102, and a partial region of the source and drain electrodes is in contact with theactive layer 106, i.e., overlaps with a portion of theactive layer 106, i.e., thedrain electrode 104 and thesource electrode 105 form achannel region 107 with theactive layer 106.
In the disclosed embodiment, theactive layer 106 also includes a firstmetal oxide layer 1061 and a secondmetal oxide layer 1062.
The firstmetal oxide layer 1061 may be disposed at two end regions of theactive layer 106, and in particular, the firstmetal oxide layer 1061 may be disposed in a region where thedrain 104 and thesource 105 overlap with theactive layer 106, or the firstmetal oxide layer 1061 extends beyond the overlapping region and extends into thechannel region 107.
Specifically, the firstmetal oxide layer 1061 may be disposed on the upper surface of the secondmetal oxide layer 1062, or may form a step-like structure directly with the secondmetal oxide layer 1062, so as to ensure that the firstmetal oxide layer 1061 has a sufficient thickness and ensure the performance of the thin film transistor.
In the embodiment of the disclosure, the material of the firstmetal oxide layer 1061 is a P-type semiconductor material, preferably CuO or Cu2Copper oxide material of O, or other metal or alloy material that can form a P-type oxide semiconductor material.
The secondmetal oxide layer 1062 is a material of a semiconductor layer of a general thin film transistor, and preferably, the secondmetal oxide layer 1062 is made of an N-type semiconductor material such as IGZO, ITO, and IZO.
Theactive layer 106 and the source/drain electrodes may be formed by a physical vapor deposition process. Annealing treatment can be carried out at the temperature of 150-450 ℃, and after the preparation and the treatment are finished, the thickness of the obtainedactive layer 106 is 300-700 angstroms, and the thickness of thedrain electrode 104 and thesource electrode 105 of the thin film transistor is 2000-5500 angstroms.
In the embodiment of the present disclosure, the thickness of the firstmetal oxide layer 1061 may be set according to the actual product, and may also be set at intervals in the overlapping area to achieve different material properties.
As shown in fig. 2, fig. 2 is a process flow diagram of a method for manufacturing a thin film transistor substrate according to an embodiment of the disclosure. The preparation process comprises the following steps:
s100: providing a substrate, and preparing a grid electrode of a thin film transistor on the substrate
Specifically, as shown in fig. 3A, fig. 3A is a schematic structural diagram of the thin film transistor substrate in the process of manufacturing the thin film transistor substrate according to the embodiment of the disclosure. First, asubstrate 300 is provided, and agate layer 101 for forming a thin film transistor is formed on thesubstrate 100. When thegate layer 101 is manufactured, a physical vapor deposition process may be used to manufacture thegate layer 101, a material of thegate layer 101 may include a metal material such as Mo or Al, and a material of thesubstrate 100 may include a material such as transparent glass. After the preparation is finished, the thickness of the obtainedgate layer 101 is 2000-5500 angstroms.
S101: depositing a gate insulating layer, forming an active layer on the gate insulating layer, wherein the active layer is made of a second metal oxide material, repairing defects of the active layer at high temperature, and patterning the active layer by using an etching process
After thesubstrate 100 and thegate layer 101 are fabricated, other layers are further fabricated. Specifically, as shown in fig. 3B, agate insulating layer 302 is formed on thesubstrate 100 such that thegate insulating layer 302 completely covers thegate layer 301. When thegate insulating layer 302 is prepared, deposition can be performed through a plasma enhanced chemical vapor deposition process, the deposition thickness is 1500-4000 angstroms, and the material of thegate insulating layer 302 comprises SiOx or a composite layer of SiNx and SiOx.
Meanwhile, anactive layer 303 is prepared on thegate insulating layer 302. Specifically, a physical vapor deposition process is used for depositing a semiconductor layer of theactive layer 303, wherein the material of theactive layer 303 may be a second metal oxide material, preferably, the material may be Indium Gallium Zinc Oxide (IGZO), or other metal semiconductor materials, then high-temperature annealing is used for defect repair of the etchedactive layer 303, the annealing temperature is 200 to 400 ℃, the processing time is 0.5 to 4 hours, and then a yellow light process and an etching process are sequentially used for processing theactive layer 303.
S102: depositing a source electrode and a drain electrode of the thin film transistor, wherein the source electrode and the drain electrode comprise a Cu electrode and a metal electrode capable of forming a P-type oxide semiconductor material, and the metal electrode is in direct contact with the second metal oxide
After the above steps are completed, the preparation of other film layers is continued, as shown in fig. 3C, thedrain electrode 304 and thesource electrode 305 are continuously prepared, thedrain electrode 304 and thesource electrode 305 are both disposed on thegate insulating layer 302, and a portion of thedrain electrode 304 and thesource electrode 305 overlap with a portion of theactive layer 303, i.e., achannel region 307 of the thin film transistor is formed.
Specifically, the source and drain electrodes can be deposited by adopting a physical vapor deposition process, and the thicknesses of the source and drain electrodes are respectively 2000-5500 angstroms. The material may be selected to be a Cu electrode, and may also be other metal materials or other metal electrodes capable of forming a P-type oxide semiconductor material. In preparation, the Cu electrode is in direct contact with the second metal oxide of theactive layer 303, and the upper metal is Mo or MoTi or other material that can protect the Cu electrode from oxidation.
S103: high-temperature annealing is carried out, so that a first metal oxide is formed in a region where the metal electrode is in contact with the second metal oxide, and the first metal oxide is a P-type semiconductor material
And performing high-temperature annealing treatment on the source and drain electrodes in the step S102. As shown in fig. 3D, since the electrode material is selected to be Cu, which reacts with thesecond metal layer 3032 in the contact region 308 of theactive layer 303 to form a firstmetal oxide layer 3031, the firstmetal oxide layer 3031 is located at two end portions of theactive layer 303, and the area of the formed region may be smaller than or equal to the area of the contact region 308, or may partially exceed the contact region 308, and the specific size may be set according to actual needs.
Specifically, the firstmetal oxide layer 3031 may be CuO or Cu2O, or other materials that may be P-type semiconductors. The thickness of the firstmetal oxide layer 3031 may be set according to a specific product.
During annealing, high-temperature annealing treatment is carried out at the temperature of 200-450 ℃ in the atmosphere of protective gas, wherein the protective gas can be N2Or other gases that can protect the electrodes. After the annealing is completed, theactive layer 303 is etched by an etching process according to the need, wherein the etching depth ratio forms CuO or Cu2The depth of O is low.
Due to the different material properties of thefirst metal layer 3031 and thesecond metal layer 3032, the corresponding electron mobility is different, and a new PN junction is formed. In the embodiment of the present disclosure, theactive layer 303 has a larger electron mobility, and when it operates, the leakage current inside the thin film transistor is small, and the overall performance of the device is good.
S104: and depositing a passivation layer, opening holes by using an etching process, and finally finishing the preparation of the thin film transistor substrate.
Finally, as shown in fig. 4, fig. 4 is a schematic view of a structure of another thin film transistor substrate according to an embodiment of the disclosure. Thepassivation layer 400 is continuously prepared on the basis of the step S103, and a via hole structure is formed on thepassivation layer 400, and meanwhile, thepixel electrode 401 material is prepared in the via hole, and finally, the thin film transistor substrate in the embodiment of the disclosure is obtained.
The embodiment of the disclosure also provides a display panel and a display device, wherein the display panel and the display device comprise the thin film transistor substrate provided in the embodiment of the disclosure and the thin film transistor substrate structure obtained by the preparation method provided in the embodiment of the disclosure.
The thin film transistor substrate and the method for manufacturing the thin film transistor substrate provided by the embodiments of the present disclosure are introduced in detail above, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present disclosure; those of ordinary skill in the art will understand that: it is to be understood that modifications may be made to the arrangements described in the embodiments above, and such modifications or alterations may be made without departing from the spirit of the respective arrangements of the embodiments of the present disclosure.
Claims (6)
1. A preparation method of a thin film transistor substrate is characterized by comprising the following steps:
s100: providing a substrate, and preparing a grid electrode of a thin film transistor on the substrate;
s101: depositing a gate insulating layer, forming an active layer on the gate insulating layer, wherein the active layer is made of a second metal oxide material, repairing defects of the active layer at high temperature, and patterning the active layer by using an etching process;
s102: depositing a source electrode and a drain electrode of the thin film transistor, wherein the source electrode and the drain electrode comprise a Cu electrode and a metal electrode which can form a P-type oxide semiconductor material, and the metal electrode is in direct contact with the second metal oxide;
s103: high-temperature annealing is carried out, so that a first metal oxide is formed in a region where the metal electrode is in contact with the second metal oxide, and the first metal oxide is a P-type semiconductor material;
s104: and depositing a passivation layer, opening holes by using an etching process, and finally finishing the preparation of the thin film transistor substrate.
2. The method of claim 1, wherein the gate electrode comprises MO or Al, and has a thickness of 2000 to 5500 angstroms.
3. The method of claim 1, wherein the gate insulating layer is formed by a plasma enhanced chemical vapor deposition process, and the thickness of the gate insulating layer is 1500 to 4000 angstroms.
4. The method of manufacturing a thin film transistor substrate according to claim 1, wherein in the step S101, the active layer is subjected to defect repair at a temperature of 200 ℃ to 400 ℃ for 0.5 hour to 4 hours.
5. The method of claim 1, wherein in the step S102, a material of a side of the metal electrode away from the active layer is Mo or MoTi.
6. The method for manufacturing a thin film transistor substrate according to claim 1, wherein the stepS103, carrying out high-temperature annealing treatment at the temperature of 200-450 ℃ in the atmosphere of protective gas, wherein the protective gas comprises N2。
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