Disclosure of Invention
The invention provides a novel circuit implementation of a two-in-one data selector, which can reduce the number of transistors of the two-in-one data selector so as to reduce the chip area.
According to one aspect of the present invention there is provided a data selector comprising an nor circuit configured to receive a selection signal and an inverted first input and to produce an intermediate result, and an and nor circuit configured to receive the selection signal, the second input and the intermediate result of the nor circuit and to produce an inverted output.
Preferably, the inverted output is an inverted first input in case the selection signal is a logic 0 and an inverted second input in case the selection signal is a logic 1.
Preferably, the NOR logic circuit comprises a first PMOS transistor having a gate terminal configured to receive the selection signal, wherein a source terminal of the first PMOS transistor is coupled to the power supply terminal, a second PMOS transistor having a gate terminal configured to receive the inverted first input, a source terminal thereof coupled to a drain terminal of the first PMOS transistor, and a drain terminal thereof coupled to the first node, a first NMOS transistor having a gate terminal configured to receive the selection signal and a drain terminal thereof coupled to the first node, and a second NMOS transistor having a gate terminal thereof configured to receive the inverted first input, and a drain terminal thereof coupled to the first node, wherein the source terminal of each of the first NMOS transistor and the second NMOS transistor is coupled to the ground terminal, wherein the NOR logic circuit is configured to generate an intermediate result at the first node.
Preferably, the AND NOR logic circuit comprises a third PMOS transistor having a gate terminal configured to receive an intermediate result of the NOR logic circuit, wherein the source terminal of the third PMOS transistor is coupled to the power supply terminal, a fourth PMOS transistor having a gate terminal configured to receive the selection signal, a source terminal coupled to the drain terminal of the third PMOS transistor, and a drain terminal coupled to the second node, a fifth PMOS transistor having a gate terminal configured to receive the second input, a source terminal coupled to the drain terminal of the third PMOS transistor, and a drain terminal coupled to the second node, a third NMOS transistor having a gate terminal configured to receive an intermediate result of the NOR logic circuit, and a drain terminal coupled to the second node, a fourth NMOS transistor having a gate terminal configured to receive the selection signal, and a drain terminal coupled to the second node, and a fifth NMOS transistor having a gate terminal configured to receive the second input and a drain terminal coupled to the second node, wherein the third NMOS transistor and the fifth NMOS transistor are each coupled to the second node, wherein the first NMOS and the second NMOS transistor are configured to generate an inverted logic node.
Detailed Description
The following detailed description of embodiments presents various details of specific embodiments of the invention. The invention may, however, be embodied in a multitude of different ways as defined and covered by the claims. In this specification, the same reference numbers may indicate identical or functionally similar elements.
The data selector refers to a device which transmits data of a plurality of channels to a unique common data channel through selection, and realizes a data selection function. The logic expression of the alternative data selector isSel is a selection signal, a0 is a first input, and a1 is a second input. Fig. 1 shows a truth table of the alternative data selector, and fig. 2 shows a logic diagram of the alternative data selector. When the select signal sel is logic 0, the output X is the first input a0. When the select signal sel is logic 1, the output X is the second input a1.
Fig. 3 shows a block diagram of the structure of the MUX2 alternative data selector. As shown in fig. 3, the MUX2 alternative data selector includes an AOI22 logic circuit and two inverter INV logic circuits. The input terminal A0 receives the first input A0, and the input terminal A1 receives the second input A1. The output of the AOI22 logic circuit isThus, the output of MUX2 one-out-of-two data selector isThe MUX2 has large chip area occupied by the data selector, large delay and low speed.
Fig. 4 shows a block diagram of a MUXI alternative data selector. As shown in fig. 4, the MUXI a data selector includes an AOI22 logic circuit and an inverter INV logic circuit. Input terminal A0 receives first input A0, input terminal A1 receives second input A1, and outputsIs the inverse of the output X in fig. 3. The MUXI data selector has a small delay, but in some cases the occupied chip area is still large.
Fig. 5 shows a block diagram of an alternative data selector in which one input is inverted. As shown in fig. 5, the alternative data selector includes an AOI22 logic circuit and two inverter INV logic circuits. Input A0 receives an inverted first input a0_n (i.e., an inversion of A0), input A1 receives a second input A1, outputsIs the inverse of the output X in fig. 3. The two-in-one data selector also has the defects of large occupied chip area, large time delay and low speed.
For CMOS circuits, their natural outputs are inverted. If a positive phase output is to be achieved, an inverter is added after the natural output. The present invention takes advantage of this characteristic of CMOS circuitry to provide a novel circuit implementation of the one-out-of-two data selector that does not require inverters, thus enabling a reduction in the number of transistors of the one-out-of-two data selector and thus a reduction in chip area.
Fig. 6 shows a block diagram of an alternative data selector according to an embodiment of the present invention. The alternative data selector in fig. 6 includes nor logic NR2 and nor logic AOI21.
The NOR logic circuit NR2 is configured to receive the selection signal sel and the inverted first input a0_n and generate an intermediate resultThe AND NOR logic circuit AOI21 is configured to receive the selection signal sel, the second input a1, and the intermediate result gn1 of the NOR logic circuit, and generate an inverted output
Inverting the first input a0_n is the inverse of the first input a0, i.eFurther can obtainThat is to sayThat is, XN is the inverse of output X.
Thus, in the case where the select signal sel is a logic 0, the inverted output XN is the inverted first inputIn the case where the select signal sel is a logic 1, the inverted output XN is an inverted second input
Fig. 7 shows a CMOS circuit diagram of an alternative data selector in accordance with an embodiment of the present invention.
As shown in fig. 7, the nor logic circuit NR2 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The gate terminal of the first PMOS transistor P1 is configured to receive the selection signal sel. The source terminal of the first PMOS transistor P1 is coupled to the power supply terminal VDD. The gate terminal of the second PMOS transistor P2 is configured to receive the inverted first input a0_n, its source terminal is coupled to the drain terminal of the first PMOS transistor, and its drain terminal is coupled to the first node J1. The gate terminal of the first NMOS transistor N1 is configured to receive the selection signal sel and the drain terminal thereof is coupled to the first node J1. The gate terminal of the second NMOS transistor N2 is configured to receive the inverted first input a0_n and its drain terminal is coupled to the first node J1. A source terminal of each of the first NMOS transistor N1 and the second NMOS transistor N2 is coupled to the ground terminal VSS. The nor logic circuit NR2 is configured to produce an intermediate result gn1 at the first node J1.
The nor logic circuit AOI21 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. The gate terminal of the third PMOS transistor P3 is configured to receive the intermediate result gn1 of the nor logic circuit. The source terminal of the third PMOS transistor P3 is coupled to the power supply terminal VDD. The gate terminal of the fourth PMOS transistor P4 is configured to receive the selection signal sel, its source terminal is coupled to the drain terminal of the third PMOS transistor, and its drain terminal is coupled to the second junction J2. The gate terminal of the fifth PMOS transistor P5 is configured to receive the second input a1, its source terminal is coupled to the drain terminal of the third PMOS transistor P3, and its drain terminal is coupled to the second node J2. The gate terminal of the third NMOS transistor N3 is configured to receive the intermediate result gn1 of the nor logic circuit and its drain terminal is coupled to the second node J2. The gate terminal of the fourth NMOS transistor N4 is configured to receive the selection signal sel and the drain terminal thereof is coupled to the second node J2. The gate terminal of the fifth NMOS transistor N5 is configured to receive the second input a1 and its drain terminal is coupled to the source terminal of the fourth NMOS transistor N4. A source terminal of each of the third NMOS transistor N3 and the fifth NMOS transistor N5 is coupled to the ground terminal VSS. The and nor logic circuit AOI21 is configured to generate an inverted output XN at the second node J2.
The alternative data selector of the embodiment of the present invention is formed by combining an nor logic circuit NR2 and an nor logic circuit AOI 21. The whole circuit does not need an inverter, so that the use of a transistor is reduced, and the chip area is saved.
The alternative data selector of the present invention is described above in connection with certain embodiments. However, it should be understood that any feature of any one embodiment may be combined with and/or substituted for any other feature of any other embodiment.
Aspects of the present disclosure may be implemented in a variety of electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics, electronic test devices, cellular communication infrastructure such as base stations, and the like. Examples of electronic devices may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smartwatches or headphones, telephones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal Digital Assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, camcorders, cameras such as digital cameras, portable memory chips, washing machines, dryers, washing/drying machines, peripherals, clocks, and the like. Furthermore, the electronic device may comprise a non-complete product.
Throughout the specification and claims, the words "comprise," "include," "have" and the like are to be construed in an inclusive sense, rather than an exclusive or exhaustive sense, unless the context clearly requires otherwise. That is, it is meant to "include, but not limited to. As generally used herein, the term "coupled" refers to two or more elements that may be connected directly or through one or more intervening elements. Likewise, as generally used herein, the term "connected" refers to two or more elements that may be connected directly or through one or more intervening elements. In addition, as used in this application, the words "herein," "above," "below," "above," and words of similar import shall refer to this application as a whole and not to any particular portions of this application.
Furthermore, unless explicitly stated otherwise or otherwise understood in the context of use, conditional language such as "may," "might," "for example," "such as," etc., as used herein are generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or states. Thus, such conditional language is not generally intended to imply that one or more embodiments require, or include, in any way, features, elements and/or states or that such features, elements and/or states are to be performed in any particular embodiment.
While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The various features and processes described above may be implemented independently of each other or may be combined in various ways. All suitable combinations and subcombinations of the features of the disclosure are intended to be within the scope of the disclosure.