CN111554718A - Array substrate, manufacturing method thereof, and display device - Google Patents
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Abstract
Description
Translated fromChinese技术领域technical field
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。The present invention relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
背景技术Background technique
在OLED阵列基板中，公共阴极层需要在阵列基板的边框区域通过过孔与电源线连接，相关技术中，公共阴极层通常通过位于阳极层的电连接部与电源线连接。由于电连接部与阳极层通过一次构图工艺形成，电连接部的材料与阳极层的材料相同，同时，由于相关技术中OLED阵列基板中的阳极层的方块电阻较大，因此，相关技术中公共阴极层与电源线之间的电阻较大，从而增大了公共阴极外围的电阻。In the OLED array substrate, the common cathode layer needs to be connected to the power line through a via hole in the frame area of the array substrate. In the related art, the common cathode layer is usually connected to the power line through an electrical connection part located on the anode layer. Since the electrical connection portion and the anode layer are formed through a single patterning process, the material of the electrical connection portion is the same as the material of the anode layer. At the same time, since the sheet resistance of the anode layer in the OLED array substrate in the related art is relatively large, it is common in the related art. The resistance between the cathode layer and the power supply line is large, thereby increasing the resistance at the periphery of the common cathode.
需要说明的是，在上述背景技术部分发明的信息仅用于加强对本发明的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。It should be noted that the information disclosed in the above Background section is only for enhancing understanding of the background of the invention, and therefore may include information that does not form the prior art known to a person of ordinary skill in the art.
发明内容SUMMARY OF THE INVENTION
本发明的目的在于提供一种阵列基板及其制作方法、显示装置，该阵列基板能够解决相关技术中，公共阴极层与电源线之间的电阻较大的技术问题。The purpose of the present invention is to provide an array substrate, a manufacturing method thereof, and a display device, which can solve the technical problem of relatively large resistance between the common cathode layer and the power supply line in the related art.
本发明的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本发明的实践而习得。Other features and advantages of the present invention will become apparent from the following detailed description, or be learned in part by practice of the present invention.
根据本发明的一个方面，提供一种阵列基板，其包括边框区域和显示区域，所述边框区域包括：位于所述显示区域一侧的第一集成区、位于所述第一集成区远离所述显示区一侧的第二集成区，所述第一集成区用于集成栅极驱动电路，所述阵列基板还包括：衬底基板、第一导电层、第一平坦层、第二导电层、像素定义层、公共阴极层。第一导电层位于所述衬底基板的一侧，包括位于所述第二集成区的第一导电部；第一平坦层位于所述第一导电层背离所述衬底基板的一侧，所述第一平坦层上设置有第一开口，所述第一开口在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上；第二导电层位于所述第一平坦层背离所述衬底基板的一侧，包括第二导电部，所述第二导电部覆盖所述第一开口，以通过所述第一开口与所述第一导电部电连接；像素定义层位于所述第二导电层背离所述衬底基板的一侧，所述像素定义层形成有位于所述第一集成区的第二开口，所述第二开口在所述衬底基板的正投影位于所述第二导电部在所述衬底基板的正投影上；公共阴极层位于所述像素定义层背离所述衬底基板的一侧，覆盖所述第二开口，且通过所述第二开口与所述第二导电部电连接。According to one aspect of the present invention, an array substrate is provided, which includes a frame area and a display area, the frame area includes: a first integration area located on one side of the display area, a first integration area located away from the first integration area a second integrated area on one side of the display area, the first integrated area is used to integrate the gate drive circuit, and the array substrate further includes: a base substrate, a first conductive layer, a first flat layer, a second conductive layer, Pixel definition layer, common cathode layer. The first conductive layer is located on one side of the base substrate, and includes a first conductive portion located in the second integration region; the first flat layer is located on the side of the first conductive layer away from the base substrate, so The first flat layer is provided with a first opening, and the orthographic projection of the first opening on the base substrate is located on the orthographic projection of the first conductive portion on the base substrate; the second conductive layer is located on the orthographic projection of the base substrate. The side of the first flat layer facing away from the base substrate includes a second conductive portion, the second conductive portion covers the first opening, so as to be electrically connected to the first conductive portion through the first opening ; The pixel definition layer is located on the side of the second conductive layer away from the base substrate, the pixel definition layer is formed with a second opening located in the first integration region, and the second opening is located in the substrate The orthographic projection of the substrate is located on the orthographic projection of the second conductive portion on the base substrate; the common cathode layer is located on the side of the pixel definition layer away from the base substrate, covers the second opening, and passes through The second opening is electrically connected to the second conductive portion.
本公开一种示例性实施例中，所述第一导电部沿其所在边框区的边沿延伸方向延伸，所述第一开口沿其所在边框区的边沿延伸方向延伸；所述第二导电部沿其所在边框区的边沿延伸方向延伸，所述第二开口沿其所在边框区的边沿延伸方向延伸。In an exemplary embodiment of the present disclosure, the first conductive portion extends along the extending direction of the edge of the frame area where the first conductive portion is located, the first opening extends along the extending direction of the edge of the frame area where the first conductive portion is located; The edge of the frame area where the second opening is located extends along the extension direction of the edge of the frame area where the second opening is located.
本公开一种示例性实施例中，所述第一平坦层的位于所述第一开口面向第一集成区一侧的厚度大于所述第一开口面向第二集成区一侧的厚度。In an exemplary embodiment of the present disclosure, the thickness of the first flat layer on the side of the first opening facing the first integration region is greater than the thickness of the first opening facing the second integration region.
本公开一种示例性实施例中，所述阵列基板还包括薄膜晶体管、信号线；所述第一导电层还包括用于形成所述薄膜晶体管源漏部的第三导电部；所述第二导电层还包括用于形成所述信号线的第四导电部。In an exemplary embodiment of the present disclosure, the array substrate further includes a thin film transistor and a signal line; the first conductive layer further includes a third conductive part for forming the source and drain parts of the thin film transistor; the second conductive layer The conductive layer further includes a fourth conductive portion for forming the signal line.
本公开一种示例性实施例中，所述阵列基板还包括阳极层、第二平坦层，阳极层设置于所述像素定义层与所述第二导电层之间；第二平坦层，设置于所述第二导电层和阳极层之间，所述第二平坦层包括条形的第一平坦部，所述第一平坦部在所述衬底基板的正投影位于所述第一开口在所述衬底基板的正投影上，且沿所述第一开口的延伸方向延伸。In an exemplary embodiment of the present disclosure, the array substrate further includes an anode layer and a second flat layer, the anode layer is disposed between the pixel definition layer and the second conductive layer; the second flat layer is disposed on the Between the second conductive layer and the anode layer, the second flat layer includes a strip-shaped first flat portion, and the orthographic projection of the first flat portion on the base substrate is located where the first opening is located. on the orthographic projection of the base substrate and extending along the extending direction of the first opening.
本公开一种示例性实施例中，覆盖于所述第一平坦层上的所述第二导电部上设置有通气孔。In an exemplary embodiment of the present disclosure, the second conductive portion covering the first flat layer is provided with a vent hole.
本公开一种示例性实施例中，所述第二导电层由导电金属材料组成。In an exemplary embodiment of the present disclosure, the second conductive layer is composed of a conductive metal material.
根据本发明的一个方面，提供一种阵列基板制作方法，所述阵列基板包括边框区域和显示区域，所述边框区域包括：位于所述显示区域一侧的第一集成区、位于所述第一集成区远离所述显示区一侧的第二集成区，所述第一集成区用于集成栅极驱动电，所述阵列基板制作方法包括：According to one aspect of the present invention, a method for fabricating an array substrate is provided, the array substrate includes a frame area and a display area, and the frame area includes: a first integration area located on one side of the display area, a first integrated area located on one side of the display area, a The integration region is a second integration region on one side away from the display region, the first integration region is used for integrating gate driving power, and the fabrication method of the array substrate includes:
形成衬底基板；forming a base substrate;
在所述衬底基板的一侧形成第一导电层，所述第一导电层包括位于所述第二集成区的第一导电部；A first conductive layer is formed on one side of the base substrate, the first conductive layer includes a first conductive portion located in the second integrated region;
在所述第一导电层背离所述衬底基板的一侧形成第一平坦层，所述第一平坦层上设置有第一开口，所述第一开口在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上；A first flat layer is formed on the side of the first conductive layer away from the base substrate, a first opening is provided on the first flat layer, and the first opening is located at the orthographic projection of the base substrate the first conductive portion is on the orthographic projection of the base substrate;
在所述第一平坦层背离所述衬底基板的一侧形成第二导电层，所述第二导电层包括第二导电部，所述第二导电部覆盖所述第一开口，以通过所述第一开口与所述第一导电部电连接；A second conductive layer is formed on a side of the first flat layer away from the base substrate, the second conductive layer includes a second conductive portion, and the second conductive portion covers the first opening to pass through the first opening. the first opening is electrically connected to the first conductive portion;
在所述第二导电层背离所述衬底基板的一侧形成像素定义层，所述像素定义层形成有位于所述第一集成区的第二开口，所述第二开口在所述衬底基板的正投影位于所述第二导电部在所述衬底基板的正投影上；A pixel definition layer is formed on the side of the second conductive layer away from the base substrate, the pixel definition layer is formed with a second opening located in the first integration region, and the second opening is located in the substrate The orthographic projection of the substrate is located on the orthographic projection of the second conductive portion on the base substrate;
在所述像素定义层背离所述衬底基板的一侧形成公共阴极层，所述公共阴极层覆盖所述第二开口，且通过所述第二开口与所述第二导电部电连接。A common cathode layer is formed on a side of the pixel definition layer away from the base substrate, the common cathode layer covers the second opening, and is electrically connected to the second conductive portion through the second opening.
本公开一种示例性实施例中，在形成所述像素定义层之前还包括：In an exemplary embodiment of the present disclosure, before forming the pixel definition layer, the method further includes:
在所述第二导电层背离所述衬底基板一侧形成所述第二平坦层，所述第二平坦层包括条形的第一平坦部，所述第一平坦部在所述衬底基板的正投影位于所述第一开口在所述衬底基板的正投影上。The second flat layer is formed on the side of the second conductive layer away from the base substrate, the second flat layer includes a strip-shaped first flat portion, and the first flat portion is on the base substrate The orthographic projection of the first opening is on the orthographic projection of the base substrate.
根据本发明的一个方面，提供一种显示装置，该显示装置包括上述的阵列基板。According to an aspect of the present invention, there is provided a display device including the above-mentioned array substrate.
本公开提供一种阵列基板及其制作方法、显示装置，该阵列基板包括边框区域和显示区域，所述边框区域包括：位于所述显示区域一侧的第一集成区、位于所述第一集成区远离所述显示区一侧的第二集成区，所述第一集成区用于集成栅极驱动电路，所述阵列基板还包括：衬底基板、第一导电层、第一平坦层、第二导电层、像素定义层、公共阴极层。第一导电层位于所述衬底基板的一侧，包括位于所述第二集成区的第一导电部；第一平坦层位于所述第一导电层背离所述衬底基板的一侧，所述第一平坦层上设置有第一开口，所述第一开口在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上；第二导电层位于所述第一平坦层背离所述衬底基板的一侧，包括第二导电部，所述第二导电部覆盖所述第一开口，以通过所述第一开口与所述第一导电部电连接；像素定义层位于所述第二导电层背离所述衬底基板的一侧，所述像素定义层形成有位于所述第一集成区的第二开口，所述第二开口在所述衬底基板的正投影位于所述第二导电部在所述衬底基板的正投影上；公共阴极层位于所述像素定义层背离所述衬底基板的一侧，覆盖所述第二开口，且通过所述第二开口与所述第二导电部电连接。其中，第一导电部或第二导电部可以作为电源线连接外部电源，该阵列基板中第二导电部可以与公共阴极层直接电连接，从而减小了公共阴极与电源线之间的电阻。The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a frame area and a display area, and the frame area includes: a first integrated area located on one side of the display area, a first integrated area located on one side of the display area, and a display area. The second integration region on the side away from the display region, the first integration region is used to integrate the gate driving circuit, and the array substrate further includes: a base substrate, a first conductive layer, a first flat layer, a first Two conductive layers, pixel definition layers, and common cathode layers. The first conductive layer is located on one side of the base substrate, and includes a first conductive portion located in the second integration region; the first flat layer is located on the side of the first conductive layer away from the base substrate, so The first flat layer is provided with a first opening, and the orthographic projection of the first opening on the base substrate is located on the orthographic projection of the first conductive portion on the base substrate; the second conductive layer is located on the orthographic projection of the base substrate. The side of the first flat layer facing away from the base substrate includes a second conductive portion, the second conductive portion covers the first opening, so as to be electrically connected to the first conductive portion through the first opening ; The pixel definition layer is located on the side of the second conductive layer away from the base substrate, the pixel definition layer is formed with a second opening located in the first integration region, and the second opening is located in the substrate The orthographic projection of the substrate is located on the orthographic projection of the second conductive portion on the base substrate; the common cathode layer is located on the side of the pixel definition layer away from the base substrate, covers the second opening, and passes through The second opening is electrically connected to the second conductive portion. The first conductive part or the second conductive part can be used as a power supply line to connect to an external power supply, and the second conductive part in the array substrate can be directly electrically connected to the common cathode layer, thereby reducing the resistance between the common cathode and the power supply line.
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.
附图说明Description of drawings
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.
图1为相关技术中一种阵列基板的俯视图；1 is a top view of an array substrate in the related art;
图2为图1中阵列基板沿虚线A-A的剖视图；2 is a cross-sectional view of the array substrate in FIG. 1 along the dotted line A-A;
图3为本公开阵列基板一种示例性实施例中的俯视图；FIG. 3 is a top view of an exemplary embodiment of the disclosed array substrate;
图4为图3中阵列基板沿虚线A-A的剖视图；4 is a cross-sectional view of the array substrate in FIG. 3 along the dotted line A-A;
图5-6为本公开阵列基板一种示例性实施例中部分层级的结构示意图；5-6 are schematic structural diagrams of some levels in an exemplary embodiment of the disclosed array substrate;
图7为本公开阵列基板另一种示例性实施例中的结构示意图。FIG. 7 is a schematic structural diagram of another exemplary embodiment of the disclosed array substrate.
具体实施方式Detailed ways
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本发明将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, such as according to the direction of the example described. It will be appreciated that if the device of the icon is turned upside down, the components described as "on" will become the components on "bottom". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a certain structure is "on" other structures, it may mean that a certain structure is integrally formed on other structures, or that a certain structure is "directly" arranged on other structures, or that a certain structure is "indirectly" arranged on another structure through another structure. other structures.
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。The terms "a", "an", "the" are used to indicate the presence of one or more elements/components/etc; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and refer to Additional elements/components/etc may be present in addition to the listed elements/components/etc.
如图1、2所示，图1为相关技术中一种阵列基板的俯视图，图2为图1中阵列基板沿虚线A-A的剖视图。该阵列基板包括显示区域03和边框区域，边框区域包括用于集成栅极驱动电路的第一集成区02以及位于第一集成区远离显示区域一侧的第二集成区01，第二集成区01可以用于集成与公共阴极连接的信号线。该阵列基板中栅极驱动电路可以包括用于向像素驱动电路提供使能信号的EM GOA和用于向像素驱动电路提供栅极驱动信号的GateGOA。如图1所示，该阵列基板包括衬底基板1、位于衬底基板一侧的电路层2、位于电路层2背离衬底基板1一侧的第一导电层(可以包括第一导电部31、第二导电部32、第三导电部33以及第四导电部34)、位于第一导电层背离衬底基板一侧的第一平坦层4、位于第一平坦层4背离衬底基板一侧的第二导电层(包括第五导电部5)、位于第二导电层背离衬底基板1一侧的第二平坦层6，位于第二平坦层背离衬底基板一侧阳极层(包括第一电连接部7)、位于阳极层背离衬底基板一侧的像素定义层8、以及位于像素定义层8背离衬底基板一侧的公共阴极层9。其中，电路层2可以包括用于形成薄膜晶体管的有源层、栅极绝缘层、栅极层。第一导电层可以作为衬底基板中薄膜晶体管的源漏层，如图1所示，第二导电部32可以作为EM GOA中薄膜晶体管的源漏极或电容的电极；第三导电部33可以作为Gate GOA中薄膜晶体管的源漏极或电容的电极；第四导电部34可以为用于向像素驱动电路提供初始信号的信号线；第一导电部31可以用于形成与公共阴极连接的第一电源线。第五导电部5可以用于形成与公共阴极连接第二电源线，第五导电部5通过贯穿第一平坦层4上的开口与第一导电部31电连接，该并联的第一电源线和第二电源线可以减小公共阴极层外围的电阻。位于阳极层的第一电连接部7通过贯穿第二平坦层6的过孔与第五导电部5电连接，公共阴极层9通过贯穿像素定义层的开口与第一电连接部7连接，从而通过第一电连接部7连通公共阴极层9和第一电源线、第二电源线。其中，第一电连接部7可以与显示区域中的阳极独立设置，即不与其他阳极电连接，公共阴极层9可与显示区域中阴极为一整体结构。第一导电层中的其他部位还可以形成显示区域中薄膜晶体管的源漏层或电容的电极。在相关技术中，第一电连接部7可以与阵列基板的阳极同层成型，即通过一次构图工艺成型，第一电连接部7的结构材料与阳极的结构材料相同。相关技术中，阵列基板阳极层通常采用ITO层、Ag层、ITO层依次层叠设置的方式，然而，相关技术中阳极层的方块电阻较大，一般可以达到0.5Ω，因此，相关技术中，公共阴极层与电源线之间的电阻较大。As shown in FIGS. 1 and 2 , FIG. 1 is a top view of an array substrate in the related art, and FIG. 2 is a cross-sectional view of the array substrate in FIG. 1 along the dotted line A-A. The array substrate includes a
基于此，本示例性实施例提供一种阵列基板，如图3-6所示，图3为本公开阵列基板一种示例性实施例中的俯视图，图4为图3中阵列基板沿虚线A-A的剖视图；图5-6为本公开阵列基板一种示例性实施例中部分层级的结构示意图。该阵列基板包括边框区域和显示区域03，所述边框区域包括：位于所述显示区域03一侧的第一集成区01、位于所述第一集成区01远离所述显示区03一侧的第二集成区02，所述第一集成区01用于集成栅极驱动电路，所述阵列基板还包括：衬底基板1、第一导电层、第一平坦层3、第二导电层、像素定义层5、公共阴极层6。第一导电层位于所述衬底基板1的一侧，包括位于所述第二集成区02的第一导电部21；第一平坦层3位于所述第一导电层背离所述衬底基板1的一侧，所述第一平坦层3上设置有第一开口71，所述第一开口71在所述衬底基板1的正投影位于所述第一导电部21在所述衬底基板1的正投影上；第二导电层位于所述第一平坦层3背离所述衬底基板1的一侧，包括第二导电部41，部分所述第二导电部41可以位于第一集成区，部分所述第二导电部41可以位于第二集成区，所述第二导电部41覆盖所述第一开口，以通过所述第一开口与所述第一导电部电31连接；像素定义层5位于所述第二导电层背离所述衬底基板1的一侧，所述像素定义层5形成有位于所述第一集成区01的第二开口72，所述第二开口72在所述衬底基板1的正投影位于所述第二导电部41在所述衬底基板1的正投影上；公共阴极层6位于所述像素定义层5背离所述衬底基板1的一侧，覆盖所述第二开口，且通过所述第二开口与所述第二导电部41电连接。Based on this, this exemplary embodiment provides an array substrate, as shown in FIGS. 3-6 , FIG. 3 is a top view of an exemplary embodiment of the array substrate of the disclosure, and FIG. 4 is the array substrate in FIG. 3 along the dotted line A-A 5-6 are schematic structural diagrams of some levels in an exemplary embodiment of the disclosed array substrate. The array substrate includes a frame area and a
如图4所示，相比于相关技术，本示例性实施例提供的阵列基板中，阵列基板在边框区域没有设置位于阳极层第一电连接部7。第二导电部41跨越第一集成区直接与公共阴极层6连接。第二导电部41可以采用方块电阻较小的材料形成，例如，第二导电部可以采用金属Ti层、金属Al层、金属Ti层依次层叠设置的结构。该阵列基板减小了公共阴极层6与第一导电部、第二导电部之间的电阻。此外，相关技术中，阳极层中的Ag通常会发生被水汽氧化的现象，从而产生向显示区域漏气的通道，本示例性实施例，在边框区域没有设置阳极层，从而避免了上述技术问题。应该理解的是，第二导电部还可以由其他金属材料形成。As shown in FIG. 4 , compared with the related art, in the array substrate provided by the present exemplary embodiment, the array substrate is not provided with the first electrical connection portion 7 located on the anode layer in the frame area. The second
本示例性实施例中，如图4所示，该阵列基板还可以包括电路层10、封装层9。电路层可以位于衬底基板1和第一导电层之间，电路层10可以包括用于形成阵列基板中薄膜晶体管的有源层、栅极绝缘层、栅极层。封装层9可以设置于公共阴极层背离衬底基板的一侧。In this exemplary embodiment, as shown in FIG. 4 , the array substrate may further include a
本示例性实施例中，如图3、5、6所示，所述第一导电部21可以沿其所在边框区的边沿延伸方向X延伸，所述第一开口71可以沿其所在边框区的边沿延伸方向X延伸；所述第二导电部41可以沿其所在边框区的边沿延伸方向X延伸，所述第二开口72可以沿其所在边框区的边沿延伸方向延伸。第一导电部21和所述第二导电部41形成并联结构，从而减小了第一导电部21和所述第二导电部41形成的电源线的电阻。第二导电部41与公共阴极层6的实际接触面积为第二开口72的面积，本示例性实施例将第二开口72设置为条形可以极大的增加第二导电部41与公共阴极层6之间的电阻，从而减小公共阴极层6与外部电源之间的方块电阻。In this exemplary embodiment, as shown in FIGS. 3 , 5 and 6 , the first
本示例性实施例中，第二导电部41需要跨越第一集成区直接与公共阴极层6连接。由于第一集成区集成有栅极驱动电路。因此，第二导电部41在衬底基板的正投影会与栅极驱动电路在衬底基板上的正投影部分重合，第二导电部41会与栅极驱动电路中的部分结构形成电容结构，从而对栅极驱动电路中部分结构的电位产生影响。In this exemplary embodiment, the second
本示例性实施例中，如图3、5所示，所述第一平坦层的位于所述第一开口面向第一集成区一侧的厚度可以大于所述第一开口面向第二集成区一侧的厚度。即通过增加所述第一平坦层的位于所述第一开口面向第一集成区一侧的厚度，减小第二导体部41与栅极驱动电路部分结构形成电容的电容值，从而减弱第二导电部41对栅极驱动电路中部分结构电位的影响。其中，所述第一平坦层的位于所述第一开口面向第一集成区一侧的厚度可以为3um，所述第一平坦层的位于所述第一开口面向第二集成区一侧的厚度可以为1.5-2um。In this exemplary embodiment, as shown in FIGS. 3 and 5 , the thickness of the first flat layer on the side of the first opening facing the first integration region may be greater than the thickness of the first opening facing the second integration region side thickness. That is, by increasing the thickness of the first flat layer on the side of the first opening facing the first integrated region, the capacitance value of the capacitor formed by the
本示例性实施例中，所述阵列基板还可以包括薄膜晶体管。部分所述第一导电层还可以用于形成所述薄膜晶体管的源漏部。例如，如图7所示，为本公开阵列基板另一种示例性实施例中的结构示意图。该阵列基板中栅极驱动电路可以包括用于向像素驱动电路提供使能信号的EM GOA和用于向像素驱动电路提供栅极驱动信号的Gate GOA。第一导电层还可以包括第三导电部22、第四导电部23。第三导电部22可以作为EM GOA中薄膜晶体管的源漏极；第四导电部23可以作为Gate GOA中薄膜晶体管的源漏极。同时，第一导电层还可以包括第五导电部24，第五导电部24可以为用作向像素驱动电路提供初始信号的信号线。此外，部分第一导电层还可以用于形成阵列基板中电容的电极。In this exemplary embodiment, the array substrate may further include thin film transistors. Part of the first conductive layer may also be used to form the source and drain parts of the thin film transistor. For example, as shown in FIG. 7 , it is a schematic structural diagram of another exemplary embodiment of the array substrate of the present disclosure. The gate driving circuit in the array substrate may include an EM GOA for providing an enable signal to the pixel driving circuit and a Gate GOA for providing a gate driving signal to the pixel driving circuit. The first conductive layer may further include a third
本示例性实施例中，所述阵列基板还可以包括信号线，部分所述第二导电层还可以用于形成所述信号线。该信号线可以为显示区中的电源线、数据线、感测信号线、该信号线还可以为栅极驱动电路中的时钟信号线、初始化信号线等。In this exemplary embodiment, the array substrate may further include signal lines, and part of the second conductive layer may also be used to form the signal lines. The signal line may be a power supply line, a data line, or a sensing signal line in the display area, and the signal line may also be a clock signal line, an initialization signal line, or the like in the gate driving circuit.
本示例性实施例中，阵列基板的显示区域包括有阳极层，由于部分第二导电层可以在显示区用作信号线，则第二导电部背离衬底基板的一侧必然需要设置第二平坦层以隔离第二导电部和阳极层。如图7所示，所述阵列基板还可以包括第二平坦层，第二平坦层可以设置于所述第二导电层和阳极层之间，其中，阳极层可以设置于第二导电层和像素定义层之间。所述第二平坦层可以包括条形的第一平坦部81，所述第一平坦部81在所述衬底基板的正投影位于所述第一开口在所述衬底基板1的正投影上，且沿所述第一开口的延伸方向延伸。像素定义层5还可以包括位于第一平坦部81背离衬底基板的一侧的子像素定义层51。子像素定义层51在衬底基板的正投影可以位于第一平坦部81在衬底基板的正投影上。该阵列基板形成封装层9后，该第一平坦部81、子像素定义层51可以形成阻挡坝，以阻挡外部水汽进入阵列基板内部。In this exemplary embodiment, the display area of the array substrate includes an anode layer. Since part of the second conductive layer can be used as a signal line in the display area, a second flat surface must be provided on the side of the second conductive portion away from the base substrate. layer to isolate the second conductive portion and the anode layer. As shown in FIG. 7 , the array substrate may further include a second flat layer, and the second flat layer may be disposed between the second conductive layer and the anode layer, wherein the anode layer may be disposed between the second conductive layer and the pixel between layers. The second flat layer may include a strip-shaped first
本示例性实施例中，阵列基板在封装工艺中，需要在高温下进行，在高温环境下，第一平坦层中的气体发生热膨胀，从而可能在第二导电部上形成鼓包，或损坏第二导电部。本示例性实施例中，覆盖于所述第一平坦层上的所述第二导电部上设置有通气孔。该通气孔可以贯穿第二导电部，从而释放第一平坦层中的气体。In this exemplary embodiment, in the packaging process of the array substrate, it needs to be carried out at a high temperature. In a high temperature environment, the gas in the first flat layer thermally expands, so that a bulge may be formed on the second conductive part, or the second conductive part may be damaged. Conductive part. In this exemplary embodiment, the second conductive portion covering the first flat layer is provided with a vent hole. The vent hole may penetrate through the second conductive portion, thereby releasing the gas in the first flat layer.
本示例性实施例还提供一种阵列基板制作方法，所述阵列基板包括边框区域和显示区域，所述边框区域包括：位于所述显示区域一侧的第一集成区、位于所述第一集成区远离所述显示区一侧的第二集成区，所述第一集成区用于集成栅极驱动电，所述阵列基板制作方法包括：The present exemplary embodiment also provides a method for fabricating an array substrate. The array substrate includes a frame area and a display area, and the frame area includes: a first integration area located on one side of the display area, a first integrated area located on one side of the display area, and a The second integration region on the side away from the display region, the first integration region is used for integrating gate driving power, and the fabrication method of the array substrate includes:
形成衬底基板；forming a base substrate;
在所述衬底基板的一侧形成第一导电层，所述第一导电层包括位于所述第二集成区的第一导电部；A first conductive layer is formed on one side of the base substrate, the first conductive layer includes a first conductive portion located in the second integrated region;
在所述第一导电层背离所述衬底基板的一侧形成第一平坦层，所述第一平坦层上设置有第一开口，所述第一开口在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上；A first flat layer is formed on the side of the first conductive layer away from the base substrate, a first opening is provided on the first flat layer, and the first opening is located at the orthographic projection of the base substrate the first conductive portion is on the orthographic projection of the base substrate;
在所述第一平坦层背离所述衬底基板的一侧形成第二导电层，所述第二导电层包括第二导电部，所述第二导电部覆盖所述第一开口，以通过所述第一开口与所述第一导电部电连接；A second conductive layer is formed on a side of the first flat layer away from the base substrate, the second conductive layer includes a second conductive portion, and the second conductive portion covers the first opening to pass through the first opening. the first opening is electrically connected to the first conductive part;
在所述第二导电层背离所述衬底基板的一侧形成像素定义层，所述像素定义层形成有位于所述第一集成区的第二开口，所述第二开口在所述衬底基板的正投影位于所述第二导电部在所述衬底基板的正投影上；A pixel definition layer is formed on the side of the second conductive layer away from the base substrate, the pixel definition layer is formed with a second opening located in the first integration region, and the second opening is located in the substrate The orthographic projection of the substrate is located on the orthographic projection of the second conductive portion on the base substrate;
在所述像素定义层背离所述衬底基板的一侧形成公共阴极层，所述公共阴极层覆盖所述第二开口，且通过所述第二开口与所述第二导电部电连接。A common cathode layer is formed on a side of the pixel definition layer away from the base substrate, the common cathode layer covers the second opening, and is electrically connected to the second conductive portion through the second opening.
本示例性实施例中，在形成所述像素定义层之前还包括：In this exemplary embodiment, before forming the pixel definition layer, the method further includes:
在所述第二导电层背离所述衬底基板一侧形成所述第二平坦层，所述第二平坦层包括条形的第一平坦部，所述第一平坦部在所述衬底基板的正投影位于所述第一开口在所述衬底基板的正投影上。The second flat layer is formed on the side of the second conductive layer away from the base substrate, the second flat layer includes a strip-shaped first flat portion, and the first flat portion is on the base substrate The orthographic projection of the first opening is on the orthographic projection of the base substrate.
本示例性实施例中，在形成所述像素定义层之前还包括：In this exemplary embodiment, before forming the pixel definition layer, the method further includes:
在第二平坦层背离衬底基板一侧形成阳极层，其中可以通过湿刻工艺将边框区域的阳极层刻蚀掉。An anode layer is formed on the side of the second flat layer away from the base substrate, wherein the anode layer in the frame area can be etched away by a wet etching process.
本示例性实施例中，在所述第一导电层背离所述衬底基板的一侧形成第一平坦层，可以包括通过半色调掩膜工艺形成第一平坦层，以使所述第一平坦层的位于所述第一开口面向第一集成区一侧的厚度可以大于所述第一开口面向第二集成区一侧的厚度。In this exemplary embodiment, forming the first planarization layer on the side of the first conductive layer away from the base substrate may include forming the first planarization layer through a halftone mask process, so as to make the first planarization layer The thickness of the layer on the side of the first opening facing the first integration region may be greater than the thickness of the first opening facing the second integration region.
本示例性实施例中，在所述衬底基板的一侧形成第一导电层前，还可以包括在衬底基板上形成上述的电路层。In this exemplary embodiment, before forming the first conductive layer on one side of the base substrate, it may further include forming the above-mentioned circuit layer on the base substrate.
本示例性实施例中，在所述像素定义层背离所述衬底基板的一侧形成公共阴极层前，还可以包括：In this exemplary embodiment, before the common cathode layer is formed on the side of the pixel definition layer away from the base substrate, the method may further include:
在像素定义层上形成支撑掩膜版的支撑柱，在阵列基板的显示区域形成发光单元。A support column for supporting the mask is formed on the pixel definition layer, and a light-emitting unit is formed in the display area of the array substrate.
本示例性实施例中，形成公共阴极层后，还可以包括在公共阴极层背离衬底基板的一侧形成封装层、玻璃盖板等。In this exemplary embodiment, after forming the common cathode layer, it may further include forming an encapsulation layer, a glass cover plate, etc. on the side of the common cathode layer away from the base substrate.
本示例性实施例还提供一种显示装置，该显示装置包括上述的阵列基板。该显示装置可以为电视、手机、平板电脑等显示装置。The present exemplary embodiment also provides a display device including the above-mentioned array substrate. The display device may be a display device such as a TV, a mobile phone, and a tablet computer.
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性远离并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。Other embodiments of the present disclosure will readily suggest themselves to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the generality of the present disclosure away from and include common general knowledge or techniques in the art not disclosed by the present disclosure . The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the disclosure being indicated by the claims.
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。It is to be understood that the present disclosure is not limited to the precise structures described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
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