Liquid crystal display chipTechnical Field
The invention belongs to the technical field of display chips, and particularly relates to a liquid crystal display chip.
Background
The existing HDMI/VGA display interfaces all have display data channel interfaces (DDCCI), but all belong to the communication design of unidirectional reading and very small bandwidth (105200 bps). The liquid crystal display supporting the touch signal cannot integrate the signals on the same transmission line at the same interface and returns to the main control terminal, and a specific interface must be additionally provided, so that the design and product production cost are increased.
Therefore, it is necessary to develop a new liquid crystal display chip.
Disclosure of Invention
The invention aims to provide a liquid crystal display chip capable of supporting USB video signals.
The invention relates to a liquid crystal display chip, which comprises a video scaling circuit, an image processing circuit electrically connected with the video scaling circuit, a TVOUT circuit electrically connected with the image processing circuit, and a data corresponding table circuit electrically connected with the TVOUT circuit; the device comprises a first USB interface, a CPU bus, a RAW/JPEG format decoder, SRAM, DMA, CPU, a timer and a DDR2 memory interface;
the first USB interface, the RAW/JPEG format decoder, SRAM, DMA, CPU, the timer and the DDR2 memory interface are respectively and electrically connected with the CPU bus;
the first USB interface is used for receiving digital signal USB input video signals, storing related data in a DDR2 memory connected with the DDR2 memory interface through DMA, taking out the related data from the DDR2 memory through DMA according to a clock pulse required by each Frame of the video scaling circuit, decoding the related data into a correct image format, temporarily storing the data in a Frame buffer area through DMA, and inputting the decoded data to the video scaling circuit through DMA for processing;
Or the first USB interface is used for receiving a digital signal USB input video signal, temporarily storing related data in a DDR2 memory connected with the DDR2 memory interface through DMA, and then taking out the related data from the DDR2 memory through DMA according to the clock required by each frame of the video scaling circuit, decoding the related data into a correct image format and inputting the correct image format into the video scaling circuit for processing.
The system further comprises a TMDS RX PHY interface, an HDMI audio phase-locked loop and an HDMI digital logic circuit, wherein the TMDS RX PHY interface and the HDMI audio phase-locked loop are respectively and electrically connected with the HDMI digital logic circuit; the HDMI digital logic circuit is electrically connected with the input video signal switching interface;
The TMDS RX PHY interface is used for receiving the digital signal HDMI input video signal, and the digital signal HDMI logic circuit is used for sorting the digital signal HDMI input video signal and then transmitting the digital signal HDMI input video signal to the input video signal switching interface.
Further, the digital-to-analog converter further comprises an ADC_ B, ADC _ G, ADC _ R, SOG composite synchronous separator and an analog front-end digital logic circuit, wherein the ADC_ B, ADC _ G, ADC _ R, SOG composite synchronous separator is respectively and electrically connected with the analog front-end digital logic circuit; the analog front-end digital logic circuit is electrically connected with the input video signal switching interface;
the ADC_ R, ADC _G and the ADC_B are used for receiving VGA signals or Ypbpr signals, and are arranged through an analog front-end digital logic circuit and then are transmitted to an input video signal switching interface.
Further, the video scaling circuit comprises an image noise reduction module, a horizontal scaling module electrically connected with the image noise reduction module, an interleaving releasing module electrically connected with the horizontal scaling module, and a vertical video scaling module electrically connected with the interleaving releasing module;
The input video signal switching interface outputs data to the image noise reduction module, the image noise reduction module performs noise removal on characteristic points and then sends the characteristic points to the horizontal scaling module, the horizontal scaling module performs horizontal video scaling, if the characteristic points are Ypbpr signals, the interleaving canceling circuit solves the interleaving video display problem, and the vertical video scaling module performs vertical video scaling and sends the processed signals to the image processing circuit.
Further, the image processing circuit comprises a sharpness adjusting module, a chroma signal pressing module electrically connected with the sharpness adjusting module, an HSV chroma space axis color adjusting module electrically connected with the chroma signal pressing module, a black/white expanding module electrically connected with the HSV chroma space axis color adjusting module, a contrast adjusting module electrically connected with the black/white expanding module, a YUV-to-RGB matrix conversion module electrically connected with the contrast adjusting module, a red-green-blue 3x3 matrix module electrically connected with the YUV-to-RGB matrix conversion module, a color correction lookup table module electrically connected with the red-green-blue 3x3 matrix module, and a dithering operation module electrically connected with the color correction lookup table module;
The video scaling circuit is divided into two paths of data output paths after processing, one path is directly connected to the red, green and blue 3x3 matrix module, the other path is input to the red, green and blue 3x3 matrix module after passing through the sharpness adjustment module, the chrominance signal suppression module, the HSV chrominance space axis color adjustment module, the black/white expansion module, the contrast adjustment module and the YUV to RGB matrix conversion module to be converted into a data format ready to be output to a liquid crystal screen, and after overlapping color operation with the color correction lookup table module, the internal color operation bit is reduced to 8 bits of pixels suitable for output from 10 bits through the dithering operation module, and the internal color operation bit is input to the TVOUT circuit to be converted into the pixel format of the liquid crystal screen, converted into the LVDS format through the data correspondence table circuit and output, thus video output is completed; the sound signal is output to an external sound power amplifier component by the I2S format.
Further, a ROM is also included that is electrically connected to the CPU bus.
Further, the system also comprises a font screen display module electrically connected with the CPU bus.
Further, the device also comprises an ADC interface and a key, wherein the ADC interface and the key are electrically connected with the CPU bus, and the ADC interface is electrically connected with the key.
Further, the system also comprises a GPIO interface, a VIC interface, an I2C/UART interface and an SPI interface which are respectively and electrically connected with the CPU bus.
Further, the touch screen also comprises a second USB interface which is respectively and electrically connected with the CPU bus and is used for being connected with the touch screen, touch control signals of the touch screen are transmitted into the chip through the second USB interface or the I2C/UART interface or the SPI interface, and after being processed by the CPU in the chip, the touch control signals are transmitted back to the signal source main control end from the first USB interface for back control.
The invention has the following advantages: the USB interface is additionally arranged to enable the mobile phone, the desktop computer, the notebook computer and the television box to copy or expand desktop display of pictures displayed by terminal equipment such as the mobile phone, the desktop computer, the notebook computer and the television box after being connected to the liquid crystal display chip through the USB interface and the driving program. Besides video and sound display, the touch control signal is supported to be reversely controlled through the USB interface, and the problem that the touch control signal cannot return to a signal source main control end (the signal source main control end refers to video source equipment such as a mobile phone, a desktop computer and a notebook computer) through the HDMI/VGA interface is solved. Meanwhile, the invention is also provided with HDMI and VGA display interfaces, and video data can be input and displayed through the HDMI and VGA display interfaces. The invention reduces the design and product production cost and increases the universality of the product.
Drawings
FIG. 1 is a schematic block diagram of the present embodiment;
FIG. 2 is a schematic diagram of a circuit path of an internal USB video display circuit of a chip according to an embodiment;
FIG. 3 is a second schematic diagram of the internal USB video display circuit path of the chip in the present embodiment;
FIG. 4 is a schematic diagram showing the reverse control of the touch signal through the USB interface in the present embodiment;
In the figure: 1. the first USB interface, 2, CPU bus, 3, ADC interface, 4, button, 5, SPI interface, 6, I2C/UART interface, 7, second USB interface, 8, GPIO interface, 9, VIC interface, 10, DDR2 memory interface, 11, RAW/JPEG format decoder, 12, SRAM,13, DMA,14, CPU,15, ROM,16, font screen display module, 17, timer, 18, SOG composite synchronous separator, 19, ADC_R,20, ADC_G,21, ADC_B,22, HDMI audio phase-locked loop, 23, TMDS RX PHY interface, 24, HDMI digital logic circuit, 25, input video signal switching interface, 26, video scaling circuit, 27, image processing circuit, 28, data mapping table circuit, 29, TVOUT circuit;
the dashed lines in fig. 2 to 3 represent the flow direction of the signals.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, in the present embodiment, a liquid crystal display chip includes a video scaling circuit 26, an image processing circuit 27 electrically connected to the video scaling circuit 26, a TVOUT circuit 29 electrically connected to the image processing circuit 27, and a data correspondence table circuit 28 electrically connected to the TVOUT circuit 29. The liquid crystal display chip further comprises a first USB interface 1, a CPU bus 2, a RAW/JPEG format decoder 11, an SRAM (i.e. static random access memory) 12, a DMA13 (i.e. memory accessor), a CPU (i.e. central processing unit) 14, a timer 17 and a DDR2 (random access memory) memory interface. The first USB interface 1, the RAW/JPEG format decoder 11, the SRAM12, the DMA13, the CPU14, the timer 17, and the DDR2 memory interface 10 are electrically connected to the CPU bus 2, respectively.
The working principle is as follows:
Referring to fig. 3, the first USB interface 1 is configured to receive a digital USB input video signal, store related data in a DDR2 memory connected to the DDR2 memory interface 10 through a DMA13, decode the related data into a correct image format after being fetched from the DDR2 memory through the DMA13 according to a clock required by each Frame of the video scaling circuit 26, store the data in the Frame buffer through the DMA13, and input the decoded data to the video scaling circuit 26 for processing through the DMA 13.
Referring to fig. 2, or the first USB interface 1 is configured to receive a digital signal USB input video signal, store related data in a DDR2 memory connected to the DDR2 memory interface 10 through a DMA13, and the RAW/JPEG format decoder 11 decodes the related data into a correct image format after taking out the related data from the DDR2 memory through the DMA13 according to a clock required by each frame of the video scaling circuit 26, and inputs the decoded data to the video scaling circuit 26 for processing; the DDR bandwidth can be greatly saved.
After the mobile phone, the desktop computer and the notebook computer are connected to the liquid crystal display chip through the USB interface and the driving program, pictures displayed on the mobile phone, the desktop computer and the notebook computer can be copied or desktop display can be expanded.
Referring to fig. 1, in this embodiment, the liquid crystal display chip further includes a TMDS (minimized transmission differential signal) RX (receive) PHY (i.e. port physical layer) interface 23, an HDMI audio phase-locked loop 22, and an HDMI digital logic circuit 24, where the TMDSRX PHY interface 23 and the HDMI audio phase-locked loop 22 are electrically connected to the HDMI digital logic circuit 24, and the HDMI digital logic circuit 24 is electrically connected to the input video signal switching interface 25. The TMDS RX PHY interface 23 is configured to receive a digital signal HDMI input video signal, and is configured by an HDMI digital logic circuit and then sent to an input video signal switching interface.
Referring to fig. 1, in this embodiment, the liquid crystal display chip further includes adc_b21 (ADC means analog-to-digital converter, B means blue), adc_g20 (ADC means analog-to-digital converter, G means green), adc_r19 (ADC means analog-to-digital converter, R means red), SOG composite synchronous separator 18 and analog front-end digital logic circuit 30, where the adc_ B, ADC _g20, adc_r19 and SOG composite synchronous separator 18 are electrically connected to the analog front-end digital logic circuit 30, respectively; the analog front-end digital logic circuit 30 is electrically connected to the input video signal switching interface 25. The adc_r19, adc_g20 and adc_b21 are configured to receive VGA signals or Ypbpr signals, and are processed by the analog front-end digital logic circuit 30 and then sent to the input video signal switching interface.
Referring to fig. 1, in the present embodiment, the input video signal switching interface 25 is automatically judged by the system or the video signal selected by the user is selected by VGA, HDMI or USB, and the input video signal is switched to the video scaling circuit 26 and the image processing circuit 27 by the present circuit.
Referring to fig. 1, in this embodiment, the video scaling circuit 26 includes an image noise reduction module, a horizontal scaling module electrically connected to the image noise reduction module, a de-interlacing module electrically connected to the horizontal scaling module, and a vertical video scaling module electrically connected to the de-interlacing module. The input video signal switching interface 25 outputs data to the image noise reduction module, the image noise reduction module performs noise removal on the characteristic points and then sends the data to the horizontal scaling module, the horizontal scaling module performs horizontal video scaling on 1920 points of maximum amplified pixels (pixels), if Ypbpr signals are detected, the interlaced video display problem is solved by the interlacing canceling circuit, then the vertical video scaling module performs vertical video scaling processing and sends the processed signals to the image processing circuit 27, and 1080 points of maximum amplified pixels are detected.
Referring to fig. 1, in this embodiment, the image processing circuit 27 includes a sharpness adjustment module, a chrominance signal suppression module electrically connected to the sharpness adjustment module, an HSV chrominance space axis color adjustment module electrically connected to the chrominance signal suppression module, a black/white expansion module electrically connected to the HSV chrominance space axis color adjustment module, a contrast adjustment module electrically connected to the black/white expansion module, a YUV-to-RGB matrix conversion module electrically connected to the contrast adjustment module, a red green blue 3x3 matrix module electrically connected to the YUV-to-RGB matrix conversion module, a color correction look-up table module electrically connected to the red green blue 3x3 matrix module, and a dithering operation module electrically connected to the color correction look-up table module. The video scaling circuit 26 is divided into two paths of data output paths after processing, one path is directly connected to the red, green and blue 3x3 matrix module, and the other path is input to the red, green and blue 3x3 matrix module to be converted into a data format ready to be output to a liquid crystal screen after passing through the sharpness adjustment module, the chrominance signal suppression module, the HSV chrominance space axis color adjustment module, the black/white expansion module, the contrast adjustment module and the YUV to RGB matrix conversion module, and after overlapping color operation with the color correction lookup table module, the internal color operation bit is reduced from 10 bits to 8 bits of pixels suitable for output through the dithering operation module, and is input to the TVOUT circuit to be converted into a liquid crystal screen pixel format, converted into an LVDS format through the data correspondence table circuit 28 and output, thus completing video output; the sound signal is output to an external sound power amplifier component by the I2S format.
Referring to fig. 1, in the present embodiment, the liquid crystal display chip is shown further including a ROM15 electrically connected to the CPU bus 2.
Referring to fig. 1, in the present embodiment, the liquid crystal display chip is shown further including a font screen display module 16 electrically connected to the CPU bus 2. The font screen display module is an interactive interface storage buffer zone with a user, the user obtains an LCD parameter adjustment target of the user through a key, an I2C/UART interface, a second USB interface and a GPIO interface, and the user feeds back an operation result of the user through characters, a scroll bar and the like while executing the adjustment target.
Referring to fig. 1, in the present embodiment, the liquid crystal display chip is shown further including an ADC interface (analog-to-digital converter interface) 3 and a key 4 electrically connected to the CPU bus 2, the ADC interface 3 being electrically connected to the key 4. The ADC interface 3 and the key 4 correspond the ADC-converted data to a key list.
Referring to fig. 1, in the present embodiment, the liquid crystal display chip further includes a GPIO interface 8, a VIC interface 9, an I2C/UART interface 6, and an SPI interface 5, which are electrically connected to the CPU bus 2, respectively; multiple interfaces are provided for accessing devices of different interfaces.
As shown in fig. 1 and fig. 4, in this embodiment, the liquid crystal display chip further includes a second USB interface 7 electrically connected to the CPU bus 2, where the second USB interface 7 is used to connect to a touch screen, and a touch signal of the touch screen is transmitted into the chip through the second USB interface 7 or the I2C/UART interface 6 or the SPI interface 5, and after being processed by the CPU14 in the chip, the touch signal is transmitted back from the first USB interface to a signal source main control end (the signal source main control end refers to a mobile phone, a desktop computer, a notebook computer, and other video source devices) for performing back control.
In fig. 1, BAIN represents a blue analog input; PB1 represents a blue progressive signal; GAIN represents the green analog input; y1 represents a luminance signal; RAIN represents the red analog input, PR1 represents the red progressive signal; SOG means adding Sync signal to the G of RGB in the VGA signal; SOY1 represents adding a Sync signal to the luminance signal; HDMI IN represents HDMI signal input; SAR AIN represents the input of an analog signal to a successive approximation analog-to-digital converter.