CN111522387A - Voltage synchronization control circuit and voltage reading control system comprising same - Google Patents

Abstract

Translated fromChinese

本发明揭露一种电压同步控制电路及包含其的电压读取控制系统，包含读取起始脉冲检测模块、第一位组读取完成脉冲检测模块、第二位组读取完成脉冲检测模块、读取信号运算模块、旗标模块及更新控制模块。读取起始脉冲检测模块产生第一输出信号。第一位组读取完成脉冲检测模块产生第一位组读取完成旗标信号。第二位组读取完成脉冲检测模块产生第二位组读取完成旗标信号。读取信号运算模块产生读取起始脉冲信号及读取完成旗标信号。旗标模块产生保留旗标信号。更新控制模块产生第三输出信号及第四输出信号。

The invention discloses a voltage synchronization control circuit and a voltage reading control system including the same, including a reading start pulse detection module, a first bit group reading completion pulse detection module, a second bit group reading completion pulse detection module, Read signal operation module, flag module and update control module. The read start pulse detection module generates a first output signal. The first bit group reading completion pulse detection module generates the first bit group reading completion flag signal. The second byte read completion pulse detection module generates a second byte read completion flag signal. The read signal operation module generates a read start pulse signal and a read completion flag signal. The flag module generates a reserved flag signal. The update control module generates a third output signal and a fourth output signal.

Description

Translated fromChinese

电压同步控制电路及包含其的电压读取控制系统Voltage synchronization control circuit and voltage reading control system including the same

技术领域technical field

本发明是有关于一种控制电路及包含其的控制系统，特别是有关于一种电压同步控制电路及包含其的电压读取控制系统。The present invention relates to a control circuit and a control system including the same, in particular to a voltage synchronous control circuit and a voltage reading control system including the same.

背景技术Background technique

在过去各种电子装置的沟通或连接都需要依照相对应的传输线，且在充电或供电上，也需要相对应的线材，所以随着时间的累积，科技的进步，线材以及供电配件会不断地更新以及淘汰，造成资源的浪费以及环保的问题，而USB-IF协会推出了一个将数据传输以及电力传输合为一体的规范，就是USB Type-C规格以及USB Power Delivery规范。为了符合这两项技术的规格，相对应的硬体规格也产生出来了，此类产品又分为两类USB-PDControllers和TCPC。In the past, communication or connection of various electronic devices required corresponding transmission lines, and corresponding cables were also required for charging or power supply. Therefore, with the accumulation of time and the advancement of technology, cables and power supply accessories will continue to be used. Updates and eliminations cause waste of resources and environmental problems. The USB-IF Association has launched a specification that integrates data transmission and power transmission, namely the USB Type-C specification and the USB Power Delivery specification. In order to meet the specifications of these two technologies, the corresponding hardware specifications have also been produced. Such products are divided into two categories: USB-PDControllers and TCPC.

以TCPC(Type-C Port Controller)基础实现含有USB Type-C及USB PD规格的系统上，会含有TCPM(Type-C Port Manager)和TCPC(Type-C Port Controller)两个区块，以及TCPCI(Type-C Port Controller Interface)介面。TCPM在系统上属于Master，PD中属于应用层，用来判断PD的资讯及处理所接收到的资讯；TCPC在系统上属于Slave，PD中属于实体层，用来传接PD数据的物理信号，但除了PD数据的处理，还会控制或判断Type-C实体端口上的信号。而TCPCI是使用I2C protocol，来当作两者之间的桥梁，I2C protocol具有可挂载多个Device的优点。A system that implements USB Type-C and USB PD specifications based on TCPC (Type-C Port Controller) will contain two blocks, TCPM (Type-C Port Manager) and TCPC (Type-C Port Controller), as well as TCPPCI (Type-C Port Controller Interface) interface. TCPM belongs to the Master on the system, and the PD belongs to the application layer, which is used to judge the information of the PD and process the received information; TCPC belongs to the Slave on the system, and the PD belongs to the entity layer, which is used to transmit the physical signal of the PD data. But in addition to the processing of PD data, it also controls or judges the signals on the Type-C physical port. The TCPCI uses the I2C protocol as a bridge between the two. The I2C protocol has the advantage of being able to mount multiple devices.

TCPC的硬体规格上会有许多暂存器，有分为状态、控制、封包传递、VBUS电压等暂存器类别，例如:POWER_STATUS、POWER_CONTROL、TRAMSMIT_BUFFER、RECEIVE_BUFFER、VBUS_VOLTAGE…等，暂存器是透过I2C Protocol做读取写入的动作。在TCPC系统应用上，TCPM与TCPC透过I2C做沟通，每次数据的沟通都是一方传送8位的数据后，另一方会回传一个ACK代表传输成功，若回传NACK代表失败。There are many registers on the hardware specifications of TCPC, which are divided into register categories such as status, control, packet transmission, and VBUS voltage, such as: POWER_STATUS, POWER_CONTROL, TRAMSMIT_BUFFER, RECEIVE_BUFFER, VBUS_VOLTAGE, etc. The registers are transparent Read and write actions through I2C Protocol. In the application of TCPC system, TCPM and TCPC communicate through I2C. Each data communication is that after one party transmits 8-bit data, the other party will return an ACK to indicate that the transmission is successful, and if it returns NACK, it means failure.

VBUS_VOLTAGE的数值代表着Type-C的VBUS电压大小，这个类比电压会透过ADC电路转成数位数值10位的数值。但因为TCPC硬体的暂存器宽度为8位，所以整笔数据会分别存放于两个暂存器，在此将它们分别命名为VBUS_VOL_HBYTE_REG及VBUS_VOL_LBYTE_REG，前面2个位存放于VBUS_VOL_HBYTE_REG，后面8个位存放于VBUS_VOL_LBYTE_REG，且随着VBUS电压的变化，会更新这两个暂存器的值。所以当TCPM要读取VBUS_VOLTAGE数据时，会先读取VBUS_VOL_LBYTE_REG，后读取VBUS_VOL_HBYTE_REG，当读取前面一个暂存器时，后面的暂存器有机会因为VBUS电压的变化而改变，使得读取到的数值与理想的数值不同步，使得读取的数据会有极大的误差，造成系统的错误。The value of VBUS_VOLTAGE represents the VBUS voltage of Type-C. This analog voltage will be converted into a 10-bit digital value through the ADC circuit. However, because the register width of the TCPC hardware is 8 bits, the entire data will be stored in two registers, which are named VBUS_VOL_HBYTE_REG and VBUS_VOL_LBYTE_REG respectively. The first 2 bits are stored in VBUS_VOL_HBYTE_REG, and the last 8 bits Bits are stored in VBUS_VOL_LBYTE_REG, and as the VBUS voltage changes, the values of these two registers are updated. Therefore, when TCPM wants to read VBUS_VOLTAGE data, it will read VBUS_VOL_LBYTE_REG first, and then read VBUS_VOL_HBYTE_REG. When reading the previous temporary register, the latter temporary register has the opportunity to change due to the change of VBUS voltage, so that the read The value of the data is not synchronized with the ideal value, so that the read data will have great errors, resulting in system errors.

发明内容SUMMARY OF THE INVENTION

有鉴于上述习知的问题，本发明的目的在于提供一种电压同步控制电路及包含其的电压读取控制系统，用以解决现有技术中所面临的问题。In view of the above-mentioned conventional problems, an object of the present invention is to provide a voltage synchronization control circuit and a voltage reading control system including the same, so as to solve the problems faced in the prior art.

上述目的，本发明揭露一种电压同步控制电路，包含读取起始脉冲检测模块、第一位组读取完成脉冲检测模块、第二位组读取完成脉冲检测模块、读取信号运算模块、旗标模块及更新控制模块。读取起始脉冲检测模块接收第一位组读取起始脉冲信号及第二位组读取起始脉冲信号，并且据以产生第一输出信号。第一位组读取完成脉冲检测模块接收第一位组读取完成脉冲信号，并且据以产生第一位组读取完成旗标信号。第二位组读取完成脉冲检测模块接收第二位组读取完成脉冲信号，并且据以产生第二位组读取完成旗标信号。读取信号运算模块连接读取起始脉冲检测模块、第一位组读取完成脉冲检测模块及第二位组读取完成脉冲检测模块，且接收第一输出信号、第一位组读取完成旗标信号、第二位组读取完成旗标信号及第一读取时限信号，并且据以产生读取起始脉冲信号及读取完成旗标信号。旗标模块连接读取信号运算模块，且接收读取起始脉冲信号及读取完成旗标信号，并且据以产生保留旗标信号。更新控制模块连接旗标模块，且接收保留旗标信号、量测结果信号、量测完成脉冲信号、第三输入信号及第四输入信号，并且产生第三输出信号及第四输出信号。For the above purpose, the present invention discloses a voltage synchronization control circuit, comprising a read start pulse detection module, a first bit group read completion pulse detection module, a second bit group read completion pulse detection module, a read signal operation module, Flag module and update control module. The read start pulse detection module receives the first bit group read start pulse signal and the second bit group read start pulse signal, and generates a first output signal accordingly. The first group reading completion pulse detection module receives the first group reading completion pulse signal, and generates the first group reading completion flag signal accordingly. The second-bit group reading completion pulse detection module receives the second-bit group reading completion pulse signal, and generates the second-bit group reading completion flag signal accordingly. The read signal operation module is connected to the read start pulse detection module, the first bit group read completion pulse detection module, and the second bit group read completion pulse detection module, and receives the first output signal and the first bit group is read. The flag signal, the second bit group read completion flag signal and the first read time limit signal are used to generate the read start pulse signal and the read completion flag signal. The flag module is connected to the read signal operation module, and receives the read start pulse signal and the read completion flag signal, and generates the reserved flag signal accordingly. The update control module is connected to the flag module, and receives the reserved flag signal, the measurement result signal, the measurement completion pulse signal, the third input signal and the fourth input signal, and generates a third output signal and a fourth output signal.

较佳地，读取起始脉冲检测模块包含第一或门，接收第一位组读取起始脉冲信号，以及接收第二位组读取起始脉冲信号，并且据以产生第一输出信号。Preferably, the read start pulse detection module includes a first OR gate, receives the first bit group read start pulse signal, and receives the second bit group read start pulse signal, and generates the first output signal accordingly. .

较佳地，第一位组读取完成脉冲检测模块包含第一多工器、第二多工器及第一正反器。第一多工器的输入端接收第一高电位，另一第一多工器的输入端接收第一位组读取完成旗标信号，以及第一选择输入端接收第一位组读取完成脉冲信号，并且据以产生第一多工器输出信号。第二多工器连接第一多工器，第二多工器的输入端接收第二低电位，另一第二多工器的输入端接收第一多工器输出信号，读取信号运算模块依据读取起始脉冲信号及第一读取时限信号产生第二输出信号，第二选择输入端接收第二输出信号，并且据以产生第二多工器输出信号。第一正反器连接第二多工器，且第一正反器接收第二多工器输出信号，并且据以产生第一位组读取完成旗标信号。Preferably, the first-bit group read completion pulse detection module includes a first multiplexer, a second multiplexer and a first flip-flop. The input terminal of the first multiplexer receives the first high level, the input terminal of the other first multiplexer receives the first-bit group reading completion flag signal, and the first selection input terminal receives the first-bit group reading-completed signal pulse signal, and generate the first multiplexer output signal accordingly. The second multiplexer is connected to the first multiplexer, the input terminal of the second multiplexer receives the second low potential, and the input terminal of the other second multiplexer receives the output signal of the first multiplexer, and reads the signal operation module The second output signal is generated according to the read start pulse signal and the first read time limit signal, and the second selection input terminal receives the second output signal and generates the second multiplexer output signal accordingly. The first flip-flop is connected to the second multiplexer, and the first flip-flop receives the output signal of the second multiplexer, and generates the first-bit group read completion flag signal accordingly.

较佳地，第二位组读取完成脉冲检测模块包含第三多工器、第四多工器及第二正反器。第三多工器的输入端接收第三高电位，另一第三多工器的输入端接收第二位组读取完成旗标信号，以及第三选择输入端接收第二位组读取完成脉冲信号，并且据以产生第三多工器输出信号。第四多工器连接第三多工器，第四多工器的输入端接收第四低电位，另一第四多工器的输入端接收第三多工器输出信号，读取信号运算模块依据读取起始脉冲信号及第一读取时限信号产生第二输出信号，第四选择输入端接收第二输出信号，并且据以产生第四多工器输出信号。第二正反器连接第四多工器，第二正反器接收第四多工器输出信号，并且据以产生第二位组读取完成旗标信号。Preferably, the second bit group read completion pulse detection module includes a third multiplexer, a fourth multiplexer and a second flip-flop. The input terminal of the third multiplexer receives the third high level, the input terminal of the other third multiplexer receives the second byte group read complete flag signal, and the third selection input terminal receives the second byte group read complete pulse signal, and generate the third multiplexer output signal accordingly. The fourth multiplexer is connected to the third multiplexer, the input terminal of the fourth multiplexer receives the fourth low potential, and the input terminal of the other fourth multiplexer receives the output signal of the third multiplexer, and reads the signal operation module The second output signal is generated according to the read start pulse signal and the first read time limit signal, and the fourth selection input terminal receives the second output signal and generates a fourth multiplexer output signal accordingly. The second flip-flop is connected to the fourth multiplexer, and the second flip-flop receives the output signal of the fourth multiplexer and generates the second bit group read completion flag signal accordingly.

较佳地，读取信号运算模块包含第一互斥或非门、第一与门、第二或门及第二与门。第一互斥或非门的输入端接收第一位组读取完成旗标信号，另一第一互斥或非门的输入端接收第二位组读取完成旗标信号，并且据以产生第一互斥或非门输出信号。第一与门连接第一互斥或非门，第一与门的输入端接收第一输出信号，另一第一与门的输入端接收第一互斥或非门输出信号，并且据以产生读取起始脉冲信号。第二或门连接第一与门，第二或门的输入端接收第一读取时限信号，另一第二或门的输入端接收读取起始脉冲信号，并且据以产生第二输出信号。第二与门，其第二与门的输入端接收第一位组读取完成旗标信号，另一第二与门的输入端接收第二位读取完成旗标信号，并且据以产生读取完成旗标信号。Preferably, the read signal operation module includes a first mutually exclusive NOR gate, a first AND gate, a second OR gate and a second AND gate. The input terminal of the first mutually exclusive NOR gate receives the first bit group read completion flag signal, and the input terminal of the other first mutually exclusive NOR gate receives the second bit group read completion flag signal, and generates accordingly. The first mutually exclusive NOR gate outputs a signal. The first AND gate is connected to the first mutually exclusive NOR gate, the input terminal of the first AND gate receives the first output signal, and the input terminal of the other first AND gate receives the first mutually exclusive NOR gate output signal, and generates accordingly. Read the start pulse signal. The second OR gate is connected to the first AND gate, the input terminal of the second OR gate receives the first read timing signal, and the input terminal of the other second OR gate receives the read start pulse signal, and generates a second output signal accordingly . The second AND gate, the input terminal of the second AND gate receives the first bit group read completion flag signal, and the input terminal of the other second AND gate receives the second bit read completion flag signal, and generates a read completion flag signal accordingly Fetch the completion flag signal.

较佳地，旗标模块包含第五多工器、第六多工器、第三正反器、第一时限计数器及第三或门。第五多工器的输入端接收第五高电位，另一第五多工器的输入端接收保留旗标信号，以及第五选择输入端接收读取起始脉冲信号，并且据以产生第五多工器输出信号。第六多工器连接第五多工器，第六多工器的输入端接收第六低电位，另一第六多工器的输入端接收第五多工器输出信号，以及第六选择输入端接收第五输出信号，并且据以产生第六多工器输出信号。第三正反器连接第六多工器，第三正反器接收第六多工器输出信号，并且据以产生保留旗标信号。第一时限计数器连接第三正反器，第一时限计数器接收保留旗标信号，并且据以产生第二读取时限信号。第三或门连接第一时限计数器及第六多工器，第三或门的输入端接收第二读取时限信号，另一第三或门的输入端接收读取完成旗标信号，并且据以产生第五输出信号。Preferably, the flag module includes a fifth multiplexer, a sixth multiplexer, a third flip-flop, a first timer counter and a third OR gate. The input terminal of the fifth multiplexer receives the fifth high potential, the input terminal of the other fifth multiplexer receives the reserved flag signal, and the fifth selection input terminal receives the read start pulse signal, and the fifth multiplexer is generated accordingly. Multiplexer output signal. The sixth multiplexer is connected to the fifth multiplexer, the input terminal of the sixth multiplexer receives the sixth low potential, the input terminal of the other sixth multiplexer receives the output signal of the fifth multiplexer, and the sixth selection input The terminal receives the fifth output signal and generates the sixth multiplexer output signal accordingly. The third flip-flop is connected to the sixth multiplexer, and the third flip-flop receives the output signal of the sixth multiplexer and generates a reserved flag signal accordingly. The first time limit counter is connected to the third flip-flop, and the first time limit counter receives the reserved flag signal and generates the second read time limit signal accordingly. The third OR gate is connected to the first time limit counter and the sixth multiplexer, the input end of the third OR gate receives the second read time limit signal, the input end of the other third OR gate receives the read completion flag signal, and according to the to generate a fifth output signal.

较佳地，更新控制模块包含第一蕴含非门、第七多工器及第八多工器。第一蕴含非门接的输入端接收量测完成脉冲信号，另一第一蕴含非门接的输入端接收保留旗标信号，并且据以产生更新脉冲信号。第七多工器连接第一蕴含非门，第七多工器的输入端接收量测结果信号，另一第七多工器的输入端接收第三输入信号，以及第七选择输入端接收更新脉冲信号，并且据以产生第三输出信号。以及第八多工器连接第一蕴含非门，第八多工器的输入端接收量测结果信号，另一第八多工器的输入端接收第四输入信号，以及第八选择输入端接收更新脉冲信号，并且据以产生第四输出信号。Preferably, the update control module includes a first implicated NOT gate, a seventh multiplexer and an eighth multiplexer. The first input terminal implicating the NOT gate receives the measurement completion pulse signal, and the other first input terminal implicating the NOT gate connection receives the reserved flag signal, and generates the update pulse signal accordingly. The seventh multiplexer is connected to the first implicated NOT gate, the input terminal of the seventh multiplexer receives the measurement result signal, the input terminal of the other seventh multiplexer receives the third input signal, and the seventh selection input terminal receives the update signal pulse signal, and generate a third output signal accordingly. and the eighth multiplexer is connected to the first implicated NOT gate, the input terminal of the eighth multiplexer receives the measurement result signal, the input terminal of the other eighth multiplexer receives the fourth input signal, and the eighth selection input terminal receives The pulse signal is updated, and a fourth output signal is generated accordingly.

较佳地，本发明也提供一种电压读取控制系统，其包含电压同步控制器、数据解析与传输模块、控制器模块、暂存器模块、组态逻辑模块及实体层与应用层模块。其中电压同步控制器，具有以上提及的电压同步控制电路，且接收第一位组读取起始脉冲信号、第一位组读取完成脉冲信号、第二位组读取起始脉冲信号、第二位组读取完成脉冲信号、量测结果信号及量测完成脉冲信号，并且据以产生第三输出信号及第四输出信号。数据解析与传输模块连接电压同步控制器，接收至少外部数据需求信号，据以产生第一位组读取起始脉冲信号、第一位组读取完成脉冲信号、第二位组读取起始脉冲信号及第二位组读取完成脉冲信号。控制器模块连接电压同步控制器，接收外部类比信号，且据以产生量测结果信号及量测完成脉冲信号。暂存器模块连接电压同步控制器、数据解析与传输模块及控制器模块，且接收第三输出信号及第四输出信号，暂存器模块储存第一位组数据及第二位组数据，并且据以产生第三输入信号及第四输入信号。组态逻辑模块连接暂存器模块，且实现使用者命令或检测外部连结状态。实体层与应用层模块连接暂存器模块。Preferably, the present invention also provides a voltage reading control system, which includes a voltage synchronization controller, a data analysis and transmission module, a controller module, a register module, a configuration logic module, and physical layer and application layer modules. The voltage synchronization controller has the above-mentioned voltage synchronization control circuit, and receives the first bit group reading start pulse signal, the first bit group reading completion pulse signal, the second bit group reading start pulse signal, The second bit group reads the completion pulse signal, the measurement result signal and the measurement completion pulse signal, and generates the third output signal and the fourth output signal accordingly. The data analysis and transmission module is connected to the voltage synchronization controller, and receives at least the external data demand signal, and generates the first-bit group reading start pulse signal, the first-bit group reading completion pulse signal, and the second-bit group reading start pulse signal. The pulse signal and the second bit group read completion pulse signal. The controller module is connected to the voltage synchronization controller, receives an external analog signal, and generates a measurement result signal and a measurement completion pulse signal accordingly. The register module is connected to the voltage synchronization controller, the data analysis and transmission module and the controller module, and receives the third output signal and the fourth output signal, the register module stores the first bit group data and the second bit group data, and Accordingly, the third input signal and the fourth input signal are generated. The configuration logic module is connected to the register module, and implements user commands or detects external connection status. The entity layer and the application layer module are connected to the register module.

较佳地，暂存器模块的第一位组数据产生第三输入信号。Preferably, the first set of data of the register module generates the third input signal.

较佳地，暂存器模块的第二位组数据产生第四输入信号。Preferably, the second group of data of the register module generates the fourth input signal.

承上所述，本发明的电压同步控制电路及包含其的电压读取控制系统具有以下优点：Based on the above, the voltage synchronization control circuit of the present invention and the voltage reading control system including the same have the following advantages:

1.当电压同步控制器接收到读取暂存器模块的第一位组数据时，利用电压同步控制电路的旗标模块产生保留旗标信号，且保留旗标信号的状态为high状态，避免第二位组数据被量测结果信号更新其数据状态。1. When the voltage synchronization controller receives the first group data of the read register module, it uses the flag module of the voltage synchronization control circuit to generate a reserved flag signal, and the state of the reserved flag signal is high to avoid The data state of the second group of data is updated by the measurement result signal.

2.利用电压同步控制电路的旗标模块内的第一时限计数器，当保留旗标信号的状态保持high状态超过一定时间间隔后，强制将保留旗标信号的状态强迫更改成low状态，让量测结果信号可以更新暂存器模块的第一位组及第二位组的数据状态，避免系统的问题。2. Using the first time limit counter in the flag module of the voltage synchronization control circuit, when the state of the reserved flag signal remains in the high state for more than a certain time interval, the state of the reserved flag signal is forcibly changed to the low state, so that the amount of The test result signal can update the data status of the first group and the second group of the register module to avoid system problems.

3.利用电压同步控制电路，暂存器模块的实际值与理想值不会有不同步的问题发生。3. Using the voltage synchronization control circuit, the actual value of the register module and the ideal value will not be out of synchronization.

附图说明Description of drawings

图1为本发明的电压同步控制电路的方块图。FIG. 1 is a block diagram of a voltage synchronization control circuit of the present invention.

图2为本发明的电压同步控制电路的第一电路图。FIG. 2 is a first circuit diagram of the voltage synchronization control circuit of the present invention.

图3为本发明的电压同步控制电路的第二电路图。FIG. 3 is a second circuit diagram of the voltage synchronization control circuit of the present invention.

图4为本发明的电压读取控制系统的方块图。FIG. 4 is a block diagram of the voltage reading control system of the present invention.

符号说明：Symbol Description:

1：第一或门1: first OR gate

2：第一多工器2: The first multiplexer

3：第二多工器3: Second Multiplexer

4：第一正反器4: The first flip-flop

5：第三多工器5: The third multiplexer

6：第四多工器6: Fourth Multiplexer

7：第二正反器7: The second flip-flop

8：第一互斥或非门8: The first mutually exclusive NOR gate

9：第一与门9: The first AND gate

10：第二或门10: Second OR gate

11：第二与门11: The second AND gate

12：第五多工器12: Fifth Multiplexer

13：第六多工器13: Sixth Multiplexer

14：第三正反器14: The third flip-flop

15：第一时限计数器15: First time limit counter

16：第三或门16: Third OR gate

17：第一蕴含非门17: The first implication NOT gate

18：第七多工器18: Seventh Multiplexer

19：第八多工器19: Eighth Multiplexer

100：读取起始脉冲检测模块100: Read start pulse detection module

101：第一位组读取完成脉冲检测模块101: The first group read completed pulse detection module

102：第二位组读取完成脉冲检测模块102: The second bit group read completed pulse detection module

103：读取信号运算模块103: Read signal operation module

104：旗标模块104: Flag Module

105：更新控制模块105: Update Control Module

106：电压同步控制器106: Voltage Synchronous Controller

107：数据解析与传输模块107: Data parsing and transmission module

108：控制器模块108: Controller module

109：暂存器模块109: Scratchpad module

110：组态逻辑模块110: Configure Logic Modules

111：实体层与应用层模块111: Entity layer and application layer modules

200：电压同步控制电路200: Voltage synchronization control circuit

300：电压读取控制系统300: Voltage reading control system

具体实施方式Detailed ways

为利了解本发明的特征、内容与优点及其所能达成的功效，兹将本发明配合图式，并以实施例的表达形式详细说明如下，而其中所使用的图式，其主旨仅为示意及辅助说明书的用，未必为本发明实施后的真实比例与精准配置，故不应就所附的图式的比例与配置关系解读、局限本发明于实际实施上的申请权利范围。In order to facilitate the understanding of the features, contents and advantages of the present invention and the effects that can be achieved, the present invention is hereby described in detail with the drawings and the expression form of the embodiments as follows, and the drawings used therein are only for the purpose of The schematic and auxiliary descriptions are not necessarily the real proportions and precise configurations after the implementation of the present invention. Therefore, the proportions and configuration relationships of the attached drawings should not be interpreted or limited to the scope of the application rights of the present invention in actual implementation.

本发明的优点、特征以及达到的技术方法将参照例示性实施例及所附图式进行更详细地描述而更容易理解，且本发明或可以不同形式来实现，故不应被理解仅限于此处所陈述的实施例，相反地，对本领域技术人员而言，所提供的实施例将使本发明更加透彻与全面且完整地传达本发明的范畴，且本发明将仅为所附加的权利要求所定义。The advantages, features, and technical methods of the present invention will be more easily understood by being described in more detail with reference to the exemplary embodiments and the accompanying drawings, and the present invention may be implemented in different forms, so it should not be construed as being limited thereto. Rather, the embodiments are set forth herein, rather, the embodiments are provided so as to fully convey the scope of the invention to those skilled in the art, and the scope of the invention will be fully and fully conveyed, and the invention will be limited only by the appended claims. definition.

请参阅图1，其为本发明的电压同步控制电路200的方块图。如图所示，其以功能划分本发明的电压同步控制电路200，且进一步分成六个模块，下述将描述各模块间的连接关系及信号的输入与输出。本发明的同步控制电路包含读取起始脉冲检测模块100、第一位组读取完成脉冲检测模块101、第二位组读取完成脉冲检测模块102、读取信号运算模块103、旗标模块104及更新控制模块105。其第一位组对应VBUS_VOLTAGE的低位组，第二位组对应VBUS_VOLTAGE的高位组，读取起始脉冲检测模块100接收第一位组读取起始脉冲信号及第二位组读取起始脉冲信号，并且藉由其内部逻辑元件产生第一输出信号，其第一输出信号对应的讯息为判断暂存器模块内的第一位组数据或第二位组数据的任一数据是否正在读取，若其任一数据正在读取，则第一输出信号为high状态(高位准状态)，否则为low状态(低位准状态)。第一位组读取完成脉冲检测模块101接收第一位组读取完成脉冲信号，并且据以产生第一位组读取完成旗标信号，其对应的讯息为，若是第一位组读取完成脉冲检测模块接收到状态为high(高位准)的第一位读取完成脉冲信号，代表低位组数据已被读出，藉由其内部逻辑元件运算，则得到状态为high的第一位组读取完成旗标信号，否则得到状态为low(低位准)的第一位组读取完成旗标信号。第二位组读取完成脉冲检测模块102接收第二位组读取完成脉冲信号，并且据以产生第二位组读取完成旗标信号，其对应的讯息为，若是第二位组读取完成脉冲检测模块接收到状态为high的第二位读取完成脉冲信号，代表高位组数据已被读出，藉由其内部逻辑元件运算，则得到状态为high的第二位组读取完成旗标信号，否则得到状态为low的第二位组读取完成旗标信号。读取信号运算模块103连接读取起始脉冲检测模块100、第一位组读取完成脉冲检测模块101及第二位组读取完成脉冲检测模块102，且接收第一输出信号、第一位组读取完成旗标信号、第二位组读取完成旗标信号及第一读取时限信号，并且据以产生读取起始脉冲信号及读取完成旗标信号，其对应的讯息为，若是低位组数据及高位组数据皆被读出，藉由内部逻辑元件运算，则得到状态为high的读取完成旗标信号，代表VBUS_VOLTAGE已被完整读出，否则得到状态为low的读取完成旗标信号。利用第一输出信号、第一位组读取完成旗标信号及第二位组读取完成旗标信号，藉由内部逻辑元件运算还能得到另一个讯息，若是低位组数据与高位组数据皆被完整读出或皆未被完整读出，且第一输出信号的状态代表低位组数据或高位组数据的中至少有一数据正在进行读取动作，则得到状态为high的读取起始脉冲信号，否则得到状态为low的读取起始脉冲信号。旗标模块104连接读取信号运算模块103，且接收读取起始脉冲信号及读取完成旗标信号，并且据以产生保留旗标信号，其对应的讯息为，若读取起始脉冲信号的状态为high，且读取完成旗标信号的状态为low时，则得到状态为high的保留旗标信号，否则得到状态为low的保留旗标信号，但是当保留旗标信号维持high的状态超过一定时间间隔，内部的逻辑元件将使其信号改变为low状态。更新控制模块105连接旗标模块104，且接收保留旗标信号、量测结果信号、量测完成脉冲信号、第三输入信号及第四输入信号，并且产生第三输出信号及第四输出信号，其对应的讯息为，若保留旗标信号的状态为high，则不论量测结果信号及量测完成脉冲信号为何，得到状态为low的第三输出信号及第四输出信号，代表低位组数据及高位组数据皆不会被量测结果信号写入。Please refer to FIG. 1 , which is a block diagram of the voltage synchronization control circuit 200 of the present invention. As shown in the figure, the voltage synchronization control circuit 200 of the present invention is divided by function, and is further divided into six modules. The following will describe the connection relationship between the modules and the input and output of signals. The synchronization control circuit of the present invention includes a read start pulse detection module 100, a first bit group read completion pulse detection module 101, a second bit group read completion pulse detection module 102, a read signal operation module 103, and a flag module 104 and update control module 105. The first bit group corresponds to the low-order group of VBUS_VOLTAGE, the second bit group corresponds to the high-order group of VBUS_VOLTAGE, and the read start pulse detection module 100 receives the read start pulse signal of the first bit group and the read start pulse of the second bit group signal, and generates a first output signal through its internal logic element, the message corresponding to the first output signal is to determine whether any data of the first group data or the second group data in the register module is being read , if any of its data is being read, the first output signal is in a high state (high level state), otherwise it is in a low state (low level state). The first group reading completion pulse detection module 101 receives the first group reading completion pulse signal, and generates the first group reading completion flag signal accordingly, and the corresponding message is, if the first group reading is completed The completion pulse detection module receives the first read completion pulse signal whose state is high (high level). The read completion flag signal is obtained, otherwise, the read completion flag signal of the first group whose state is low (low level) is obtained. The second-bit group reading completion pulse detection module 102 receives the second-bit group reading completion pulse signal, and generates the second-bit group reading completion flag signal accordingly, and the corresponding message is, if the second-bit group reading is completed The completion pulse detection module receives the second-bit read completion pulse signal whose state is high, which means that the high-order group data has been read out. Through its internal logic element operation, the second-bit group read completion flag whose state is high is obtained. The flag signal, otherwise, the read completion flag signal of the second bit group whose state is low is obtained. The read signal operation module 103 is connected to the read start pulse detection module 100, the first bit group read completion pulse detection module 101 and the second bit group read completion pulse detection module 102, and receives the first output signal, the first bit group The group read complete flag signal, the second group read complete flag signal, and the first read time limit signal are used to generate the read start pulse signal and the read complete flag signal. The corresponding messages are: If both the low-order group data and the high-order group data are read out, through the internal logic element operation, the read completion flag signal with the state of high will be obtained, which means that VBUS_VOLTAGE has been completely read out, otherwise, the read completion of the state of low will be obtained. flag signal. Using the first output signal, the read completion flag signal of the first bit group and the read completion flag signal of the second bit group, another message can be obtained through the operation of internal logic elements. It is completely read out or not completely read out, and the state of the first output signal represents that at least one data in the low-order group data or the high-order group data is being read, then a read start pulse signal with a high state is obtained , otherwise the read start pulse signal with the state of low is obtained. The flag module 104 is connected to the read signal operation module 103, and receives the read start pulse signal and the read completion flag signal, and generates a reserved flag signal accordingly. The corresponding message is, if the read start pulse signal When the status of the read completion flag signal is high, and the status of the read completion flag signal is low, the reserved flag signal with the status of high is obtained, otherwise the reserved flag signal with the status of low is obtained, but when the reserved flag signal maintains the high state After a certain time interval, the internal logic element will change its signal to the low state. The update control module 105 is connected to the flag module 104, and receives the reserved flag signal, the measurement result signal, the measurement completion pulse signal, the third input signal and the fourth input signal, and generates the third output signal and the fourth output signal, The corresponding message is, if the state of the reserved flag signal is high, no matter what the measurement result signal and the measurement completion pulse signal are, the third output signal and the fourth output signal whose state is low are obtained, representing the low-order group data and The high-order group data will not be written by the measurement result signal.

请参阅图2，其为电压同步控制电路200的第一电路图。如图所示，读取起始脉冲检测模块100内具有逻辑元件第一或门1，其两个输入端其中的一个输入端接收第一位组读取起始脉冲信号1_1，另一个输入端接收第二位组读取起始脉冲信号1_2，藉由第一或门1的运算特性，若是第一位组读取起始脉冲信号1_1或第二位组读取起始脉冲信号1_2的中，至少有一个的状态为high，则输出状态为high的第一输出信号，代表低位组数据或高位组数据至少有一个正在读取。Please refer to FIG. 2 , which is a first circuit diagram of the voltage synchronization control circuit 200 . As shown in the figure, the read start pulse detection module 100 has a logic element first ORgate 1, one of its two input terminals receives the first bit group read start pulse signal 1_1, and the other input terminal Receive the second bit group read start pulse signal 1_2, according to the operation characteristics of the first ORgate 1, if the first bit group read start pulse signal 1_1 or the second bit group read start pulse signal 1_2 , the state of at least one of them is high, then the first output signal whose state is high is output, indicating that at least one of the low-order group data or the high-order group data is being read.

续请参阅图2，第一位组读取完成脉冲检测模块101内，具有以下逻辑元件，第一多工器2、连接第一多工器的第二多工器3及连接第二多工器的第一正反器4。下文提到的多工器，皆为二个输入端搭配一个选择输入端的逻辑元件，第一多工器2其中一个输入端固定接收高电位(high状态)，另一个输入端接收第一正反器4输出信号，第一选择输入端则接收第一位组读取完成脉冲信号2_1，若是第一位组读取完成脉冲信号2_1为high状态，则第一多工器2输出信号为high状态。第二多工器3其中一个输入端固定接收低电位(low状态)，另一个输入端接收第一多工器2输出信号，第二选择输入端接收的信号，则是由上述读取信号运算模块103输出的读取起始脉冲信号9_1及其接收来自外部的第一读取时限信号10_1，利用读取信号运算模块103内部的逻辑元件产生第二输出信号。第二多工器3输出信号，若第二选择输入端的信号为状态high，则输出状态low。第一正反器4接收第二多工器3输出信号，产生第一位组读取完成其标信号。总结来说，第一位组读取完成脉冲检测模块101整体在运作时，其对应的信号变化为，当第一位组读取完成脉冲信号2_1接收到状态为high的信号，且读取信号运算模块103输出的读取起始脉冲信号9_1及其接收来自外部的第一读取时限信号10_1两者皆为状态low的信号时，第一位组读取完成旗标信号才会变为high状态，代表低位组数据已在时限内被完整读出，且尚未接收到另一个新的读取起始脉冲信号9_1。Continuing to refer to FIG. 2 , the first-bit group read completion pulse detection module 101 has the following logic elements: a first multiplexer 2 , a second multiplexer 3 connected to the first multiplexer, and a second multiplexer connected to the second multiplexer The first flip-flop 4 of the device. The multiplexers mentioned below are all logic elements with two input terminals and a selection input terminal. One input terminal of the first multiplexer 2 is fixed to receive a high potential (high state), and the other input terminal receives the first positive and negative. The first selection input terminal receives the first group reading completion pulse signal 2_1, if the first group reading completion pulse signal 2_1 is in the high state, the output signal of the first multiplexer 2 is in the high state . One of the input terminals of the second multiplexer 3 is fixed to receive a low potential (low state), the other input terminal receives the output signal of the first multiplexer 2, and the signal received by the second selection input terminal is calculated by the above read signal The read start pulse signal 9_1 output by the module 103 and the first read time limit signal 10_1 received from the outside are used to generate the second output signal by using the logic element inside the read signal operation module 103 . The second multiplexer 3 outputs a signal, and if the signal at the second selection input terminal is in a state of high, it outputs a state of low. The first flip-flop 4 receives the output signal of the second multiplexer 3, and generates a flag signal of the completion of reading the first bit group. To sum up, when the first group read completion pulse detection module 101 is operating as a whole, its corresponding signal change is, when the first group read completion pulse signal 2_1 receives a signal with a state of high, and the read signal When both the read start pulse signal 9_1 output by the operation module 103 and the first read time limit signal 10_1 received from the outside are in the low state, the first group read completion flag signal will become high. The state indicates that the low-order group data has been completely read out within the time limit, and another new read start pulse signal 9_1 has not been received.

第二位组读取完成脉冲检测模块102内，具有以下逻辑元件，第三多工器5、连接第三多工器的第四多工器6及连接第四多工器的第二正反器7。第三多工器5其中一个输入端固定接收高电位(high状态)，另一个输入端接收第二正反器7输出信号，第三选择输入端则接收第二位组读取完成脉冲信号，若是第二位组读取完成脉冲信号为high状态，则第三多工器5输出信号为high状态。第四多工器6其中一个输入端固定接收低电位(low状态)，另一个输入端接收第三多工器5输出信号，第四选择输入端接收的信号，则是由上述读取信号运算模块103输出的读取起始脉冲信号9_1及其接收来自外部的第一读取时限信号10_1，利用读取信号运算模块103内部的逻辑元件产生第二输出信号。第四多工器6输出信号，若第四选择输入端的信号为状态high，则输出状态low。第二正反器7接收第四多工器6输出信号，产生第二位组读取完成其标信号。总结来说，第二位组读取完成脉冲检测模块102整体在运作时，其对应的信号变化为，当第二位组读取完成脉冲信号接收到状态为high的信号，且读取信号运算模块103输出的读取起始脉冲信号9_1及其接收来自外部的第一读取时限信号10_1两者皆为状态low的信号时，第二位组读取完成旗标信号才会变为high状态，代表高位组数据已在时限内被完整读出，且尚未接收到另一个读取起始脉冲信号9_1。The second bit group read completion pulse detection module 102 has the following logic elements: a third multiplexer 5, a fourth multiplexer 6 connected to the third multiplexer, and a second positive and negative multiplexer connected to the fourth multiplexer device 7. One of the input terminals of the third multiplexer 5 is fixed to receive a high potential (high state), the other input terminal receives the output signal of the second flip-flop 7, and the third selection input terminal receives the second bit group reading completion pulse signal, If the read completion pulse signal of the second bit group is in the high state, the output signal of the third multiplexer 5 is in the high state. One of the input terminals of the fourth multiplexer 6 is fixed to receive a low potential (low state), the other input terminal receives the output signal of the third multiplexer 5, and the signal received by the fourth selection input terminal is calculated by the above-mentioned read signal. The read start pulse signal 9_1 output by the module 103 and the first read time limit signal 10_1 received from the outside are used to generate the second output signal by using the logic element inside the read signal operation module 103 . The fourth multiplexer 6 outputs a signal, and if the signal at the fourth selection input terminal is in a state of high, it outputs a state of low. The second flip-flop 7 receives the output signal of the fourth multiplexer 6 and generates a flag signal of the completion of reading the second bit group. To sum up, when the second-bit group read completion pulse detection module 102 is operating as a whole, the corresponding signal changes are: when the second-bit group read completion pulse signal receives a signal whose state is high, and the read signal operation When both the read start pulse signal 9_1 output by the module 103 and the first read time limit signal 10_1 received from the outside are in the low state, the second bit group read completion flag signal will become the high state. , indicating that the high-order group data has been completely read out within the time limit, and another read start pulse signal 9_1 has not been received.

读取信号运算模块103内，具有以下逻辑元件，第一互斥或非门8(NXOR)、连接第一互斥或非门8(NXOR)的第一与门9、连接第一与门9的第二或门10及第二与门11。第一互斥或非门8(NXOR)其中一个输入端接收来自上述第一位组读取完成脉冲检测模块101的第一位组读取完成旗标信号，第一互斥或非门8(NXOR)另一个输入端接收来自上述第二位组读取完成脉冲检测模块102的第二位组读取完成旗标信号，且产生第一互斥或非门8(NXOR)输出信号，若第一位组读取完成旗标信号及第二位组读取完成旗标信号皆为high状态或皆为low状态，则产生状态为high的第一互斥或非门8(NXOR)输出信号，否则产生状态为low的第一互斥或非门8(NXOR)输出信号，其对应的讯息为，若低位组数据及高位组数据皆已被完整读出或皆未被完整读出，则产生状态为high的第一互斥或非门8(NXOR)输出信号，否则产生状态为low的第一互斥或非门8(NXOR)输出信号。第一与门9的其中一个输入端接收第一互斥或非门8输出信号，且第一与门9的另一个输入端接收来自上述读取起始脉冲检测模块100的第一输出信号，且产生读取起始脉冲信号9_1，若第一互斥或非门8输出信号及第一输出信号皆为high状态，则产生状态为high的读取起始脉冲信号9_1，否则产生状态为low的读取起始脉冲信号9_1，其对应的讯息为，若低位组数据及高位组数据皆已被完整读出或皆未被完整读出，且接收到低位组读取起始脉冲信号或高位组读取起始脉冲信号，则第一与门9输出状态为high的读取起始脉冲信号9_1，否则第一与门9输出状态为low的读取起始脉冲信号9_1。第二或门10的其中一个输入端接收读取起始脉冲信号9_1，且第二或门10的另一个输入端接收来自外部的第一读取时限信号10_1，产生上述的第二输出信号，其对应的讯息为，若在小于第一读取时限信号10_1的周期(10毫秒)内，且未接收到状态为high的读取起始脉冲信号9_1，则第二或门10产生状态为low的第二输出信号，否则第二或门10产生状态为high的第二输出信号，上述第一位组读取完成脉冲检测模块101的第二多工器3的第二选择输入端，及上述第二位组读取完成脉冲检测模块102的第四多工器6的选择输入端，两者接收其第二输出信号。第二与门11的其中一个输入端接收第一位组读取完成旗标信号，第二与门11的另一个输入端接收第二位组读取完成旗标信号，产生读取完成旗标信号11_1，其对应的讯息为，当低位组数据及高位组数据皆已被完整读出或皆未被完整读出，则输出状态为high的读取完成旗标信号11_1，否则输出状态为low的读取完成旗标信号11_1。总结来说，读取信号运算模块103整体在运作时，其对应的信号变化为，当低位组数据及高位组数据皆已被完整读出，则输出状态为high的读取完成旗标信号11_1至旗标模块104，代表有一个VBUS_VOLTAGE已被完整读出，否则输出状态为low的读取完成旗标信号11_1至旗标模块104。若是低位组数据及高位组数据皆已被完整读出或皆未被完整读出，且再接收到来自上述读取起始脉冲检测模块100，状态为high的第一输出信号，则输出状态为high的读取起始脉冲信号9_1至旗标模块104，代表有一个VBUS_VOLTAGE的读取正在进行，否则输出状态为low的读取起始脉冲信号9_1至旗标模块104。The read signal operation module 103 has the following logic elements: a first mutually exclusive NOR gate 8 (NXOR), a first AND gate 9 connected to the first mutually exclusive NOR gate 8 (NXOR), and a first AND gate 9 connected The second OR gate 10 and the second ANDgate 11. One of the input ends of the first mutually exclusive NOR gate 8 (NXOR) receives the first group reading completion flag signal from the above-mentioned first group reading completion pulse detection module 101, and the first mutually exclusive NOR gate 8 ( NXOR) another input terminal receives the second bit group read completion flag signal from the above-mentioned second bit group read completion pulse detection module 102, and generates the first mutually exclusive NOR gate 8 (NXOR) output signal, if the first When the read completion flag signal of one bit group and the read completion flag signal of the second bit group are both in the high state or in the low state, the output signal of the first mutually exclusive NOR gate 8 (NXOR) whose state is high is generated, Otherwise, the output signal of the first mutually exclusive NOR gate 8 (NXOR) whose state is low is generated. The output signal of the first mutual exclusive NOR gate 8 (NXOR) whose state is high, otherwise, the output signal of the first mutually exclusive NOR gate 8 (NXOR) whose state is low is generated. One of the input terminals of the first AND gate 9 receives the output signal of the first mutually exclusive NORgate 8, and the other input terminal of the first AND gate 9 receives the first output signal from the above-mentioned read start pulse detection module 100, And generate the read start pulse signal 9_1, if the output signal of the first mutual exclusive NORgate 8 and the first output signal are both in the high state, the read start pulse signal 9_1 with the high state is generated, otherwise the generated state is low The corresponding message of the read start pulse signal 9_1 is, if both the low-order group data and the high-order group data have been read out completely or not, and the low-order group read start pulse signal or high-order group data is received If the group read start pulse signal, the first AND gate 9 outputs a read start pulse signal 9_1 whose state is high; otherwise, the first AND gate 9 outputs a read start pulse signal 9_1 whose state is low. One of the input terminals of the second OR gate 10 receives the read start pulse signal 9_1, and the other input terminal of the second OR gate 10 receives the first read timing signal 10_1 from the outside to generate the above-mentioned second output signal, The corresponding message is that if the read start pulse signal 9_1 whose state is high is not received within a period (10 milliseconds) less than the first read time limit signal 10_1, the second OR gate 10 generates a state of low. Otherwise, the second OR gate 10 generates a second output signal whose state is high. The second bit group read completion pulse detection module 102 selects the input terminal of the fourth multiplexer 6, and both receive the second output signal thereof. One of the input terminals of the second ANDgate 11 receives the read completion flag signal of the first bit group, and the other input terminal of the second ANDgate 11 receives the read completion flag signal of the second bit group to generate the read completion flag Signal 11_1, the corresponding message is, when both the low-order group data and the high-order group data have been completely read out or have not been read out completely, the read completion flag signal 11_1 whose output state is high, otherwise the output state is low The read completion flag signal 11_1. To sum up, when the read signal operation module 103 is operating as a whole, its corresponding signal changes are, when both the low-order group data and the high-order group data have been completely read out, the read completion flag signal 11_1 with a high state is output. To the flag module 104 , it means that one VBUS_VOLTAGE has been read out completely, otherwise, the read completion flag signal 11_1 with a low state is output to the flag module 104 . If both the low-order group data and the high-order group data have been completely read out or have not been read out completely, and the first output signal whose state is high from the read start pulse detection module 100 is received, the output state is The high read start pulse signal 9_1 is sent to the flag module 104 , indicating that a VBUS_VOLTAGE is being read, otherwise, the low read start pulse signal 9_1 is output to the flag module 104 .

请参阅图3，其为电压同步控制电路200的第二电路图。如图所示，旗标模块104内，具有以下元件，第五多工器12、连接第五多工器12的第六多工器13、连接第六多工器的第三正反器14、连接第三正反器的第一时限计数器15及连接第一时限计数器15与第六多工器13的第三或门16。第五多工器12其中一个输入端固定接收第五高电位，第五多工器12另一个输入端接收由第三正反器14输出的保留旗标信号，第五选择输入端接收来自读取信号运算模块103的读取起始脉冲信号9_1。若读取起始脉冲信号9_1为状态high，则第五多工器12产生状态为high的第五多工器输出信号。第六多工器13其中一个输入端固定第六低电位，第六多工器13另一个输入端接收来自第五多工器12的第五多工器12输出信号，第六选择输入端接收来自第三或门16的第五输出信号，若第五输出信号为状态high，则第六多工器13输出状态为low的第六多工器13输出信号。第三正反器14接收第六多工器13输出信号，产生保留旗标信号。第一时限计数器15接收第三正反器14输出的保留旗标信号，产生第二读取时限信号，若保留旗标信号维持状态high的时间间隔超过预设时间(10毫秒)，则第二读取时限信号强制更改为状态low。第三或门16其中一个输入端接收第二读取时限信号，第三或门16另一个输入端接收来自读取信号运算模块103的读取完成旗标信号，产生上述的第五输出信号。总结来说，旗标模块104整体在运作时，其对应的信号变化为，若来自读取信号运算模块103的读取起始脉冲信号9_1为状态high，且第二读取时限信号与读取完成旗标信号皆为状态low，则保留旗标信号为状态high，否则为状态low的信号。Please refer to FIG. 3 , which is a second circuit diagram of the voltage synchronization control circuit 200 . As shown in the figure, the flag module 104 includes the following elements: afifth multiplexer 12, asixth multiplexer 13 connected to thefifth multiplexer 12, and a third flip-flop 14 connected to the sixth multiplexer , a firsttime limit counter 15 connected to the third flip-flop, and a third ORgate 16 connected to the firsttime limit counter 15 and thesixth multiplexer 13 . One of the input terminals of thefifth multiplexer 12 is fixed to receive the fifth high potential, the other input terminal of thefifth multiplexer 12 receives the reserved flag signal output by the third flip-flop 14, and the fifth selection input terminal receives the signal from the read The read start pulse signal 9_1 of the signal operation module 103 is taken. If the read start pulse signal 9_1 is in a high state, thefifth multiplexer 12 generates a fifth multiplexer output signal whose state is high. One of the input terminals of thesixth multiplexer 13 is fixed at a sixth low potential, the other input terminal of thesixth multiplexer 13 receives the output signal of thefifth multiplexer 12 from thefifth multiplexer 12 , and the sixth selection input terminal receives For the fifth output signal from the third ORgate 16, if the fifth output signal is in a state of high, thesixth multiplexer 13 outputs an output signal of thesixth multiplexer 13 whose state is low. The third flip-flop 14 receives the output signal of thesixth multiplexer 13 and generates a reserved flag signal. The firsttime limit counter 15 receives the reserved flag signal output by the third flip-flop 14, and generates a second read time limit signal. The read time limit signal is forcibly changed to state low. One input terminal of the third ORgate 16 receives the second read timing signal, and the other input terminal of the third ORgate 16 receives the read completion flag signal from the read signal operation module 103 to generate the above-mentioned fifth output signal. To sum up, when the flag module 104 is operating as a whole, the corresponding signal changes are, if the read start pulse signal 9_1 from the read signal operation module 103 is in the high state, and the second read time limit signal is the same as the read signal When the completion flag signals are all in the state low, the reserved flag signal is in the state high, otherwise it is the signal in the state low.

续请参阅图3，更新控制模块105内，具有以下元件，第一蕴含非门17，连接第一蕴含非门17的第七多工器18，连接第一蕴含非门17的第八多工器19。第一蕴含非门17其中一个输入端接收来自旗标模块104的保留旗标信号，第一蕴含非门17另一个输入端接收来自上述控制器模块108的量测完成脉冲信号，产生更新脉冲信号。第七多工器18其中一个输入端接收来自上述控制器模块108的量测结果信号18_1，第七多工器18另一个输入端接收来自上述暂存器模块109的储存第一位组数据的暂存器产生的第三输入信号，第七选择输入端接收来自第一蕴含非门17产生的更新脉冲信号，产生第三输出信号。第八多工器19其中一个输入端接收来自上述控制器模块108的量测结果信号19_1，第八多工器19另一个输入端接收来自上述暂存器模块109的储存第二位组数据的暂存器产生的第四输入信号，第八选择输入端接收来自第一蕴含非门17产生的更新脉冲信号，产生第四输出信号。总结来说，更新控制模块105整体在运作时，其对应的信号变化为，只有当保留旗标信号的状态为low，且量测完成脉冲信号状态为high时，第七多工器18或第八多工器19会将状态为high的量测结果信号输出为第三输出信号，其余情形第三输出信号皆为状态low。Continuing to refer to FIG. 3 , the update control module 105 includes the following elements: a first implicatedNOT gate 17 , aseventh multiplexer 18 connected to the first implicatedNOT gate 17 , and an eighth multiplexer connected to the first implicatedNOT gate 17device 19. One input end of the first implicatedNOT gate 17 receives the reserved flag signal from the flag module 104, and the other input end of the first implicatedNOT gate 17 receives the measurement completion pulse signal from the above-mentioned controller module 108 to generate an update pulse signal . One of the input terminals of theseventh multiplexer 18 receives the measurement result signal 18_1 from the above-mentioned controller module 108 , and the other input terminal of theseventh multiplexer 18 receives the data stored in the first set of data from the above-mentioned register module 109 . For the third input signal generated by the temporary register, the seventh selection input terminal receives the update pulse signal generated from the firstimplication NOT gate 17 to generate the third output signal. One of the input terminals of theeighth multiplexer 19 receives the measurement result signal 19_1 from the above-mentioned controller module 108 , and the other input terminal of theeighth multiplexer 19 receives the signal for storing the second group of data from the above-mentioned register module 109 . For the fourth input signal generated by the temporary register, the eighth selection input terminal receives the update pulse signal generated from the firstimplication NOT gate 17 to generate the fourth output signal. To sum up, when the update control module 105 is operating as a whole, its corresponding signal changes are that only when the state of the reserved flag signal is low and the state of the measurement completion pulse signal is high, theseventh multiplexer 18 or the first The eight-multiplexer 19 outputs the measurement result signal whose state is high as the third output signal, and the third output signal is in the state of low in other cases.

请参阅图4，其为电压读取控制系统300的方块图。如图所示，本发明提供的电压读取控制系统300中的电压同步控制器106包含上述的电压同步控制电路200，其电压同步控制器106接收上述数据解析与传输模块107产生的第一位组读取起始脉冲信号、第一位组读取完成脉冲信号、第二位组读取起始脉冲信号、第二位组读取完成脉冲信号、控制器模块108产生的量测结果信号及量测完成脉冲信号，并且产生第三输出信号及第四输出信号至暂存器模块109。数据解析与传输模块107接收来自上述TCPM传送的数据需求信号，产生第一位组读取起始脉冲信号、第一位组读取完成脉冲信号、第二位组读取起始脉冲信号及第二位组读取完成脉冲信号，并且传送至电压同步控制器106。控制器模块108接收来自外部的类比信号，产生量测结果信号及量测完成脉冲信号，并且传送至电压同步控制器106。暂存器模块109连接电压同步控制器106、数据解析与传输模块107及控制器模块108，其中暂存器模块109内，储存第一位组数据及第二位组数据，其数据的状态由上述电压同步控制器106的更新控制模块105输出的第三输出信号及第四输出信号来决定。电压读取控制系统300还包含实现使用者命令或检测外部连结状态的组态逻辑模块110，其连接暂存器模块109及连接暂存器模块109的实体层与应用层模块111。Please refer to FIG. 4 , which is a block diagram of the voltage reading control system 300 . As shown in the figure, the voltage synchronization controller 106 in the voltage reading control system 300 provided by the present invention includes the voltage synchronization control circuit 200 described above, and the voltage synchronization controller 106 receives the first bit generated by the data analysis and transmission module 107 The group read start pulse signal, the first group read complete pulse signal, the second group read start pulse signal, the second group read complete pulse signal, the measurement result signal generated by the controller module 108, and The completion pulse signal is measured, and a third output signal and a fourth output signal are generated to the register module 109 . The data analysis and transmission module 107 receives the data request signal transmitted from the above-mentioned TCPM, and generates the first group reading start pulse signal, the first group reading completion pulse signal, the second group reading start pulse signal and the first group reading start pulse signal. The 2-bit read completion pulse signal is sent to the voltage synchronization controller 106 . The controller module 108 receives an external analog signal, generates a measurement result signal and a measurement completion pulse signal, and sends them to the voltage synchronization controller 106 . The register module 109 is connected to the voltage synchronization controller 106 , the data analysis and transmission module 107 and the controller module 108 , wherein the register module 109 stores the first set of data and the second set of data, and the state of the data is represented by It is determined by the third output signal and the fourth output signal output by the update control module 105 of the voltage synchronization controller 106 . The voltage reading control system 300 also includes a configuration logic module 110 that implements user commands or detects external connection states, which is connected to the register module 109 and the physical layer andapplication layer modules 111 that connect the register module 109 .

复请参阅图3及图4，更新控制模块105的第七多工器18产生的第三输出信号，将决定暂存器模块109内储存第一位组数据的状态，而第一位组数据又成为第三输入信号，传送至第七多工器18的某一个输入端。3 and 4 again, the third output signal generated by theseventh multiplexer 18 of the update control module 105 determines the state of the first set of data stored in the register module 109, and the first set of data is stored in the register module 109. It becomes the third input signal again, and is transmitted to a certain input terminal of theseventh multiplexer 18 .

更新控制模块105的第八多工器19产生的第三输出信号，将决定暂存器模块109内储存第二位组数据的状态，而第二位组数据又成为第四输入信号，传送至第八多工器19的某一个输入端。The third output signal generated by theeighth multiplexer 19 of the update control module 105 will determine the state of storing the second group of data in the register module 109, and the second group of data will become the fourth input signal and transmitted to A certain input terminal of theeighth multiplexer 19 .

承上所述，本发明的电压同步控制电路200及包含其的电压读取控制系统300具有以下优点：Based on the above, the voltage synchronization control circuit 200 of the present invention and the voltage reading control system 300 including the same have the following advantages:

1.当电压同步控制器接收到读取暂存器模块的第一位组数据时，利用电压同步控制电路200的旗标模块产生保留旗标信号，且保留旗标信号的状态为high状态，避免第二位组数据被量测结果信号更新其数据状态。1. When the voltage synchronization controller receives the first set of data of the read register module, the flag module of the voltage synchronization control circuit 200 is used to generate a reserved flag signal, and the state of the reserved flag signal is a high state, To prevent the data state of the second group of data from being updated by the measurement result signal.

2.利用电压同步控制电路200的旗标模块内的第一时限计数器，当保留旗标信号的状态保持high状态超过一定时间间隔后，强制将保留旗标信号的状态强迫更改成low状态，让量测结果信号可以更新暂存器模块的第一位组及第二位组的数据状态，避免系统的问题。2. Using the first time limit counter in the flag module of the voltage synchronization control circuit 200, when the state of the reserved flag signal remains in the high state for more than a certain time interval, the state of the reserved flag signal is forcibly changed to the low state, so that The measurement result signal can update the data status of the first group and the second group of the register module to avoid system problems.

3.利用电压同步控制电路200，暂存器模块的实际值与理想值不会有不同步的问题发生。3. Using the voltage synchronization control circuit 200, the actual value and the ideal value of the register module will not be out of synchronization.

以上所述的实施例仅为说明本发明的技术思想及特点，其目的在使所属技术领域具有通常知识者能够了解本发明的内容并据以实施，当不能以的限定本发明的专利范围，即大凡依本发明所揭示的精神所作的均等变化或修饰，仍应涵盖在本发明的权利要求范围内。The above-mentioned embodiments are only to illustrate the technical idea and characteristics of the present invention, and the purpose thereof is to enable those with ordinary knowledge in the technical field to understand the content of the present invention and implement it accordingly, when it cannot limit the patent scope of the present invention, That is, all equivalent changes or modifications made according to the spirit disclosed in the present invention should still be covered within the scope of the claims of the present invention.

Claims (10)

Translated fromChinese

1.一种电压同步控制电路，其特征在于，包含：1. a voltage synchronous control circuit, is characterized in that, comprises:一读取起始脉冲检测模块，接收一第一位组读取起始脉冲信号及一第二位组读取起始脉冲信号，并且据以产生一第一输出信号；a read start pulse detection module, receiving a first bit group read start pulse signal and a second bit group read start pulse signal, and generating a first output signal accordingly;一第一位组读取完成脉冲检测模块，接收一第一位组读取完成脉冲信号，并且据以产生一第一位组读取完成旗标信号；a first-bit group reading completion pulse detection module, receiving a first-bit group reading completion pulse signal, and generating a first-bit group reading completion flag signal accordingly;一第二位组读取完成脉冲检测模块，接收一第二位组读取完成脉冲信号，并且据以产生一第二位组读取完成旗标信号；a second-bit group reading completion pulse detection module, receiving a second-bit group reading completion pulse signal, and generating a second-bit group reading completion flag signal accordingly;一读取信号运算模块，连接所述读取起始脉冲检测模块、所述第一位组读取完成脉冲检测模块及所述第二位组读取完成脉冲检测模块，且接收所述第一输出信号、所述第一位组读取完成旗标信号、所述第二位组读取完成旗标信号及一第一读取时限信号，并且据以产生一读取起始脉冲信号及一读取完成旗标信号；a read signal operation module, connected to the read start pulse detection module, the first bit group read completion pulse detection module and the second bit group read completion pulse detection module, and receives the first output signal, the first bit group read completion flag signal, the second bit group read completion flag signal and a first read time limit signal, and generate a read start pulse signal and a read start pulse signal accordingly read completion flag signal;一旗标模块，连接所述读取信号运算模块，且接收所述读取起始脉冲信号及所述读取完成旗标信号，并且据以产生一保留旗标信号；以及a flag module, connected to the read signal operation module, receiving the read start pulse signal and the read completion flag signal, and generating a reserved flag signal accordingly; and一更新控制模块，连接所述旗标模块，且接收所述保留旗标信号、一量测结果信号、一量测完成脉冲信号、一第三输入信号及一第四输入信号，并且产生一第三输出信号及一第四输出信号。an update control module, connected to the flag module, and receives the reserved flag signal, a measurement result signal, a measurement completion pulse signal, a third input signal and a fourth input signal, and generates a first Three output signals and a fourth output signal.2.根据权利要求1所述的电压同步控制电路，其特征在于，所述读取起始脉冲检测模块包含：2. The voltage synchronization control circuit according to claim 1, wherein the read start pulse detection module comprises:一第一或门，接收所述第一位组读取起始脉冲信号，以及接收所述第二位组读取起始脉冲信号，并且据以产生所述第一输出信号。A first OR gate receives the first bit group read start pulse signal and the second bit group read start pulse signal, and generates the first output signal accordingly.3.根据权利要求1所述的电压同步控制电路，其特征在于，所述第一位组读取完成脉冲检测模块包含：3. The voltage synchronization control circuit according to claim 1, wherein the first bit group read completion pulse detection module comprises:一第一多工器，所述第一多工器的输入端接收一第一高电位，另一所述第一多工器的输入端接收所述第一位组读取完成旗标信号，以及一第一选择输入端接收所述第一位组读取完成脉冲信号，并且据以产生一第一多工器输出信号；a first multiplexer, the input terminal of the first multiplexer receives a first high potential, and the input terminal of the other first multiplexer receives the read completion flag signal of the first bit group, and a first selection input terminal to receive the read completion pulse signal of the first bit group, and to generate a first multiplexer output signal accordingly;一第二多工器，连接所述第一多工器，所述第二多工器的输入端接收一第二低电位，另一所述第二多工器的输入端接收所述第一多工器输出信号，所述读取信号运算模块依据所述读取起始脉冲信号及所述第一读取时限信号产生一第二输出信号，一第二选择输入端接收所述第二输出信号，并且据以产生一第二多工器输出信号；以及A second multiplexer is connected to the first multiplexer, the input terminal of the second multiplexer receives a second low potential, and the input terminal of the other second multiplexer receives the first multiplexer a multiplexer output signal, the read signal operation module generates a second output signal according to the read start pulse signal and the first read time limit signal, and a second selection input terminal receives the second output signal, and generate a second multiplexer output signal accordingly; and一第一正反器，连接所述第二多工器，所述第一正反器接收所述第二多工器输出信号，并且据以产生所述第一位组读取完成旗标信号。a first flip-flop connected to the second multiplexer, the first flip-flop receives the output signal of the second multiplexer, and generates the read completion flag signal of the first bit group accordingly .4.根据权利要求1所述的电压同步控制电路，其特征在于，所述第二位组读取完成脉冲检测模块包含：4. The voltage synchronization control circuit according to claim 1, wherein the second bit group read completion pulse detection module comprises:一第三多工器，所述第三多工器的输入端接收一第三高电位，另一所述第三多工器的输入端接收所述第二位组读取完成旗标信号，以及一第三选择输入端接收所述第二位组读取完成脉冲信号，并且据以产生一第三多工器输出信号；a third multiplexer, the input terminal of the third multiplexer receives a third high potential, and the input terminal of the other third multiplexer receives the read completion flag signal of the second bit group, and a third selection input terminal to receive the second bit group read completion pulse signal, and to generate a third multiplexer output signal accordingly;一第四多工器，连接所述第三多工器，所述第四多工器的输入端接收一第四低电位，另一所述第四多工器的输入端接收所述第三多工器输出信号，所述读取信号运算模块依据所述读取起始脉冲信号及所述第一读取时限信号产生一第二输出信号，一第四选择输入端接收所述第二输出信号，并且据以产生一第四多工器输出信号；以及A fourth multiplexer is connected to the third multiplexer, the input terminal of the fourth multiplexer receives a fourth low potential, and the input terminal of the other fourth multiplexer receives the third multiplexer a multiplexer output signal, the read signal operation module generates a second output signal according to the read start pulse signal and the first read time limit signal, and a fourth selection input terminal receives the second output signal, and generate a fourth multiplexer output signal accordingly; and一第二正反器，连接所述第四多工器，所述第二正反器接收所述第四多工器输出信号，并且据以产生所述第二位组读取完成旗标信号。A second flip-flop is connected to the fourth multiplexer, the second flip-flop receives the output signal of the fourth multiplexer, and generates the read completion flag signal of the second bit group accordingly .5.根据权利要求1所述的电压同步控制电路，其特征在于，所述读取信号运算模块包含：5. The voltage synchronization control circuit according to claim 1, wherein the read signal operation module comprises:一第一互斥或非门，所述第一互斥或非门的输入端接收所述第一位组读取完成旗标信号，另一所述第一互斥或非门的输入端接收所述第二位组读取完成旗标信号，并且据以产生一第一互斥或非门输出信号；A first mutually exclusive NOR gate, the input terminal of the first mutually exclusive NOR gate receives the read completion flag signal of the first group, and the input terminal of the other first mutually exclusive NOR gate receives The second bit group reads the completion flag signal, and generates a first mutually exclusive NOR gate output signal accordingly;一第一与门，连接所述第一互斥或非门，所述第一与门的输入端接收所述第一输出信号，另一所述第一与门的输入端接收所述第一互斥或非门输出信号，并且据以产生所述读取起始脉冲信号；A first AND gate is connected to the first mutually exclusive NOR gate, the input terminal of the first AND gate receives the first output signal, and the input terminal of the other first AND gate receives the first Mutually exclusive NOR gate output signal, and generate the read start pulse signal accordingly;一第二或门，连接所述第一与门，所述第二或门的输入端接收所述第一读取时限信号，另一所述第二或门的输入端接收所述读取起始脉冲信号，并且据以产生一第二输出信号；以及A second OR gate, connected to the first AND gate, the input terminal of the second OR gate receives the first read timing signal, and the input terminal of the other second OR gate receives the read start signal an initial pulse signal, and a second output signal is generated accordingly; and一第二与门，所述第二与门的输入端接收所述第一位组读取完成旗标信号，另一所述第二与门的输入端接收所述第二位组读取完成旗标信号，并且据以产生所述读取完成旗标信号。A second AND gate, the input terminal of the second AND gate receives the read completion flag signal of the first bit group, and the input terminal of the other second AND gate receives the read completion of the second bit group flag signal, and the read completion flag signal is generated accordingly.6.根据权利要求1所述的电压同步控制电路，其特征在于，所述旗标模块包含：6. The voltage synchronization control circuit according to claim 1, wherein the flag module comprises:一第五多工器，所述第五多工器的输入端接收一第五高电位，另一所述第五多工器的输入端接收所述保留旗标信号，以及一第五选择输入端接收所述读取起始脉冲信号，并且据以产生一第五多工器输出信号；a fifth multiplexer, the input terminal of the fifth multiplexer receives a fifth high potential, the input terminal of the other fifth multiplexer receives the reserved flag signal, and a fifth selection input The terminal receives the read start pulse signal, and generates a fifth multiplexer output signal accordingly;一第六多工器，连接所述第五多工器，所述第六多工器的输入端接收一第六低电位，另一所述第六多工器的输入端接收所述第五多工器输出信号，以及一第六选择输入端接收一第五输出信号，并且据以产生一第六多工器输出信号；A sixth multiplexer is connected to the fifth multiplexer, the input terminal of the sixth multiplexer receives a sixth low potential, and the input terminal of the other sixth multiplexer receives the fifth multiplexer The multiplexer output signal, and a sixth selection input terminal receives a fifth output signal, and generates a sixth multiplexer output signal accordingly;一第三正反器，连接所述第六多工器，所述第三正反器接收所述第六多工器输出信号，并且据以产生所述保留旗标信号；a third flip-flop connected to the sixth multiplexer, the third flip-flop receives the output signal of the sixth multiplexer, and generates the reserved flag signal accordingly;一第一时限计数器，连接所述第三正反器，所述第一时限计数器接收所述保留旗标信号，并且据以产生一第二读取时限信号；以及a first time limit counter connected to the third flip-flop, the first time limit counter receives the reserved flag signal, and generates a second read time limit signal accordingly; and一第三或门，连接所述第一时限计数器及所述第六多工器，所述第三或门的输入端接收所述第二读取时限信号，另一所述第三或门的输入端接收所述读取完成旗标信号，并且据以产生所述第五输出信号。A third OR gate, connected to the first time limit counter and the sixth multiplexer, the input end of the third OR gate receives the second read time limit signal, and the other gate of the third OR gate The input terminal receives the read completion flag signal and generates the fifth output signal accordingly.7.根据权利要求1所述的电压同步控制电路，其特征在于，所述更新控制模块包含：7. The voltage synchronization control circuit according to claim 1, wherein the update control module comprises:一第一蕴含非门，所述第一蕴含非门的输入端接收所述量测完成脉冲信号，另一所述第一蕴含非门的输入端接收所述保留旗标信号，并且据以产生一更新脉冲信号；A first implicated NOT gate, the input of the first implicated NOT gate receives the measurement completion pulse signal, and the other input end of the first implicated NOT gate receives the reserved flag signal, and generates accordingly an update pulse signal;一第七多工器，连接所述第一蕴含非门，所述第七多工器的输入端接收所述量测结果信号，另一所述第七多工器的输入端接收所述第三输入信号，以及一第七选择输入端接收所述更新脉冲信号，并且据以产生一第三输出信号；以及A seventh multiplexer is connected to the first implicated NOT gate, the input terminal of the seventh multiplexer receives the measurement result signal, and the input terminal of the other seventh multiplexer receives the first three input signals, and a seventh selection input terminal receives the refresh pulse signal and generates a third output signal accordingly; and一第八多工器，连接所述第一蕴含非门，所述第八多工器的输入端接收所述量测结果信号，另一所述第八多工器的输入端接收所述第四输入信号，以及一第八选择输入端接收所述更新脉冲信号，并且据以产生一第四输出信号。an eighth multiplexer, connected to the first implication NOT gate, the input terminal of the eighth multiplexer receives the measurement result signal, and the input terminal of the other eighth multiplexer receives the first Four input signals and an eighth selection input terminal receive the refresh pulse signal and generate a fourth output signal accordingly.8.一种电压读取控制系统，其特征在于，包含：8. A voltage reading control system, characterized in that, comprising:一电压同步控制器，具有如权利要求1至7中任一项所述的电压同步控制电路，且接收所述第一位组读取起始脉冲信号、所述第一位组读取完成脉冲信号、所述第二位组读取起始脉冲信号、所述第二位组读取完成脉冲信号、所述量测结果信号及所述量测完成脉冲信号，并且据以产生一第三输出信号及一第四输出信号；A voltage synchronization controller, having the voltage synchronization control circuit according to any one of claims 1 to 7, and receiving the first-bit group reading start pulse signal and the first-bit group reading completion pulse signal, the second bit group reading start pulse signal, the second bit group reading completion pulse signal, the measurement result signal and the measurement completion pulse signal, and a third output is generated accordingly signal and a fourth output signal;一数据解析与传输模块，连接所述电压同步控制器，接收至少一外部数据需求信号，据以产生所述第一位组读取起始脉冲信号、所述第一位组读取完成脉冲信号、所述第二位组读取起始脉冲信号及所述第二位组读取完成脉冲信号；A data analysis and transmission module, connected to the voltage synchronization controller, receives at least one external data request signal, and generates the first-bit group read start pulse signal and the first-bit group read-complete pulse signal accordingly , the second bit group read start pulse signal and the second bit group read completion pulse signal;一控制器模块，连接所述电压同步控制器，接收一外部类比信号，且据以产生所述量测结果信号及所述量测完成脉冲信号；a controller module, connected to the voltage synchronization controller, receiving an external analog signal, and generating the measurement result signal and the measurement completion pulse signal accordingly;一暂存器模块，连接所述电压同步控制器、所述数据解析与传输模块及所述控制器模块，且接收所述第三输出信号及所述第四输出信号，所述暂存器模块储存一第一位组数据及一第二位组数据，并且据以产生一第三输入信号及一第四输入信号；A register module is connected to the voltage synchronization controller, the data analysis and transmission module and the controller module, and receives the third output signal and the fourth output signal, the register module storing a first set of data and a second set of data, and generating a third input signal and a fourth input signal accordingly;一组态逻辑模块，连接所述暂存器模块，且实现使用者命令或检测外部连结状态；以及a configuration logic module, connected to the register module, and implementing user commands or detecting external connection status; and一实体层与应用层模块，连接所述暂存器模块。A physical layer and application layer module is connected to the register module.9.根据权利要求8所述的电压读取控制系统，其特征在于，所述暂存器模块的所述第一位组数据产生所述第三输入信号。9 . The voltage reading control system according to claim 8 , wherein the first set of data of the register module generates the third input signal. 10 .10.根据权利要求8所述的电压读取控制系统，其特征在于，所述暂存器模块的所述第二位组数据产生所述第四输入信号。10 . The voltage reading control system of claim 8 , wherein the second bit group data of the register module generates the fourth input signal. 11 .

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