CN111490783B - Delta-sigma analog-to-digital converter - Google Patents

Abstract

Translated fromChinese

本发明提出一种三角积分模拟数字转换器，包含：减法器，用于从模拟输入信号中减去反馈信号；回路滤波器，用于处理减法器的输出信号以产生滤波信号；信号比较电路，可选择性地操作在偏移检测模式或信号比较模式，其中，信号比较电路操作在偏移检测模式时会产生与滤波信号及参考信号的相对大小无关的误差信号，而操作在信号比较模式时则会产生与滤波信号及参考信号的相对大小对应的比较信号；偏移校正电路，用于校正信号比较电路的偏移，并控制信号比较电路在偏移检测模式与信号比较模式之间交替切换；以及数字模拟转换器，用于依据比较信号产生反馈信号。

The present invention proposes a delta-sigma analog-to-digital converter, comprising: a subtractor for subtracting a feedback signal from an analog input signal; a loop filter for processing an output signal of the subtractor to generate a filter signal; a signal comparison circuit, Can be selectively operated in offset detection mode or signal comparison mode, wherein the signal comparison circuit will generate an error signal independent of the relative magnitude of the filtered signal and the reference signal when operating in the offset detection mode, while operating in the signal comparison mode A comparison signal corresponding to the relative size of the filtered signal and the reference signal will be generated; the offset correction circuit is used to correct the offset of the signal comparison circuit, and controls the signal comparison circuit to alternately switch between the offset detection mode and the signal comparison mode ; and a digital-to-analog converter for generating a feedback signal according to the comparison signal.

Description

Translated fromChinese

三角积分模拟数字转换器Delta-Sigma Analog-to-Digital Converter

技术领域technical field

本发明涉及模拟数字转换器(analog-to-digital converter，ADC)，特别涉及一种用于交替进行信号转换与比较器偏移校正并可同时减少空闲音产生的三角积分模拟数字转换器(sigma-delta ADC)。The present invention relates to an analog-to-digital converter (analog-to-digital converter, ADC), in particular to a delta-sigma analog-to-digital converter (sigma) for alternately performing signal conversion and comparator offset correction and simultaneously reducing idle tones. -delta ADC).

背景技术Background technique

三角积分模拟数字转换器的应用相当广泛，但其内部的比较器常因工艺差异(process deviation)而存在信号偏移(offset)的情况。若不校正三角积分模拟数字转换器的比较器偏移，将会严重影响三角积分模拟数字转换器的信噪比(signal-to-noise，SNR)，以及总谐波失真加噪音(TotalHarmonic Distortion plus Noise，THDN)等相关效能。Delta-sigma analog-to-digital converters are widely used, but their internal comparators often have signal offsets due to process deviation. If the comparator offset of the delta-sigma ADC is not corrected, the signal-to-noise ratio (signal-to-noise, SNR) and total harmonic distortion plus noise (TotalHarmonic Distortion plus Noise, THDN) and other related performance.

另外，传统的三角积分模拟数字转换器的电路特性也容易产生空闲音(idletone)的问题。现有技术通常是在三角积分模拟数字转换器中设置额外的抖动信号产生电路来抑制空闲音的产生，但也因此会增加电路的复杂度。In addition, the circuit characteristic of the traditional delta-sigma analog-to-digital converter is also prone to produce the problem of idle tone (idle tone). In the prior art, an additional jitter signal generating circuit is usually provided in the delta-sigma analog-to-digital converter to suppress generation of idle tones, but this also increases the complexity of the circuit.

发明内容Contents of the invention

有鉴于此，如何用精简的电路减轻或消除三角积分模拟数字转换器的比较器偏移并同时减少空闲音产生，实为有待解决的问题。In view of this, how to reduce or eliminate the comparator offset of the delta-sigma analog-to-digital converter with a simplified circuit and at the same time reduce the generation of idle tones is a problem to be solved.

本说明书提供一种三角积分模拟数字转换器的实施例，其包含：一减法器，设置成从一模拟输入信号中减去一反馈信号；一回路滤波器，耦接于该减法器，设置成处理该减法器的输出信号以产生一滤波信号；一第一信号比较电路，耦接于该回路滤波器与一第一参考信号，设置成可选择性地操作在一偏移检测模式或一信号比较模式，其中，该第一信号比较电路操作在该偏移检测模式时会产生与该滤波信号及该第一参考信号的相对大小无关的一第一误差信号，而操作在该信号比较模式时则会产生与该滤波信号及该第一参考信号的相对大小对应的一第一比较信号；一偏移校正电路，耦接于该第一信号比较电路，设置成依据该第一误差信号校正该第一信号比较电路的偏移情况，并控制该第一信号比较电路在该偏移检测模式与该信号比较模式之间交替切换；以及一数字模拟转换器，耦接于该第一信号比较电路的输出端与该减法器，设置成依据该第一比较信号产生该反馈信号。This specification provides an embodiment of a delta-sigma analog-to-digital converter, which includes: a subtractor configured to subtract a feedback signal from an analog input signal; a loop filter coupled to the subtractor configured to processing the output signal of the subtractor to generate a filtered signal; a first signal comparison circuit, coupled to the loop filter and a first reference signal, configured to selectively operate in an offset detection mode or a signal A comparison mode, wherein the first signal comparison circuit generates a first error signal independent of the relative magnitudes of the filtered signal and the first reference signal when operating in the offset detection mode, and when operating in the signal comparison mode A first comparison signal corresponding to the relative magnitudes of the filtered signal and the first reference signal will be generated; an offset correction circuit, coupled to the first signal comparison circuit, is configured to correct the first error signal according to the first error signal Offset of the first signal comparison circuit, and control the first signal comparison circuit to alternately switch between the offset detection mode and the signal comparison mode; and a digital-to-analog converter coupled to the first signal comparison circuit The output terminal of the subtractor is set to generate the feedback signal according to the first comparison signal.

上述实施例的优点之一，是偏移校正电路可有效校正第一信号比较电路的信号偏移情况，所以能改善三角积分模拟数字转换器的整体效能。One of the advantages of the above embodiment is that the offset correction circuit can effectively correct the signal offset of the first signal comparison circuit, so the overall performance of the delta-sigma analog-to-digital converter can be improved.

上述实施例的另一优点，是偏移校正电路在进行第一信号比较电路的偏移校正时，可同时抑制空闲音的产生，因此无需设置额外的抖动信号产生电路，所以能简化三角积分模拟数字转换器的电路架构。Another advantage of the above embodiment is that the offset correction circuit can suppress the generation of idle tones at the same time when performing the offset correction of the first signal comparison circuit, so there is no need to set an additional jitter signal generation circuit, so the delta-sigma simulation can be simplified Circuit architecture of a digitizer.

本发明的其他优点将搭配以下的说明和附图进行更详细的解说。Other advantages of the present invention will be explained in more detail with the following description and accompanying drawings.

附图说明Description of drawings

图1为本发明第一实施例的三角积分模拟数字转换器简化后的功能方框图。FIG. 1 is a simplified functional block diagram of a delta-sigma analog-to-digital converter according to the first embodiment of the present invention.

图2为图1中的三角积分模拟数字转换器简化后的第一实施例运行时序图。FIG. 2 is a simplified operational timing diagram of the first embodiment of the delta-sigma analog-to-digital converter in FIG. 1 .

图3为图1中的信号比较电路的第一实施例简化后的功能图。FIG. 3 is a simplified functional diagram of the first embodiment of the signal comparison circuit in FIG. 1 .

图4至图6为图2中的信号比较电路操作在不同模式时的简化后运行示意图。4 to 6 are simplified operational schematic diagrams of the signal comparison circuit in FIG. 2 operating in different modes.

图7为图1中的三角积分模拟数字转换器简化后的第二实施例运行时序图。FIG. 7 is a simplified operational timing diagram of the second embodiment of the delta-sigma analog-to-digital converter in FIG. 1 .

图8为图1中的信号比较电路的第二实施例简化后的功能图。FIG. 8 is a simplified functional diagram of the second embodiment of the signal comparison circuit in FIG. 1 .

图9为图1中的信号比较电路的第三实施例简化后的功能图。FIG. 9 is a simplified functional diagram of a third embodiment of the signal comparison circuit in FIG. 1 .

符号说明Symbol Description

100 三角积分模拟数字转换器(Sigma-Delta analog-to-digital converter)100 Sigma-Delta analog-to-digital converter

110 减法器(subtractor)110 Subtractor (subtractor)

120 回路滤波器(loop filter)120 Loop filter (loop filter)

130 第一信号比较电路(first signal comparing circuit)130 First signal comparing circuit (first signal comparing circuit)

132 第一比较器(first comparator)132 first comparator (first comparator)

134 第一信号选择电路(first signal selection circuit)134 The first signal selection circuit (first signal selection circuit)

136 第一补偿电路(first compensation circuit)136 The first compensation circuit (first compensation circuit)

140 第二信号比较电路(second signal comparing circuit)140 Second signal comparing circuit (second signal comparing circuit)

142 第二比较器(second comparator)142 second comparator (second comparator)

144 第二信号选择电路(second signal selection circuit)144 Second signal selection circuit (second signal selection circuit)

146 第二补偿电路(second compensation circuit)146 Second compensation circuit (second compensation circuit)

150 偏移校正电路(offset calibration circuit)150 offset correction circuit (offset calibration circuit)

160 数字模拟转换器(digital-to-analog converter)160 digital-to-analog converter

322 第一输入端(first input terminal)322 First input terminal (first input terminal)

324 第二输入端(second input terminal)324 Second input terminal (second input terminal)

326 第三输入端(third input terminal)326 Third input terminal (third input terminal)

328 第四输入端(fourth input terminal)328 Fourth input terminal (fourth input terminal)

342 第一开关电路(first switch circuit)342 First switch circuit

344 第二开关电路(second switch circuit)344 Second switch circuit

362 补偿电容(compensation capacitor)362 Compensation capacitor

364 第一调整电路(first adjusting circuit)364 First adjusting circuit (first adjusting circuit)

366 第二调整电路(second adjusting circuit)366 Second adjusting circuit (second adjusting circuit)

368 第三开关电路(third switch circuit)368 Third switch circuit

具体实施方式Detailed ways

以下将配合相关附图来说明本发明的实施例。在附图中，相同的标号表示相同或类似的元件或方法流程。Embodiments of the present invention will be described below in conjunction with related drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.

图1为本发明第一实施例的三角积分模拟数字转换器100简化后的功能方框图。三角积分模拟数字转换器100可用于将一模拟输入信号Sin转换成相应的数字输出信号。FIG. 1 is a simplified functional block diagram of a delta-sigma analog-to-digital converter 100 according to the first embodiment of the present invention. The delta-sigma ADC 100 is used to convert an analog input signal Sin into a corresponding digital output signal.

如图1所示，三角积分模拟数字转换器100包含一减法器110、一回路滤波器120、一或多个信号比较电路(例如，图1中的示例性第一信号比较电路130与第二信号比较电路140)、一偏移校正电路150、以及一数字模拟转换器160。As shown in FIG. 1 , the delta-sigma analog-to-digital converter 100 includes asubtractor 110, aloop filter 120, and one or more signal comparison circuits (for example, the exemplary firstsignal comparison circuit 130 and the secondsignal comparison circuit 130 in FIG. 1 signal comparison circuit 140 ), anoffset correction circuit 150 , and a digital-to-analog converter 160 .

减法器110耦接于模拟输入信号Sin，设置成从模拟输入信号Sin中减去一反馈信号Sfb。Thesubtractor 110 is coupled to the analog input signal Sin and configured to subtract a feedback signal Sfb from the analog input signal Sin.

回路滤波器120耦接于减法器110，设置成处理减法器110的输出信号以产生一滤波信号SF。Theloop filter 120 is coupled to thesubtractor 110 and configured to process the output signal of thesubtractor 110 to generate a filtered signal SF.

第一信号比较电路130耦接于回路滤波器120与一第一参考信号VR1，设置成可选择性地操作在一偏移检测模式或一信号比较模式。第一信号比较电路130操作在偏移检测模式时，会产生与滤波信号SF及第一参考信号VR1的相对大小无关的一第一误差信号ERR1。而第一信号比较电路130操作在信号比较模式时，则会产生与滤波信号SF及第一参考信号VR1的相对大小对应的一第一比较信号CMP1。The firstsignal comparison circuit 130 is coupled to theloop filter 120 and a first reference signal VR1, and is configured to selectively operate in an offset detection mode or a signal comparison mode. When the firstsignal comparison circuit 130 operates in the offset detection mode, it generates a first error signal ERR1 which is independent of the relative magnitudes of the filter signal SF and the first reference signal VR1. When the firstsignal comparison circuit 130 operates in the signal comparison mode, it will generate a first comparison signal CMP1 corresponding to the relative magnitudes of the filter signal SF and the first reference signal VR1.

第二信号比较电路140耦接于回路滤波器120与一第二参考信号VRn，同样设置成可选择性地操作在偏移检测模式或信号比较模式。第二信号比较电路140操作在偏移检测模式时，会产生与滤波信号SF及第二参考信号VRn的相对大小无关的一第二误差信号ERRn。而第二信号比较电路140操作在信号比较模式时，则会产生与滤波信号SF及第二参考信号VRn的相对大小对应的一第二比较信号CMPn。The secondsignal comparison circuit 140 is coupled to theloop filter 120 and a second reference signal VRn, and is also configured to selectively operate in an offset detection mode or a signal comparison mode. When the secondsignal comparison circuit 140 operates in the offset detection mode, it generates a second error signal ERRn that is independent of the relative magnitudes of the filter signal SF and the second reference signal VRn. When the secondsignal comparison circuit 140 operates in the signal comparison mode, it will generate a second comparison signal CMPn corresponding to the relative magnitude of the filter signal SF and the second reference signal VRn.

偏移校正电路150耦接于第一信号比较电路130与第二信号比较电路140，设置成依据第一误差信号ERR1校正第一信号比较电路130的偏移情况，并依据第二误差信号ERRn校正第二信号比较电路140的偏移情况。此外，偏移校正电路150还设置成控制第一信号比较电路130在偏移检测模式与信号比较模式之间交替切换，并且控制第二信号比较电路140在偏移检测模式与信号比较模式之间交替切换。Theoffset correction circuit 150 is coupled to the firstsignal comparison circuit 130 and the secondsignal comparison circuit 140, configured to correct the offset of the firstsignal comparison circuit 130 according to the first error signal ERR1, and to correct the offset according to the second error signal ERRn Offset of the secondsignal comparison circuit 140 . In addition, theoffset correction circuit 150 is also configured to control the firstsignal comparison circuit 130 to alternately switch between the offset detection mode and the signal comparison mode, and control the secondsignal comparison circuit 140 to switch between the offset detection mode and the signal comparison mode Toggle alternately.

数字模拟转换器160耦接于第一信号比较电路130的输出端、第二信号比较电路140的输出端以及减法器110，设置成依据第一比较信号CMP1与第二比较信号CMPn产生前述的反馈信号Sfb。The digital-to-analog converter 160 is coupled to the output end of the firstsignal comparison circuit 130, the output end of the secondsignal comparison circuit 140, and thesubtractor 110, and is configured to generate the aforementioned feedback according to the first comparison signal CMP1 and the second comparison signal CMPn. Signal Sfb.

实作上，前述的减法器110可利用各种基于运算放大器架构的合适电路、或是其他具有模拟信号相减功能的现有电路来实现。回路滤波器120可利用各种具有噪声整形的合适积分电路来实现。偏移校正电路150可利用各种能够判读数字信号、进行数字运算、与产生控制信号的合适电路来实现。数字模拟转换器160则可用各种合适的现有数字至模拟转换电路来实现。In practice, theaforesaid subtractor 110 can be realized by various suitable circuits based on the architecture of operational amplifiers, or other existing circuits with analog signal subtraction functions.Loop filter 120 can be implemented using various suitable integrating circuits with noise shaping. The offsetcorrection circuit 150 can be realized by various suitable circuits capable of interpreting digital signals, performing digital operations, and generating control signals. The digital-to-analog converter 160 can be realized by various suitable existing digital-to-analog conversion circuits.

另外，可将三角积分模拟数字转换器100中的所有信号比较电路设计成具有类似的电路架构与运行方式。例如，在图1的实施例中，第一信号比较电路130包含有一第一比较器132、一第一信号选择电路134、以及一第一补偿电路136。相仿地，第二信号比较电路140包含有一第二比较器142、一第二信号选择电路144、以及一第二补偿电路146。In addition, all the signal comparison circuits in the delta-sigma analog-to-digital converter 100 can be designed to have similar circuit structures and operation modes. For example, in the embodiment of FIG. 1 , the firstsignal comparison circuit 130 includes afirst comparator 132 , a firstsignal selection circuit 134 , and afirst compensation circuit 136 . Similarly, the secondsignal comparison circuit 140 includes asecond comparator 142 , a secondsignal selection circuit 144 , and asecond compensation circuit 146 .

在第一信号比较电路130中，第一比较器132包含有四个输入端，并设置成依据这四个输入端的信号产生相应的输出信号。第一信号选择电路134耦接于回路滤波器120、第一比较器132、偏移校正电路150、第一参考信号VR1、与一第一固定电位信号VF1，并设置成依据偏移校正电路150的控制，选择性切换第一比较器132的输入端所耦接的信号。第一补偿电路136耦接于第一比较器132与偏移校正电路150，设置成依据偏移校正电路150的控制，对第一比较器132的至少其中一个输入端进行信号补偿。前述的第一固定电位信号VF1可以是第一比较器132的共模电压信号或是其他具有固定电压值的参考信号。In the firstsignal comparison circuit 130 , thefirst comparator 132 includes four input terminals and is configured to generate corresponding output signals according to the signals of the four input terminals. The firstsignal selection circuit 134 is coupled to theloop filter 120, thefirst comparator 132, the offsetcorrection circuit 150, the first reference signal VR1, and a first fixed potential signal VF1, and is configured to be based on the offsetcorrection circuit 150 The control selectively switches the signal coupled to the input terminal of thefirst comparator 132 . Thefirst compensation circuit 136 is coupled to thefirst comparator 132 and the offsetcorrection circuit 150 , and is configured to perform signal compensation on at least one input terminal of thefirst comparator 132 according to the control of the offsetcorrection circuit 150 . The aforementioned first fixed potential signal VF1 may be the common-mode voltage signal of thefirst comparator 132 or other reference signals with fixed voltage values.

在第二信号比较电路140中，第二比较器142设置成比较其输入端的信号以产生输出信号。第二信号选择电路144耦接于回路滤波器120、第二比较器142、偏移校正电路150、第二参考信号VRn、与一第二固定电位信号VFn，并设置成依据偏移校正电路150的控制，选择性切换第二比较器142的输入端所耦接的信号。第二补偿电路146耦接于第二比较器142与偏移校正电路150，设置成依据偏移校正电路150的控制，对第二比较器142的至少其中一个输入端进行信号补偿。前述的第二固定电位信号VFn可以是第二比较器142的共模电压信号或是其他具有固定电压值的参考信号。In the secondsignal comparison circuit 140, asecond comparator 142 is arranged to compare the signals at its inputs to generate an output signal. The secondsignal selection circuit 144 is coupled to theloop filter 120, thesecond comparator 142, the offsetcorrection circuit 150, the second reference signal VRn, and a second fixed potential signal VFn, and is configured according to the offsetcorrection circuit 150 The control selectively switches the signal coupled to the input terminal of thesecond comparator 142 . Thesecond compensation circuit 146 is coupled to thesecond comparator 142 and the offsetcorrection circuit 150 , and is configured to perform signal compensation on at least one input terminal of thesecond comparator 142 according to the control of the offsetcorrection circuit 150 . The aforementioned second fixed potential signal VFn may be the common-mode voltage signal of thesecond comparator 142 or other reference signals with fixed voltage values.

实作上，前述的第一固定电位信号VF1与第二固定电位信号VFn两者可以具有相同的电压值，也可以分别具有不同的电压值。In practice, both the aforementioned first fixed potential signal VF1 and the second fixed potential signal VFn may have the same voltage value, or may have different voltage values respectively.

请参考图2，其所示出为图1中的三角积分模拟数字转换器100简化后的第一实施例运行时序图。Please refer to FIG. 2 , which shows a simplified operation timing diagram of the first embodiment of the delta-sigma analog-to-digital converter 100 in FIG. 1 .

在运行时，偏移校正电路150可依据一工作时钟CLK进行运行，并在工作时钟CLK的每一预定数量的工作周期中，控制每个信号比较电路切换至偏移检测模式至少一次、也切换至信号比较模式至少一次。前述的预定数量，实作上可以是一个、两个、三个、或是其他的固定整数。During operation, the offsetcorrection circuit 150 can operate according to a working clock CLK, and control each signal comparison circuit to switch to the offset detection mode at least once and also switch to signal compare mode at least once. The aforementioned predetermined number may be one, two, three, or other fixed integers in practice.

例如，如图2所示，偏移校正电路150可在工作时钟CLK的每一工作周期中，控制前述的第一信号比较电路130与第二信号比较电路140先同步切换至偏移检测模式运行一段时间(例如，时段T21)、然后再同步切换至信号比较模式运行一段时间(例如，时段T22)。在本实施例中，时段T21与时段T22的长度都是工作时钟CLK的半个工作周期。For example, as shown in FIG. 2 , the offsetcorrection circuit 150 can control the aforementioned firstsignal comparison circuit 130 and secondsignal comparison circuit 140 to switch to the offset detection mode synchronously in each working cycle of the working clock CLK. For a period of time (for example, period T21 ), and then synchronously switch to the signal comparison mode and run for a period of time (for example, period T22 ). In this embodiment, the lengths of the time period T21 and the time period T22 are both half a working period of the working clock CLK.

在偏移检测模式中，第一信号选择电路134会将第一比较器132的输入端耦接至第一固定电位信号VF1，使第一比较器132产生前述的第一误差信号ERR1，而第二信号选择电路144则会将第二比较器142的输入端耦接至第二固定电位信号VFn，使第二比较器142产生前述的第二误差信号ERRn。In the offset detection mode, the firstsignal selection circuit 134 will couple the input terminal of thefirst comparator 132 to the first fixed potential signal VF1, so that thefirst comparator 132 generates the aforementioned first error signal ERR1, and the second The two-signal selection circuit 144 couples the input end of thesecond comparator 142 to the second fixed potential signal VFn, so that thesecond comparator 142 generates the aforementioned second error signal ERRn.

在信号比较模式中，第一信号选择电路134会改为将第一比较器132的输入端分别耦接至滤波信号SF与第一参考信号VR1，使第一比较器132产生前述的第一比较信号CMP1，而第二信号选择电路144则会改为将第二比较器142的输入端分别耦接至滤波信号SF与第二参考信号VRn，使第二比较器142产生前述的第二比较信号CMPn。In the signal comparison mode, the firstsignal selection circuit 134 will instead couple the input terminals of thefirst comparator 132 to the filter signal SF and the first reference signal VR1, so that thefirst comparator 132 generates the aforementioned first comparison signal CMP1, and the secondsignal selection circuit 144 will instead couple the input terminals of thesecond comparator 142 to the filter signal SF and the second reference signal VRn, so that thesecond comparator 142 generates the aforementioned second comparison signal CMPn.

偏移校正电路150可依据第一误差信号ERR1调整第一补偿电路136的信号补偿量，以校正第一比较器132的信号偏移情况。同样地，偏移校正电路150可依据第二误差信号ERRn调整第二补偿电路146的信号补偿量，以校正第二比较器142的信号偏移情况。The offsetcorrection circuit 150 can adjust the signal compensation amount of thefirst compensation circuit 136 according to the first error signal ERR1 to correct the signal offset of thefirst comparator 132 . Likewise, the offsetcorrection circuit 150 can adjust the signal compensation amount of thesecond compensation circuit 146 according to the second error signal ERRn, so as to correct the signal offset of thesecond comparator 142 .

由前述说明可知，前述三角积分模拟数字转换器100中的每个信号比较电路会间歇地进行滤波信号SF与相应参考信号的比较动作，以实现三角积分模拟数字转换器100的模拟至数字转换功能。It can be seen from the foregoing description that each signal comparison circuit in the aforementioned delta-sigma analog-to-digital converter 100 will intermittently compare the filtered signal SF with the corresponding reference signal to realize the analog-to-digital conversion function of the delta-sigma-sigma analog-to-digital converter 100 .

另一方面，前述三角积分模拟数字转换器100中的每个信号比较电路也会间歇地切换至偏移检测模式，使偏移校正电路150得以依据每个比较器在偏移检测模式时所输出的误差信号判断个别比较器的信号偏移情况，并控制前述的补偿电路校正相应比较器的信号偏移情况。On the other hand, each signal comparison circuit in the aforementioned delta-sigma analog-to-digital converter 100 will also intermittently switch to the offset detection mode, so that the offsetcorrection circuit 150 can be based on the output of each comparator in the offset detection mode The error signal of the individual comparator is used to determine the signal offset of the individual comparator, and the aforementioned compensation circuit is controlled to correct the signal offset of the corresponding comparator.

前述三角积分模拟数字转换器100中的多个信号比较电路共同扮演一量化器(quantizer)的角色，而这些信号比较电路所产生的比较信号(例如，前述的第一比较信号CMP1与第二比较信号CMPn)共同形成三角积分模拟数字转换器100的数字输出信号，可供后级的数字处理电路(图中未示出)做进一步处理。A plurality of signal comparison circuits in the aforementioned delta-sigma analog-to-digital converter 100 jointly play the role of a quantizer (quantizer), and the comparison signals generated by these signal comparison circuits (for example, the aforementioned first comparison signal CMP1 and the second comparison signal The signals CMPn) jointly form the digital output signal of the delta-sigma analog-to-digital converter 100, which can be further processed by a subsequent digital processing circuit (not shown in the figure).

前述回路滤波器120的运行可对三角积分模拟数字转换器100的量化噪声(quantization noise)进行噪声整形(noise shaping)，将量化噪声移往人耳较无法感受的高频频段，以借此提升输出音频的品质。The operation of theaforementioned loop filter 120 can carry out noise shaping (noise shaping) to the quantization noise (quantization noise) of the delta-sigma analog-to-digital converter 100, and move the quantization noise to the high-frequency band which is less perceptible to the human ear, thereby improving The quality of the output audio.

另外，同一个信号比较电路在每个工作周期中操作于偏移检测模式的时间长度，并不限定于要与操作于信号比较模式的时间长度相等。例如，在某些实施例中，可将同一个信号比较电路在每个工作周期中操作于偏移检测模式的时间长度，调整成比操作于信号比较模式的时间长度更长。又例如，在另一些实施例中，则可将同一个信号比较电路在每个工作周期中操作于偏移检测模式的时间长度，调整成比操作于信号比较模式的时间长度更短。In addition, the length of time that the same signal comparison circuit operates in the offset detection mode in each duty cycle is not limited to be equal to the time length of operation in the signal comparison mode. For example, in some embodiments, the length of time that the same signal comparison circuit operates in the offset detection mode can be adjusted to be longer than the time length of operation in the signal comparison mode in each duty cycle. For another example, in some other embodiments, the duration of the same signal comparison circuit operating in the offset detection mode in each working cycle can be adjusted to be shorter than the duration of operation in the signal comparison mode.

如前所述，三角积分模拟数字转换器100中的所有信号比较电路可设计成具有类似的电路架构与运行方式。以下将以第一信号比较电路130为例，并搭配图3至图5来进一步说明每个信号比较电路的实施方式与运行方式。As mentioned above, all signal comparison circuits in the delta-sigma analog-to-digital converter 100 can be designed to have similar circuit structures and operation modes. The following will take the firstsignal comparison circuit 130 as an example and further illustrate the implementation and operation of each signal comparison circuit with reference to FIG. 3 to FIG. 5 .

图3为图1中的第一信号比较电路130的第一实施例简化后的功能图。图4为第一信号比较电路130操作在偏移检测模式时的简化后运行示意图。图5为第一信号比较电路130操作在信号比较模式时的简化后运行示意图。FIG. 3 is a simplified functional diagram of the first embodiment of the firstsignal comparison circuit 130 in FIG. 1 . FIG. 4 is a simplified operational diagram of the firstsignal comparison circuit 130 operating in the offset detection mode. FIG. 5 is a simplified operational schematic diagram of the firstsignal comparison circuit 130 operating in the signal comparison mode.

在图3的实施例中，第一信号比较电路130的第一比较器132包含有一第一输入端322、一第二输入端324、一第三输入端326、与一第四输入端328。第一信号选择电路134包含有一第一开关电路342与一第二开关电路344。第一补偿电路136包含有一补偿电容362、一第一调整电路364、一第二调整电路366、与一第三开关电路368。In the embodiment of FIG. 3 , thefirst comparator 132 of the firstsignal comparison circuit 130 includes afirst input terminal 322 , asecond input terminal 324 , athird input terminal 326 , and afourth input terminal 328 . The firstsignal selection circuit 134 includes afirst switch circuit 342 and asecond switch circuit 344 . Thefirst compensation circuit 136 includes acompensation capacitor 362 , afirst adjustment circuit 364 , asecond adjustment circuit 366 , and athird switch circuit 368 .

在第一比较器132中，第一输入端322与第二输入端324耦接于第一信号选择电路134，第三输入端326耦接于第一补偿电路136，第四输入端328则耦接于一第一共模信号VCM1。第一比较器132设置成比较第一输入端322与第二输入端324的信号、并同时比较第三输入端326与第四输入端328的信号，以产生一相应的输出信号。第一比较器132的每个输入信号都可以用单端信号(single-ended signal)或差分式信号(differentialsignal)的形式实现。在运行时，前述的第一输入端322、第二输入端324、第三输入端326、与第四输入端328的信号会同时影响第一比较器132所产生的输出信号。实作上，第一比较器132可用各种合适的既有四输入比较器来实现，且第一共模信号VCM1可用第三输入端326与第四输入端328两者之间的共模电压(common mode voltage)信号来实现。In thefirst comparator 132, thefirst input terminal 322 and thesecond input terminal 324 are coupled to the firstsignal selection circuit 134, thethird input terminal 326 is coupled to thefirst compensation circuit 136, and thefourth input terminal 328 is coupled to connected to a first common mode signal VCM1. Thefirst comparator 132 is configured to compare the signals of thefirst input terminal 322 and thesecond input terminal 324 and simultaneously compare the signals of thethird input terminal 326 and thefourth input terminal 328 to generate a corresponding output signal. Each input signal of thefirst comparator 132 can be realized in the form of a single-ended signal or a differential signal. During operation, the aforementioned signals of thefirst input terminal 322 , thesecond input terminal 324 , thethird input terminal 326 , and thefourth input terminal 328 will simultaneously affect the output signal generated by thefirst comparator 132 . In practice, thefirst comparator 132 can be realized by various suitable existing four-input comparators, and the first common-mode signal VCM1 can be realized by the common-mode voltage between thethird input terminal 326 and the fourth input terminal 328 (common mode voltage) signal to achieve.

在第一信号选择电路134中，第一开关电路342耦接于回路滤波器120、第一固定电位信号VF1、与第一比较器132的一第一输入端322之间，并设置成可依据偏移校正电路150的控制，切换第一输入端322所耦接的信号。第二开关电路344耦接于第一参考信号VR1、第一固定电位信号VF1、与第一比较器132的一第二输入端324之间，并设置成可依据偏移校正电路150的控制，切换第二输入端324所耦接的信号。In the firstsignal selection circuit 134, thefirst switch circuit 342 is coupled between theloop filter 120, the first fixed potential signal VF1, and afirst input terminal 322 of thefirst comparator 132, and is configured to The control of the offsetcorrection circuit 150 switches the signal coupled to thefirst input terminal 322 . Thesecond switch circuit 344 is coupled between the first reference signal VR1, the first fixed potential signal VF1, and asecond input terminal 324 of thefirst comparator 132, and is configured to be controlled by the offsetcorrection circuit 150, Switch the signal coupled to thesecond input terminal 324 .

在第一补偿电路136中，补偿电容362的第一端耦接于第三输入端326，且补偿电容362的第二端耦接于一固定电位端(例如，接地端)。第一调整电路364耦接于补偿电容362的第一端，设置成在偏移校正电路150的控制下，对补偿电容362进行充电。第二调整电路366耦接于补偿电容362的第一端，设置成在偏移校正电路150的控制下，对补偿电容362进行放电。第三开关电路368设置成在偏移校正电路150的控制下，选择性地将第一比较器132的第三输入端326耦接至前述的第一共模信号VCM1。In thefirst compensation circuit 136 , the first end of thecompensation capacitor 362 is coupled to thethird input end 326 , and the second end of thecompensation capacitor 362 is coupled to a fixed potential end (eg, ground end). Thefirst adjustment circuit 364 is coupled to the first end of thecompensation capacitor 362 and configured to charge thecompensation capacitor 362 under the control of the offsetcorrection circuit 150 . Thesecond adjustment circuit 366 is coupled to the first end of thecompensation capacitor 362 and configured to discharge thecompensation capacitor 362 under the control of the offsetcorrection circuit 150 . Thethird switch circuit 368 is configured to selectively couple thethird input terminal 326 of thefirst comparator 132 to the aforementioned first common-mode signal VCM1 under the control of the offsetcorrection circuit 150 .

实作上，前述的第一比较器132可用各种合适的既有四输入比较器来实现。第一共模信号VCM1可用第三输入端326与第四输入端328两者之间的共模电压(common modevoltage)信号来实现。第一开关电路342与第二开关电路344皆可用各种合适的晶体管组合来实现。补偿电容362可用各种合适的电容器或电路内部的寄生电容来实现。第三开关电路368可用各种合适的单一晶体管或晶体管组合来实现。第一调整电路364可用合适的电流源(current source)电路来实现。第二调整电路366则可用合适的电流槽(current sink)电路来实现。In practice, the aforementionedfirst comparator 132 can be realized by various suitable existing four-input comparators. The first common mode signal VCM1 can be realized by a common mode voltage signal between thethird input terminal 326 and thefourth input terminal 328 . Both thefirst switch circuit 342 and thesecond switch circuit 344 can be realized by various suitable transistor combinations. Thecompensation capacitor 362 can be realized by various suitable capacitors or parasitic capacitors inside the circuit. Thethird switch circuit 368 can be realized by any suitable single transistor or combination of transistors. Thefirst adjustment circuit 364 can be implemented with a suitable current source circuit. Thesecond adjustment circuit 366 can be realized by a suitable current sink circuit.

如图4所示，在三角积分模拟数字转换器100开始运行时，偏移校正电路150可将第一信号比较电路130先设置成操作在偏移检测模式一段时间(例如，时段T21)。在这段期间，偏移校正电路150可控制第一开关电路342将第一输入端322耦接至第一固定电位信号VF1，控制第二开关电路344将第二输入端324耦接至第一固定电位信号VF1。在第一信号比较电路130第一次操作在偏移检测模式期间，偏移校正电路150还会导通(turn on)第三开关电路368以将第三输入端326耦接至前述的第一共模信号VCM1。因此，第一比较器132的第一输入端322与第二输入端324在这段期间内会形成短路，且第三输入端326与第四输入端328在这段期间内也会形成短路。在此情况下，第一比较器132会比较第一输入端322的信号与第二输入端324的信号，也会比较第三输入端326的信号与第四输入端328的信号，并根据前述的两种比较结果产生与滤波信号SF及第一参考信号VR1的相对大小无关的相应误差信号，亦即前述的第一误差信号ERR1。As shown in FIG. 4 , when the delta-sigma ADC 100 starts to operate, the offsetcorrection circuit 150 can first set the firstsignal comparison circuit 130 to operate in the offset detection mode for a period of time (eg, period T21 ). During this period, the offsetcorrection circuit 150 can control thefirst switch circuit 342 to couple thefirst input terminal 322 to the first fixed potential signal VF1, and control thesecond switch circuit 344 to couple thesecond input terminal 324 to the first fixed potential signal VF1. Fixed potential signal VF1. During the first time when the firstsignal comparison circuit 130 is operating in the offset detection mode, the offsetcorrection circuit 150 will also turn on thethird switch circuit 368 to couple thethird input terminal 326 to the aforementioned first Common-mode signal VCM1. Therefore, thefirst input terminal 322 and thesecond input terminal 324 of thefirst comparator 132 will form a short circuit during this period, and thethird input terminal 326 and thefourth input terminal 328 will also form a short circuit during this period. In this case, thefirst comparator 132 will compare the signal of thefirst input terminal 322 and the signal of thesecond input terminal 324, and also compare the signal of thethird input terminal 326 and the signal of thefourth input terminal 328, and according to the aforementioned The two comparison results generate a corresponding error signal that is independent of the relative magnitudes of the filtered signal SF and the first reference signal VR1 , that is, the aforementioned first error signal ERR1 .

在第一信号比较电路130操作在偏移检测模式的期间(例如，时段T21)，偏移校正电路150根据当次操作产生出的第一误差信号ERR1的极性控制第一调整电路364对补偿电容362进行充电、或是控制第二调整电路366对补偿电容362进行放电，以对第一比较器132的第三输入端326施加一补偿信号，以校正第一比较器132的信号偏移情况。在运行时，偏移校正电路150可将第一调整电路364每次的充电量设置为一固定量、和/或将第二调整电路366每次的放电量设置为一固定量。During the period when the firstsignal comparison circuit 130 is operating in the offset detection mode (for example, period T21), the offsetcorrection circuit 150 controls thefirst adjustment circuit 364 to compensate Thecapacitor 362 is charged, or thesecond adjustment circuit 366 is controlled to discharge thecompensation capacitor 362, so as to apply a compensation signal to thethird input terminal 326 of thefirst comparator 132 to correct the signal offset of thefirst comparator 132 . During operation, the offsetcorrection circuit 150 can set the charge amount of thefirst adjustment circuit 364 to a fixed amount each time, and/or set the discharge amount of thesecond adjustment circuit 366 to a fixed amount each time.

接着，如图5所示，偏移校正电路150可将第一信号比较电路130切换至信号比较模式运行一段时间(例如，时段T22)。在这段期间，偏移校正电路150可控制第一开关电路342将第一输入端322耦接至滤波信号SF，控制第二开关电路344将第二输入端324耦接至第一参考信号VR1，并关断(turn off)第三开关电路368。另一方面，控制偏移校正电路150在这段期间会控制第一调整电路364与第二调整电路366停止对补偿电容362进行充电/放电运行。在信号比较模式中，第一比较器132会比较滤波信号SF与第一参考信号VR1，以产生与滤波信号SF及第一参考信号VR1的相对大小对应的一第一比较信号CMP1。在这段期间，第一补偿电路136也会持续对第三输入端326的信号进行补偿，所以第一比较器132所产生的第一比较信号CMP1的极性，在某种程度上也会反映出第三输入端326被施加补偿信号后的信号偏移情况。Next, as shown in FIG. 5 , the offsetcorrection circuit 150 can switch the firstsignal comparison circuit 130 to the signal comparison mode to run for a period of time (eg, period T22 ). During this period, the offsetcorrection circuit 150 can control thefirst switch circuit 342 to couple thefirst input terminal 322 to the filter signal SF, and control thesecond switch circuit 344 to couple thesecond input terminal 324 to the first reference signal VR1 , and turn off thethird switch circuit 368 . On the other hand, the control offsetcorrection circuit 150 controls thefirst adjustment circuit 364 and thesecond adjustment circuit 366 to stop charging/discharging thecompensation capacitor 362 during this period. In the signal comparison mode, thefirst comparator 132 compares the filtered signal SF and the first reference signal VR1 to generate a first comparison signal CMP1 corresponding to the relative magnitudes of the filtered signal SF and the first reference signal VR1. During this period, thefirst compensation circuit 136 will also continue to compensate the signal at thethird input terminal 326, so the polarity of the first comparison signal CMP1 generated by thefirst comparator 132 will also reflect to some extent The signal deviation after the compensation signal is applied to thethird input terminal 326 is shown.

之后，如图6所示，偏移校正电路150可将第一信号比较电路130切换至偏移检测模式运行一段时间(例如，时段T23)。在这段期间，偏移校正电路150对于第一信号选择电路134与第一补偿电路136的控制方式，大致上与前一次将第一信号比较电路130设置成偏移检测模式时类似。差别在于，偏移校正电路150在前述第一次将第一信号比较电路130设置成偏移检测模式时，会将第三开关电路368导通，但在那之后每次偏移校正电路150将第一信号比较电路130切换至偏移检测模式时，都会关断第三开关电路368。换言之，在时段T23中，第三开关电路368会处于关断状态。Afterwards, as shown in FIG. 6 , the offsetcorrection circuit 150 may switch the firstsignal comparison circuit 130 to the offset detection mode to run for a period of time (eg, period T23 ). During this period, the control mode of the offsetcorrection circuit 150 for the firstsignal selection circuit 134 and thefirst compensation circuit 136 is substantially similar to that when the firstsignal comparison circuit 130 was set to the offset detection mode last time. The difference is that the offsetcorrection circuit 150 will turn on thethird switch circuit 368 when the firstsignal comparison circuit 130 is set to the offset detection mode for the first time, but after that each time the offsetcorrection circuit 150 will When the firstsignal comparison circuit 130 switches to the offset detection mode, thethird switch circuit 368 is turned off. In other words, during the time period T23, thethird switch circuit 368 is in an off state.

在时段T23中，第一比较器132的第一输入端322与第二输入端324同样会形成短路，但第三输入端326与第四输入端328并不会形成短路。在这段期间，第一补偿电路136会持续对第三输入端326进行信号补偿。In the time period T23 , thefirst input terminal 322 and thesecond input terminal 324 of thefirst comparator 132 also form a short circuit, but thethird input terminal 326 and thefourth input terminal 328 do not form a short circuit. During this period, thefirst compensation circuit 136 continues to perform signal compensation on thethird input terminal 326 .

同样地，第一比较器132在时段T23中会比较第一输入端322的信号与第二输入端324的信号，也会比较第三输入端326的信号与第四输入端328的信号，并根据前述的两种比较结果产生与滤波信号SF及第一参考信号VR1的相对大小无关的第一误差信号ERR1。Similarly, thefirst comparator 132 will compare the signal of thefirst input terminal 322 and the signal of thesecond input terminal 324 in the period T23, and also compare the signal of thethird input terminal 326 and the signal of thefourth input terminal 328, and According to the aforementioned two comparison results, the first error signal ERR1 is generated regardless of the relative magnitudes of the filter signal SF and the first reference signal VR1.

偏移校正电路150通过检测第一信号比较电路130于每次偏移检测模式中所输出的第一误差信号ERR1的极性来决定每次的补偿方向，例如当本次偏移检测模式产生的第一误差信号ERR1的极性为负，偏移校正电路150便控制第一调整电路364对补偿电容362进行充电；若本次偏移检测模式产生的第一误差信号ERR1的极性为正，偏移校正电路150便控制第二调整电路366对补偿电容362进行放电，从而调整对第一比较器132的第三输入端326所施加的信号补偿量，借此降低第一比较器132的信号偏移情况。The offsetcorrection circuit 150 determines the compensation direction each time by detecting the polarity of the first error signal ERR1 output by the firstsignal comparison circuit 130 in each offset detection mode, for example, when the current offset detection mode generates The polarity of the first error signal ERR1 is negative, and the offsetcorrection circuit 150 controls thefirst adjustment circuit 364 to charge thecompensation capacitor 362; if the polarity of the first error signal ERR1 generated in this offset detection mode is positive, The offsetcorrection circuit 150 controls thesecond adjustment circuit 366 to discharge thecompensation capacitor 362, thereby adjusting the signal compensation amount applied to thethird input terminal 326 of thefirst comparator 132, thereby reducing the signal of thefirst comparator 132 Offset situation.

接下来，在后续三角积分模拟数字转换器100进行模拟至数字转换的信号处理过程中，偏移校正电路150可反复进行前述时段T22与时段T23的运行，以间歇性检测并动态校正第一信号比较电路130中的第一比较器132的信号偏移情况。Next, during the signal processing process of the subsequent analog-to-digital conversion by the delta-sigma analog-to-digital converter 100, the offsetcorrection circuit 150 can repeatedly perform the operation of the aforementioned period T22 and period T23 to intermittently detect and dynamically correct the first signal The signal deviation of thefirst comparator 132 in thecomparison circuit 130 .

同样地，偏移校正电路150可采用前述方式，间歇性检测第二信号比较电路140中的第二比较器142的信号偏移情况，并动态控制第二补偿电路146对第二比较器142的输入端施加补偿信号，以校正第二比较器142的信号偏移情况。Similarly, the offsetcorrection circuit 150 can use the aforementioned method to intermittently detect the signal offset of thesecond comparator 142 in the secondsignal comparison circuit 140, and dynamically control thesecond compensation circuit 146 to thesecond comparator 142. A compensation signal is applied to the input to correct the signal offset of thesecond comparator 142 .

由前述说明可知，偏移校正电路150会间歇性检测每个信号比较电路中的比较器的信号偏移情况，并动态控制个别补偿电路对相应比较器的输入端施加补偿信号，以校正三角积分模拟数字转换器100中的比较器的信号偏移情况。It can be seen from the foregoing description that the offsetcorrection circuit 150 will intermittently detect the signal offset of the comparators in each signal comparison circuit, and dynamically control the individual compensation circuits to apply compensation signals to the input terminals of the corresponding comparators to correct the delta-sigma The signal offset of the comparator in the analog-to-digital converter 100 .

由于不同比较器的信号偏移情况有所不同，所以在同一时间点中，前述的第一补偿电路136对第一比较器132的输入端所施加的补偿信号量，很可能会与前述的第二补偿电路146对第二比较器142的输入端所施加的补偿信号量不同。Since the signal offsets of different comparators are different, at the same time point, the amount of compensation signal applied by the aforementionedfirst compensation circuit 136 to the input terminal of thefirst comparator 132 is likely to be different from that of the aforementionedfirst comparator 132. The twocompensation circuits 146 apply different compensation signals to the input terminals of thesecond comparator 142 .

另一方面，由于偏移校正电路150在每次信号比较电路操作在偏移检测模式时，都会对该信号比较电路中的补偿电路进行调整，且调整的方向可能与前一次相同、也可能与前一次不同。因此，同一个比较器所接收到的输入信号补偿量，并非固定不变，而是会随着时间呈现持续略微波动的变化，且其变化方式类似于噪声。On the other hand, because the offsetcorrection circuit 150 will adjust the compensation circuit in the signal comparison circuit every time the signal comparison circuit operates in the offset detection mode, and the adjustment direction may be the same as the previous time, or may be the same as the previous time. The previous time was different. Therefore, the compensation amount of the input signal received by the same comparator is not fixed, but will show continuous and slightly fluctuating changes over time, and the change method is similar to noise.

例如，前述第一补偿电路136对于第一比较器132的输入端施加补偿信号的运行，在某种程度上恰好可等效为是在第一比较器132的输入端施加类似噪声的抖动信号(dithering signal)。For example, the aforementioned operation of the first compensatingcircuit 136 to apply a compensation signal to the input terminal of thefirst comparator 132 can be equivalent to applying a dithering signal similar to noise to the input terminal of the first comparator 132 ( dithering signal).

又例如，前述第二补偿电路146对于第二比较器142的输入端施加补偿信号的运行，在某种程度恰好上也可等效为是在第二比较器142的输入端施加类似噪声的抖动信号。As another example, the operation of the aforementionedsecond compensation circuit 146 applying a compensation signal to the input terminal of thesecond comparator 142 can also be equivalent to applying noise-like jitter to the input terminal of thesecond comparator 142 to a certain extent. Signal.

因此，在前述三角积分模拟数字转换器100的第一信号比较电路130与回路滤波器120之间的信号路径上，无需耦接任何传统的抖动信号产生电路(dither signalgenerating circuit)，便可有效避免或减轻第一比较器132输出空闲音(idle tone)的可能性。Therefore, on the signal path between the firstsignal comparison circuit 130 and theloop filter 120 of the aforementioned delta-sigma analog-to-digital converter 100, there is no need to couple any traditional dither signal generating circuit (dither signal generating circuit), which can effectively avoid Or reduce the possibility of thefirst comparator 132 outputting an idle tone.

同样地，在第二信号比较电路140与回路滤波器120之间的信号路径上，无需耦接任何传统的抖动信号产生电路，便可有效避免或减轻第二比较器142输出空闲音的可能性。Likewise, on the signal path between the secondsignal comparison circuit 140 and theloop filter 120, there is no need to couple any traditional jitter signal generating circuit, so that the possibility of thesecond comparator 142 outputting idle tones can be effectively avoided or reduced. .

在前述的实施例中，偏移校正电路150会将第一信号比较电路130与第二信号比较电路140同步切换至偏移检测模式，也会将第一信号比较电路130与第二信号比较电路140同步切换至信号比较模式。但这只是一示例性运行方式，而非局限本发明的实际实施方式。In the foregoing embodiments, the offsetcorrection circuit 150 will switch the firstsignal comparison circuit 130 and the secondsignal comparison circuit 140 to the offset detection mode synchronously, and will also switch the firstsignal comparison circuit 130 and the secondsignal comparison circuit 140 switches to signal comparison mode synchronously. But this is just an exemplary operation mode, rather than limiting the actual implementation mode of the present invention.

例如，图7所示出为图1中的三角积分模拟数字转换器100简化后的第二实施例运行时序图。For example, FIG. 7 shows a simplified operational timing diagram of the second embodiment of the delta-sigma analog-to-digital converter 100 in FIG. 1 .

在图7的实施例中，偏移校正电路150会控制所有信号比较电路在相同的时段同步操作在信号比较模式，但会把不同信号比较电路操作在偏移检测模式的时段设置成不相同。例如，如图7所示，偏移校正电路150可在时段T71将第一信号比较电路130设置成操作在偏移检测模式，并在之后的时段T72才把第二信号比较电路140设置成操作在偏移检测模式。接着，在时段T73中，偏移校正电路150会控制所有信号比较电路都操作在信号比较模式。在另一实施例中，偏移校正电路150可在时段T71将第一信号比较电路130设置成操作在偏移检测模式，接着在时段T73中控制所有信号比较电路都操作在信号比较模式，并在下一个工作时钟周期中的时段T74才把第二信号比较电路140设置成操作在偏移检测模式。In the embodiment of FIG. 7 , the offsetcorrection circuit 150 controls all the signal comparison circuits to operate in the signal comparison mode synchronously at the same time period, but sets different time periods for different signal comparison circuits to operate in the offset detection mode. For example, as shown in FIG. 7, the offsetcorrection circuit 150 can set the firstsignal comparison circuit 130 to operate in the offset detection mode during the period T71, and then set the secondsignal comparison circuit 140 to operate in the subsequent period T72. in offset detection mode. Next, in the period T73, the offsetcorrection circuit 150 controls all the signal comparison circuits to operate in the signal comparison mode. In another embodiment, the offsetcorrection circuit 150 may set the firstsignal comparison circuit 130 to operate in the offset detection mode during the period T71, and then control all the signal comparison circuits to operate in the signal comparison mode during the period T73, and The secondsignal comparison circuit 140 is set to operate in the offset detection mode only during the period T74 in the next working clock cycle.

接下来，偏移校正电路150可在时段T74将第一信号比较电路130设置成操作在偏移检测模式，并在之后的时段T75才把第二信号比较电路140设置成操作在偏移检测模式。Next, the offsetcorrection circuit 150 may set the firstsignal comparison circuit 130 to operate in the offset detection mode during the period T74, and then set the secondsignal comparison circuit 140 to operate in the offset detection mode in the subsequent period T75. .

换言之，第一信号比较电路130与第二信号比较电路140被切换至偏移检测模式的时序可以有所不同，而且处于偏移检测模式的时间长度也可以有所不同。这样的运行方式可减轻偏移校正电路150在同一时段中的运算负担，可降低对于偏移校正电路150的运算能力要求，所以偏移校正电路150可用较精简的电路架构来实现。In other words, the timing at which the firstsignal comparison circuit 130 and the secondsignal comparison circuit 140 are switched to the offset detection mode may be different, and the time lengths in the offset detection mode may also be different. Such an operation mode can reduce the computation burden of the offsetcorrection circuit 150 in the same period, and can reduce the computation capacity requirement for the offsetcorrection circuit 150 , so the offsetcorrection circuit 150 can be implemented with a simpler circuit architecture.

另外，在前述的实施例中，第一补偿电路136会包含有补偿电容362、第一调整电路364、第二调整电路366、与第三开关电路368。但这只是一示例性架构，而非局限本发明的实施方式。In addition, in the foregoing embodiments, thefirst compensation circuit 136 includes acompensation capacitor 362 , afirst adjustment circuit 364 , asecond adjustment circuit 366 , and athird switch circuit 368 . But this is just an exemplary architecture, not limiting the implementation of the present invention.

例如，图8为图1中的第一信号比较电路130的第二实施例简化后的功能图。在图8的实施例中，第一补偿电路136中省略了前述的第三开关电路368。For example, FIG. 8 is a simplified functional diagram of the second embodiment of the firstsignal comparison circuit 130 in FIG. 1 . In the embodiment of FIG. 8 , the aforementionedthird switch circuit 368 is omitted from thefirst compensation circuit 136 .

在此情况下，偏移校正电路150可在第一次将第一信号比较电路130设置成偏移检测模式时，控制第一调整电路364对补偿电容362进行充电、或是控制第二调整电路366对补偿电容362进行放电，以对第一比较器132的第三输入端326施加一预定的信号补偿量。通过反复进行前述时段T22与时段T23的运行，同样可有效校正第一信号比较电路130中的第一比较器132的信号偏移情况，但达到稳态所需的时间可能会比前图3的实施例略长一些。In this case, the offsetcorrection circuit 150 can control thefirst adjustment circuit 364 to charge thecompensation capacitor 362 or control thesecond adjustment circuit 364 when the firstsignal comparison circuit 130 is set to the offset detection mode for the first time. 366 discharges thecompensation capacitor 362 to apply a predetermined signal compensation amount to thethird input terminal 326 of thefirst comparator 132 . By repeating the operation of the aforementioned period T22 and period T23, the signal offset of thefirst comparator 132 in the firstsignal comparison circuit 130 can also be effectively corrected, but the time required to reach a steady state may be longer than that of the previous FIG. 3 The example is slightly longer.

又例如，图9为图1中的第一信号比较电路130的第三实施例简化后的功能图。在图9的实施例中，第一补偿电路136中省略了前述的第二调整电路366与第三开关电路368。For another example, FIG. 9 is a simplified functional diagram of the third embodiment of the firstsignal comparison circuit 130 in FIG. 1 . In the embodiment of FIG. 9 , the aforementionedsecond adjustment circuit 366 andthird switch circuit 368 are omitted from thefirst compensation circuit 136 .

在此情况下，偏移校正电路150可在第一次将第一信号比较电路130设置成偏移检测模式时，控制第一调整电路364对补偿电容362进行充电，以对第一比较器132的第三输入端326施加一预定的信号补偿量。通过反复进行前述时段T22与时段T23的运行，同样可校正第一信号比较电路130中的第一比较器132的信号偏移情况，但达到稳态的时间所需的时间可能会比前述图8的实施例稍长一些。In this case, the offsetcorrection circuit 150 can control thefirst adjustment circuit 364 to charge thecompensation capacitor 362 to charge thefirst comparator 132 when the firstsignal comparison circuit 130 is set to the offset detection mode for the first time. Thethird input terminal 326 applies a predetermined amount of signal compensation. By repeatedly performing the operation of the aforementioned period T22 and period T23, the signal offset of thefirst comparator 132 in the firstsignal comparison circuit 130 can also be corrected, but the time required to reach a steady state may be longer than the aforementioned FIG. 8 The example is slightly longer.

请注意，三角积分模拟数字转换器100中的信号比较电路的数量并不局限于前述实施例。实作上，可依电路需求增加三角积分模拟数字转换器100中的信号比较电路数量。在某些实施例中，亦可将三角积分模拟数字转换器100中的信号比较电路的数量减少至只有一个，以简化整体电路的架构。Please note that the number of signal comparison circuits in the delta-sigma analog-to-digital converter 100 is not limited to the foregoing embodiments. In practice, the number of signal comparison circuits in the delta-sigma analog-to-digital converter 100 can be increased according to circuit requirements. In some embodiments, the number of signal comparison circuits in the delta-sigma analog-to-digital converter 100 can also be reduced to only one, so as to simplify the structure of the overall circuit.

此外，各个信号比较电路中的比较器(例如，前述的第一比较器132、第二比较器142)的输入端数量，可依电路需求扩充到更多个数，而不局限于前述实施例中的4个。In addition, the number of input terminals of the comparators (for example, the aforementionedfirst comparator 132 and the second comparator 142) in each signal comparison circuit can be expanded to more numbers according to circuit requirements, and is not limited to the aforementioned embodiments. 4 of them.

在某些实施例中，亦可在前述第一比较器132的第四输入端328额外耦接一组与第一补偿电路136架构相同、但补偿方向相反的补偿电路。在某些实施例中，亦可将前述的第一补偿电路136改为耦接于第一比较器132的第四输入端328。在某些实施例中，亦可改为将第一比较器132的第三输入端326与第四输入端328同时耦接于能够提供类似前述第一补偿电路136的信号补偿功能的切换式电容(switched-capacitor)电路。同样地，其他信号比较电路中的比较器的输入端所耦接的补偿电路，亦可按照前述变化方式加以修改。In some embodiments, a set of compensation circuits having the same structure as thefirst compensation circuit 136 but opposite to the compensation direction can also be coupled to thefourth input terminal 328 of thefirst comparator 132 . In some embodiments, the aforementionedfirst compensation circuit 136 can also be changed to be coupled to thefourth input terminal 328 of thefirst comparator 132 . In some embodiments, thethird input terminal 326 and thefourth input terminal 328 of thefirst comparator 132 may also be coupled to a switched capacitor capable of providing a signal compensation function similar to that of thefirst compensation circuit 136 described above. (switched-capacitor) circuit. Similarly, the compensation circuit coupled to the input terminal of the comparator in other signal comparison circuits can also be modified according to the aforementioned variation.

由前述说明可知，偏移校正电路150可有效校正三角积分模拟数字转换器100中的每个信号比较电路的信号偏移情况，所以能改善三角积分模拟数字转换器100的整体效能。It can be known from the foregoing description that the offsetcorrection circuit 150 can effectively correct the signal offset of each signal comparison circuit in the delta-sigma analog-to-digital converter 100 , so the overall performance of the delta-sigma analog-to-digital converter 100 can be improved.

另外，偏移校正电路150控制前述补偿电路对相关比较器的输入端施加补偿信号的动作，恰好可等效为是在比较器的输入端施加类似噪声的抖动信号，所以能同时有效避免或减轻三角积分模拟数字转换器100中的比较器输出空闲音的可能性。因此，在三角积分模拟数字转换器100中无需设置额外的抖动信号产生电路，可简化电路的复杂度。In addition, the action of the offsetcorrection circuit 150 controlling the above-mentioned compensation circuit to apply the compensation signal to the input terminal of the relevant comparator is just equivalent to applying a jitter signal similar to noise to the input terminal of the comparator, so it can effectively avoid or reduce the The probability that the comparator in the delta-sigma analog-to-digital converter 100 outputs an idle tone. Therefore, there is no need to set an additional jitter signal generating circuit in the delta-sigma analog-to-digital converter 100 , which can simplify the complexity of the circuit.

在说明书及权利要求中使用了某些词汇来指称特定的元件，而本领域内的技术人员可能会用不同的名词来称呼同样的元件。本说明书及权利要求并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的基准。在说明书及权利要求中所提及的“包含”为开放式的用语，应解释成“包含但不限定于”。另外，“耦接”一词在此包含任何直接及间接的连接手段。因此，若文中描述第一元件耦接于第二元件，则代表第一元件可通过电性连接或无线传输、光学传输等信号连接方式而直接地连接于第二元件，或通过其它元件或连接手段间接地电性或信号连接至第二元件。Certain terms are used in the specification and claims to refer to specific elements, but those skilled in the art may use different terms to refer to the same element. The specification and claims do not use the difference in name as the way to distinguish components, but the difference in function of the components as the basis for distinction. The "comprising" mentioned in the description and the claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection means such as wireless transmission or optical transmission, or through other elements or connections. The means is indirectly electrically or signally connected to the second element.

在说明书中所使用的“和/或”的描述方式，包含所列举的其中一个项目或多个项目的任意组合。另外，除非说明书中特别指明，否则任何单数的用语都同时包含复数的含义。The description of "and/or" used in the specification includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular terms include plural meanings at the same time.

说明书及权利要求中的“电压信号”，在实作上可采用电压形式或电流形式来实现。说明书及权利要求中的“电流信号”，在实作上也可用电压形式或电流形式来实现。The "voltage signal" in the specification and claims can be implemented in the form of voltage or current in practice. The "current signal" in the specification and claims can also be realized in the form of voltage or current in practice.

以上仅为本发明的优选实施例，凡依本发明权利要求所做的等效变化与修改，皆应属本发明的涵盖范围。The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

Translated fromChinese

1.一种三角积分模拟数字转换器(100)，包含：1. A delta-sigma analog-to-digital converter (100), comprising:一减法器(110)，设置成从一模拟输入信号(Sin)中减去一反馈信号(Sfb)；a subtractor (110) arranged to subtract a feedback signal (Sfb) from an analog input signal (Sin);一回路滤波器(120)，耦接于该减法器(110)，设置成处理该减法器(110)的输出信号以产生一滤波信号(SF)；a loop filter (120), coupled to the subtractor (110), configured to process the output signal of the subtractor (110) to generate a filtered signal (SF);一第一信号比较电路(130)，耦接于该回路滤波器(120)与一第一参考信号(VR1)，设置成可选择性地操作在一偏移检测模式或一信号比较模式，其中，该第一信号比较电路(130)操作在该偏移检测模式时产生与该滤波信号(SF)及该第一参考信号(VR1)的相对大小无关的一第一误差信号(ERR1)，而操作在该信号比较模式时则产生与该滤波信号(SF)及该第一参考信号(VR1)的相对大小对应的一第一比较信号(CMP1)；a first signal comparison circuit (130), coupled to the loop filter (120) and a first reference signal (VR1), configured to selectively operate in an offset detection mode or a signal comparison mode, wherein , the first signal comparison circuit (130) operates in the offset detection mode to generate a first error signal (ERR1) independent of the relative magnitudes of the filtered signal (SF) and the first reference signal (VR1), and When operating in the signal comparison mode, a first comparison signal (CMP1) corresponding to the relative magnitudes of the filtered signal (SF) and the first reference signal (VR1) is generated;一偏移校正电路(150)，耦接于该第一信号比较电路(130)，设置成依据该第一误差信号(ERR1)校正该第一信号比较电路(130)的偏移情况，并控制该第一信号比较电路(130)在该偏移检测模式与该信号比较模式之间交替切换；以及an offset correction circuit (150), coupled to the first signal comparison circuit (130), configured to correct the offset of the first signal comparison circuit (130) according to the first error signal (ERR1), and control the first signal comparison circuit (130) alternately switches between the offset detection mode and the signal comparison mode; and一数字模拟转换器(160)，耦接于该第一信号比较电路(130)的输出端与该减法器(110)，设置成依据该第一比较信号(CMP1)产生该反馈信号(Sfb)，a digital-to-analog converter (160), coupled to the output terminal of the first signal comparison circuit (130) and the subtractor (110), configured to generate the feedback signal (Sfb) according to the first comparison signal (CMP1) ,其中，该第一信号比较电路(130)包含有：Wherein, the first signal comparison circuit (130) includes:一第一比较器(132)，具有一第一输入端(322)、一第二输入端(324)、一第三输入端(326)、与一第四输入端(328)，设置成比较该第一输入端(322)与该第二输入端(324)的信号、并比较该第三输入端(326)与该第四输入端(328)的信号，以产生一相应的输出信号，其中，该第四输入端(328)耦接于一第一共模信号(VCM1)；和A first comparator (132), has a first input terminal (322), a second input terminal (324), a third input terminal (326), and a fourth input terminal (328), arranged to compare the signals of the first input terminal (322) and the second input terminal (324), and comparing the signals of the third input terminal (326) and the fourth input terminal (328) to generate a corresponding output signal, Wherein, the fourth input terminal (328) is coupled to a first common mode signal (VCM1); and一第一信号选择电路(134)，耦接于该回路滤波器(120)、该第一比较器(132)的该第一输入端(322)、该第一比较器(132)的该第二输入端(324)、该偏移校正电路(150)、该第一参考信号(VR1)、与一第一固定电位信号(VF1)，其中，在该偏移检测模式中，该第一信号选择电路(134)将该第一输入端(322)与该第二输入端(324)都耦接至该第一固定电位信号(VF1)，使该第一比较器(132)产生该第一误差信号(ERR1)，而在该信号比较模式中，该第一信号选择电路(134)改为将该第一输入端(322)与该第二输入端(324)分别耦接至该滤波信号(SF)与该第一参考信号(VR1)，使该第一比较器(132)产生该第一比较信号(CMP1)。A first signal selection circuit (134), coupled to the loop filter (120), the first input terminal (322) of the first comparator (132), and the first input terminal (322) of the first comparator (132) Two input terminals (324), the offset correction circuit (150), the first reference signal (VR1), and a first fixed potential signal (VF1), wherein, in the offset detection mode, the first signal The selection circuit (134) couples both the first input terminal (322) and the second input terminal (324) to the first fixed potential signal (VF1), so that the first comparator (132) generates the first error signal (ERR1), and in the signal comparison mode, the first signal selection circuit (134) instead couples the first input terminal (322) and the second input terminal (324) to the filtered signal (SF) and the first reference signal (VR1), make the first comparator (132) generate the first comparison signal (CMP1).2.如权利要求1所述的三角积分模拟数字转换器(100)，其中，该第一信号比较电路(130)还包含有：2. The delta-sigma analog-to-digital converter (100) as claimed in claim 1, wherein, the first signal comparison circuit (130) also includes:一第一补偿电路(136)，耦接于该第一比较器(132)的该第三输入端(326)与该偏移校正电路(150)，设置成依据该偏移校正电路(150)的控制，对该第一比较器(132)的该第三输入端(326)进行信号补偿；A first compensation circuit (136), coupled to the third input terminal (326) of the first comparator (132) and the offset correction circuit (150), configured to be based on the offset correction circuit (150) The control of this first comparator (132) this 3rd input end (326) carries out signal compensation;其中，该偏移校正电路(150)还设置成在一工作时钟(CLK)的每一预定数量的工作周期中，控制该第一信号选择电路(134)切换至该偏移检测模式至少一次、也切换至该信号比较模式至少一次，且该偏移校正电路(150)还设置成依据该第一误差信号(ERR1)调整该第一补偿电路(136)的信号补偿量。Wherein, the offset correction circuit (150) is further configured to control the first signal selection circuit (134) to switch to the offset detection mode at least once in every predetermined number of working cycles of a working clock (CLK), Also switch to the signal comparison mode at least once, and the offset correction circuit (150) is also configured to adjust the signal compensation amount of the first compensation circuit (136) according to the first error signal (ERR1).3.如权利要求2所述的三角积分模拟数字转换器(100)，其中，该第一信号选择电路(134)包含有：3. The delta-sigma analog-to-digital converter (100) as claimed in claim 2, wherein the first signal selection circuit (134) comprises:一第一开关电路(342)，耦接于该回路滤波器(120)、该第一固定电位信号(VF1)、与该第一输入端(322)之间，并受控于该偏移校正电路(150)；以及a first switch circuit (342), coupled between the loop filter (120), the first fixed potential signal (VF1), and the first input terminal (322), and controlled by the offset correction circuit (150); and一第二开关电路(344)，耦接于该第一参考信号(VR1)、该第一固定电位信号(VF1)、与该第二输入端(324)之间，并受控于该偏移校正电路(150)；a second switch circuit (344), coupled between the first reference signal (VR1), the first fixed potential signal (VF1), and the second input terminal (324), and controlled by the offset Correction circuit (150);其中，在该偏移检测模式中，该偏移校正电路(150)控制该第一开关电路(342)将该第一输入端(322)耦接至该第一固定电位信号(VF1)，并控制该第二开关电路(344)将该第二输入端(324)耦接至该第一固定电位信号(VF1)；而在该信号比较模式中，该偏移校正电路(150)控制该第一开关电路(342)将该第一输入端(322)耦接至该滤波信号(SF)，并控制该第二开关电路(344)将该第二输入端(324)耦接至该第一参考信号(VR1)。Wherein, in the offset detection mode, the offset correction circuit (150) controls the first switch circuit (342) to couple the first input terminal (322) to the first fixed potential signal (VF1), and controlling the second switch circuit (344) to couple the second input terminal (324) to the first fixed potential signal (VF1); and in the signal comparison mode, the offset correction circuit (150) controls the first A switch circuit (342) couples the first input terminal (322) to the filtered signal (SF), and controls the second switch circuit (344) to couple the second input terminal (324) to the first Reference signal (VR1).4.如权利要求3所述的三角积分模拟数字转换器(100)，其中，该第一补偿电路(136)包含有：4. The delta-sigma analog-to-digital converter (100) as claimed in claim 3, wherein the first compensation circuit (136) comprises:一补偿电容(362)，其中，该补偿电容(362)的第一端耦接于该第三输入端(326)，且该补偿电容(362)的第二端耦接于一固定电位端；以及A compensation capacitor (362), wherein the first terminal of the compensation capacitor (362) is coupled to the third input terminal (326), and the second terminal of the compensation capacitor (362) is coupled to a fixed potential terminal; as well as一第一调整电路(364)，耦接于该补偿电容(362)的第一端，设置成在该偏移校正电路(150)的控制下，对该补偿电容(362)进行充电。A first adjustment circuit (364), coupled to the first end of the compensation capacitor (362), is configured to charge the compensation capacitor (362) under the control of the offset correction circuit (150).5.如权利要求4所述的三角积分模拟数字转换器(100)，其中，该第一补偿电路(136)还包含有：5. The delta-sigma analog-to-digital converter (100) as claimed in claim 4, wherein, the first compensation circuit (136) further comprises:一第二调整电路(366)，耦接于该补偿电容(362)的第一端，设置成在该偏移校正电路(150)的控制下，对该补偿电容(362)进行放电。A second adjustment circuit (366), coupled to the first end of the compensation capacitor (362), is configured to discharge the compensation capacitor (362) under the control of the offset correction circuit (150).6.如权利要求5所述的三角积分模拟数字转换器(100)，其中，该第一补偿电路(136)还包含有：6. The delta-sigma analog-to-digital converter (100) as claimed in claim 5, wherein, the first compensation circuit (136) further comprises:一第三开关电路(368)，设置成在该偏移校正电路(150)的控制下，选择性地将该第一比较器(132)的该第三输入端(326)耦接至该第一共模信号(VCM1)。a third switch circuit (368), configured to selectively couple the third input terminal (326) of the first comparator (132) to the first comparator (132) under the control of the offset correction circuit (150); A common-mode signal (VCM1).7.如权利要求4所述的三角积分模拟数字转换器(100)，其中，该第一补偿电路(136)还包含有：7. The delta-sigma analog-to-digital converter (100) as claimed in claim 4, wherein, the first compensation circuit (136) further comprises:一第三开关电路(368)，设置成在该偏移校正电路(150)的控制下，选择性地将该第一比较器(132)的该第三输入端(326)耦接至该第一共模信号(VCM1)。a third switch circuit (368), configured to selectively couple the third input terminal (326) of the first comparator (132) to the first comparator (132) under the control of the offset correction circuit (150); A common-mode signal (VCM1).8.如权利要求2所述的三角积分模拟数字转换器(100)，还包含：8. The delta-sigma analog-to-digital converter (100) as claimed in claim 2, further comprising:一第二信号比较电路(140)，耦接于该回路滤波器(120)、该偏移校正电路(150)、该数字模拟转换器(160)、与一第二参考信号(VRn)，设置成可选择性地操作在该偏移检测模式或该信号比较模式，其中，该第二信号比较电路(140)操作在该偏移检测模式时产生与该滤波信号(SF)及该第二参考信号(VRn)的相对大小无关的一第二误差信号(ERRn)，而操作在该信号比较模式时则产生与该滤波信号(SF)及该第二参考信号(VRn)的相对大小对应的一第二比较信号(CMPn)；A second signal comparison circuit (140), coupled to the loop filter (120), the offset correction circuit (150), the digital-to-analog converter (160), and a second reference signal (VRn), set be selectively operable in the offset detection mode or the signal comparison mode, wherein the second signal comparison circuit (140) operates in the offset detection mode to generate the filtered signal (SF) and the second reference A second error signal (ERRn) that is independent of the relative magnitude of the signal (VRn), while operating in the signal comparison mode produces a signal corresponding to the relative magnitudes of the filtered signal (SF) and the second reference signal (VRn). a second comparison signal (CMPn);其中，该偏移校正电路(150)还设置成依据该第二误差信号(ERRn)校正该第二信号比较电路(140)的偏移情况，并控制该第二信号比较电路(140)在该偏移检测模式与该信号比较模式之间交替切换，且该数字模拟转换器(160)还设置成依据该第二比较信号(CMPn)产生该反馈信号(Sfb)。Wherein, the offset correcting circuit (150) is further configured to correct the offset of the second signal comparing circuit (140) according to the second error signal (ERRn), and control the second signal comparing circuit (140) in the The offset detection mode and the signal comparison mode are alternately switched, and the digital-to-analog converter (160) is also configured to generate the feedback signal (Sfb) according to the second comparison signal (CMPn).9.如权利要求2至8中任一所述的三角积分模拟数字转换器(100)，其中，在该第一比较器(132)与该回路滤波器(120)之间的信号路径上，并未耦接任何抖动信号产生电路。9. The delta-sigma analog-to-digital converter (100) as claimed in any one of claims 2 to 8, wherein, on the signal path between the first comparator (132) and the loop filter (120), It is not coupled to any jitter signal generating circuit.10.如权利要求2至8中任一所述的三角积分模拟数字转换器(100)，其中，该第一比较器(132)的该第一输入端(322)、该第二输入端(324)、该第三输入端(326)、与该第四输入端(328)，皆未耦接任何抖动信号产生电路。10. The delta-sigma analog-to-digital converter (100) as claimed in any one of claims 2 to 8, wherein the first input terminal (322), the second input terminal ( 324 ), the third input terminal ( 326 ), and the fourth input terminal ( 328 ) are not coupled to any jitter signal generating circuit.

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