CN111459876A - FPGA system with EC function - Google Patents

Abstract

The invention relates to an FPGA system with an EC function, which comprises an FPGA chip, an input interface and an output interface, wherein the FPGA chip is respectively and electrically connected with the input interface and the output interface, the other end of the input interface is respectively and electrically connected with a sensor, a keyboard and a battery module, and the other end of the output interface is respectively and electrically connected with a power supply module, an indicator lamp, a fan speed regulation module, a display screen brightness module and a CPU. The FPGA chip is connected with the input interface and the output interface, the input interface is electrically connected with the sensor, the keyboard and the battery module, and the output interface is electrically connected with the power module, the indicator light, the fan speed regulation module, the display screen brightness module and the CPU to form an FPGA system, so that the FPGA system realizes all functions of the EC chip. Different domestic FPGA chips can be selected according to use requirements, and the FPGA system has the advantages of strong universality, low price, small volume, high reliability and the like.

Description

FPGA system with EC function

Technical Field

The invention relates to an embedded system, in particular to an FPGA system with an EC function.

Background

The embedded controller EC (embedded controller) can be widely applied to notebook computers, and can meet related functional requirements of the notebook computers on a keyboard module, a power supply management module, an indicator light module, a fan control module and the like, at present, the embedded controller EC is mainly obtained by adopting a special chip which is mainly produced in Taiwan and America and has no domestic special chip, the universality of the special chip is poor, and the price is higher, and the other mode is that the embedded controller EC adopts a CP L D + ARM combined design, the CP L D is responsible for connecting and converting a L PC protocol to communicate with a host CPU or a bridge chip, and the ARM is responsible for connecting a keyboard, a sensor, a fan, a display screen and the like, but the structure has complex circuit, large volume and relatively poor reliability, and the size is an important index for the notebook computer mainboard or the embedded system, so the structure has low practicability.

Disclosure of Invention

Aiming at the technical problems in the prior art, the invention provides the FPGA system with the EC function, which has small volume and high reliability.

The technical scheme for solving the technical problems is as follows: the FPGA system with the EC function is characterized by comprising an FPGA chip, an input interface and an output interface, wherein the FPGA chip is electrically connected with the input interface and the output interface respectively, the other end of the input interface is electrically connected with a sensor, a keyboard and a battery module respectively, and the other end of the output interface is electrically connected with a power supply module, an indicator lamp, a fan speed regulation module, a display screen brightness module and a CPU respectively.

On the basis of the technical scheme, in order to achieve the convenience of use and the stability of equipment, the invention can also make the following improvements on the technical scheme:

further, the input interface comprises an I2C bus, an input I/O (input/output) bus and an SMBUS (system management bus), and the sensors comprise a temperature sensor, a light sensor and a screen opening and closing sensor.

Furthermore, the I2C bus is respectively and electrically connected with a temperature sensor and a light sensor, the temperature sensor is used for monitoring the temperature of the CPU and the GPU in real time, the light sensor is used for collecting ambient light signals, the temperature sensor transmits the detected temperature signals to the FPGA chip through the I2C bus, the FPGA chip transmits the detected temperature signals to the CPU through the L PC bus, the light signals collected by the light sensor are transmitted to the FPGA chip through the I2C bus, and the FPGA chip automatically adjusts the brightness of the display screen according to the intensity of light.

The FPGA chip receives key values of the keyboard and transmits the key values to the CPU through an L PC bus, when the screen opening and closing sensor detects that the screen is closed, the FPGA chip closes the backlight of the display screen, the power consumption of the system is reduced, and when the screen opening and closing sensor detects that the screen is opened, the FPGA chip restores the backlight of the display screen.

The FPGA chip transmits the received battery state signal to the CPU through L PC bus.

Further, the output interfaces include an output I/O, PWM interface and L PC bus.

The FPGA chip controls the color and the display state of the indicator light according to the charge-discharge state of the battery, and the FPGA chip controls the power-on and power-off of the system power supply according to the power-on state of the L PC bus.

Furthermore, the PWM interface is respectively and electrically connected with the fan speed regulation module and the display screen brightness module. The FPGA chip is connected with a PWM pin of the fan through a PWM interface, and the rotating speed of the fan is adjusted according to temperature signals of the CPU and the GPU fed back by the temperature sensor, and the numerical value of the rotating speed feedback pin of the fan is recorded. The FPGA chip automatically adjusts the brightness of the display screen according to the numerical value of the light sensor, supports the brightness adjusting key to manually add and subtract the brightness, records the current brightness numerical value, and restores the brightness value after the next power-on.

The FPGA chip is connected with the CPU through a L PC bus, and transmits temperature signals of the CPU and the GPU and state signals of the battery to the CPU through a L PC bus.

The invention has the advantages that a single FPGA chip is connected with the input interface and the output interface, the input interface is electrically connected with the sensor, the keyboard and the battery module, and the output interface is electrically connected with the power module, the indicator light, the fan speed regulation module, the display screen brightness module and the CPU to form an FPGA system, so that the FPGA system realizes all functions of the EC chips such as L PC bus communication, sensor signal acquisition, screen brightness regulation, battery management, fan speed regulation, power control and the like.

Drawings

Fig. 1 is a schematic structural diagram of an FPGA system of the present invention.

The reference numbers are recorded as follows: the system comprises anFPGA chip 100, aninput interface 200, anoutput interface 300, atemperature sensor 201, alight sensor 202, akeyboard 203, a screen opening andclosing sensor 204, abattery module 205, a displayscreen brightness module 301, a fanspeed regulation module 302, anindicator light 303, apower supply module 304 and aCPU 305.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.

As shown in fig. 1, an FPGA system with an EC function includes anFPGA chip 100, aninput interface 200, and anoutput interface 300, where theFPGA chip 100 is electrically connected to theinput interface 200 and theoutput interface 300, the other end of theinput interface 200 is electrically connected to a sensor, akeyboard 203, and abattery module 205, and the other end of theoutput interface 300 is electrically connected to apower module 304, anindicator light 303, a fanspeed regulation module 302, a displayscreen brightness module 301, and a CPU305, respectively. TheFPGA chip 100 adopts a domestic bee series FPGA chip with a crystal oscillator and a program memory integrated inside, and can be used in cooperation with domestic processors such as Feiteng FT1500, Feiteng FT2000 and the like.

Theinput interface 200 comprises an I2C bus, an input I/O bus and an SMBUS bus, and the sensors comprise atemperature sensor 201, alight sensor 202 and a screen opening andclosing sensor 204.

The I2C bus is respectively electrically connected with thetemperature sensor 201 and thelight sensor 202, thetemperature sensor 201 is used for monitoring the temperature of a CPU and a GPU in real time, thelight sensor 202 is used for collecting ambient light signals, thetemperature sensor 201 transmits the detected temperature signals to theFPGA chip 100 through the I2C bus, theFPGA chip 100 transmits the temperature signals to the CPU305 through the L PC bus, the light signals collected by thelight sensor 202 are transmitted to theFPGA chip 100 through the I2C bus, and theFPGA chip 100 automatically adjusts the brightness of the display screen through a PWM interface according to the intensity of light.

The input I/O is respectively connected with akeyboard 203 and a screen opening andclosing sensor 204, thekeyboard 203 transmits keys of thekeyboard 203 through the input I/O, key values such as volume +, volume-, screen backlight +, screen backlight-, a touch pad switch, a WIFI switch, a screen switch, a switching display screen and the like can be set in a self-defined mode AT the same time, an FPGA chip receives the key values of the keyboard and converts the key values into standard second keyboard (AT key) key values to be transmitted to a CPU305 through an L PC bus, the screen opening andclosing sensor 204 is used for collecting opening and closing signals of a screen, when the screen opening andclosing sensor 204 detects that the screen is closed, theFPGA chip 100 closes the backlight of the display screen to reduce the power consumption of a system, and when the screen opening andclosing sensor 204 detects that the screen is opened, theFPGA chip 100 restores the backlight of the.

The SMBUS bus is electrically connected with thebattery module 205, thebattery module 205 transmits a state signal of the battery through the SMBUS bus, the battery state comprises information such as charging, discharging, whether the battery is completely consumed, the remaining percentage capacity of the battery, the full charge capacity of the battery, the remaining capacity of the battery, the temperature of the battery, the voltage of the battery, the current of the battery, the average current of the battery, the full charge capacity of the battery design, the voltage of the battery design, the serial number of the battery and the like, and theFPGA chip 100 transmits the received battery state signal to the CPU through the L PC bus.

Theoutput interface 200 includes an output I/O, PWM interface and a L PC bus.

The output I/O is respectively and electrically connected with theindicator light 303 and thepower supply module 304, theFPGA chip 100 controls the color and the display state of theindicator light 303 according to the charge-discharge state of the battery, when the battery is used for supplying power and the battery power is sufficient, theindicator light 303 is displayed to be light green and normally on, when the battery power is insufficient, theindicator light 303 is displayed to be light green and normally on, when an external direct current power supply or an adapter is used for supplying power and the battery is charged, theindicator light 303 is displayed to be light green and normally on, after the charging is finished, theFPGA chip 100 controls the power-on and power-off of the power supplies of the system, such as 5V, 3.3V, 1.8V and the like according to the power-on state of the L PC bus, such as restarting, shutdown, startup, S3 suspension, S63.

The PWM interface is electrically connected to the fanspeed regulation module 302 and the displayscreen brightness module 301, respectively. TheFPGA chip 100 is connected to the PWM pin of the fan through the PWM interface according to the temperatures of the CPU and the GPU fed back by thetemperature sensor 201, thereby adjusting the rotation speed of the fan and recording the value of the fan rotation speed feedback pin. TheFPGA chip 100 automatically adjusts the brightness of the display screen in the displayscreen brightness module 301 according to the value of thelight sensor 202, supports the brightness adjustment key to manually add or subtract the brightness, records the current brightness value, and restores the brightness value after the next power-on, wherein the brightness adjustment range of the displayscreen brightness module 301 is 0-100.

The L PC bus is electrically connected to the CPU305 theFPGA chip 100 is connected to the CPU305 via the L PC bus and transmits the CPU, GPU temperature signals and battery status signals to the CPU305 via the L PC bus.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (9)

1. The FPGA system with the EC function is characterized by comprising an FPGA chip, an input interface and an output interface, wherein the FPGA chip is electrically connected with the input interface and the output interface respectively, the other end of the input interface is electrically connected with a sensor, a keyboard and a battery module respectively, and the other end of the output interface is electrically connected with a power supply module, an indicator lamp, a fan speed regulation module, a display screen brightness module and a CPU respectively.

2. The EC-capable FPGA system of claim 1, wherein the input interfaces comprise an I2C bus, an input I/O and an SMBUS bus, and the sensors comprise a temperature sensor, a light sensor and a screen open/close sensor.

3. The FPGA system with EC function of claim 2, wherein the I2C bus is electrically connected with a temperature sensor and a light sensor respectively, the temperature sensor is used for monitoring the temperature of CPU and GPU in real time, and the light sensor is used for collecting the ambient light signal.

4. The FPGA system with the EC function of claim 2, wherein the input I/O is respectively connected with a keyboard and a screen opening/closing sensor, the keyboard transmits keys of the keyboard through the input I/O, and the screen opening/closing sensor is used for acquiring opening/closing signals of a screen.

5. The EC-enabled FPGA system of claim 2 wherein the SMBUS bus is electrically connected to a battery module that transmits a status signal of the battery via the SMBUS bus.

6. The EC-enabled FPGA system of claim 1, wherein the output interface comprises an output I/O, PWM interface and a L PC bus.

7. The EC-enabled FPGA system of claim 6, wherein the output I/O is electrically connected to an indicator light and a power module, respectively.

8. The FPGA system with EC function of claim 6, wherein the PWM interface is electrically connected with the fan speed regulation module and the display screen brightness module respectively.

9. The EC-enabled FPGA system of claim 6, wherein the L PC bus is electrically connected with a CPU.

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