CN111431517A - Ultra-high-speed bootstrap switch circuit with embedded input buffer - Google Patents
Ultra-high-speed bootstrap switch circuit with embedded input bufferDownload PDFInfo
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明涉及半导体集成电路技术领域，特别涉及内嵌输入缓冲器的超高速自举开关电路。The invention relates to the technical field of semiconductor integrated circuits, in particular to an ultra-high-speed bootstrap switch circuit with an embedded input buffer.
背景技术Background technique
模数转换器的输入自举开关的工作速度直接决定了模数转换器的转换速率。传统的自举开关不仅仅需要驱动采样电容，也需要驱动自举开关的栅极。当模数转换器的转换速率升高时，需要在极短的时间内抬升自举开关的栅极电位。这就需要具有大驱动能力的输入驱动电路。这会大幅提高电路的能量消耗。而且，也不一定能实现高速采样。传统的自举开关也需要一个或多个电容用于抬升自举开关的栅极电压。这也不利于将自举开关应用于小尺寸工艺上。The working speed of the input bootstrap switch of the analog-to-digital converter directly determines the conversion rate of the analog-to-digital converter. The traditional bootstrap switch not only needs to drive the sampling capacitor, but also needs to drive the gate of the bootstrap switch. When the slew rate of the analog-to-digital converter increases, the gate potential of the bootstrap switch needs to be raised in a very short time. This requires an input drive circuit with a large drive capability. This greatly increases the power consumption of the circuit. Also, high-speed sampling is not always possible. Conventional bootstrap switches also require one or more capacitors to boost the gate voltage of the bootstrap switch. This is also not conducive to the application of the bootstrap switch to the small size process.
发明内容SUMMARY OF THE INVENTION
为克服现有技术中的问题，本发明的目的是提供一种内嵌输入缓冲器的超高速自举开关电路，可以实现高速的工作状态切换，也可以等比例缩小，应用在更小的工艺上。In order to overcome the problems in the prior art, the purpose of the present invention is to provide an ultra-high-speed bootstrap switch circuit with an embedded input buffer, which can realize high-speed working state switching, and can also be scaled down to be applied in a smaller process. superior.
为达到上述目的，本发明采用的技术方案如下：For achieving the above object, the technical scheme adopted in the present invention is as follows:
内嵌输入缓冲器的超高速自举开关电路，包括输入NMOS管、输入PMOS管、导通开关NMOS管、时钟控制NMOS管、第一恒流源和第二恒流源、输入端以及输出端、时钟控制管以及时钟信号输入端；An ultra-high-speed bootstrap switch circuit with an embedded input buffer, including an input NMOS transistor, an input PMOS transistor, an on-switch NMOS transistor, a clock-controlled NMOS transistor, a first constant current source and a second constant current source, an input end and an output end , clock control tube and clock signal input terminal;
输入端与输入PMOS管的栅极及输入NMOS管的栅极相连；高压源经第一恒流源与输入PMOS管的源极、导通开关NMOS管的栅极以及时钟控制NMOS管的漏极相连接，时钟控制NMOS管的栅极与时钟信号输入端相连接，输入PMOS管的漏极及时钟控制NMOS管的源极接地；The input terminal is connected to the gate of the input PMOS tube and the gate of the input NMOS tube; the high-voltage source is connected to the source of the input PMOS tube through the first constant current source, the gate of the turn-on switch NMOS tube and the drain of the clock-controlled NMOS tube connected, the gate of the clock control NMOS tube is connected to the clock signal input terminal, the drain of the input PMOS tube and the source of the clock control NMOS tube are grounded;
输入NMOS管的漏极与高压源相连，第二恒流源的负极接地，信号输出端与导通开关NMOS管的漏极相连。The drain of the input NMOS transistor is connected to the high voltage source, the negative electrode of the second constant current source is grounded, and the signal output end is connected to the drain of the on-switch NMOS transistor.
本发明进一步的改进在于，当时钟信号输入端从高电平切换到低电平时，NMOS管从截断态切换到导通状态，第一节点对输出端充放电。A further improvement of the present invention is that when the input terminal of the clock signal is switched from a high level to a low level, the NMOS transistor is switched from the off state to the on state, and the first node charges and discharges the output terminal.
本发明进一步的改进在于，第一节点与输入NMOS管的源极、导通开关NMOS管的源极及第二恒流源的正极相连接，第一节点比输入端的电位低一个NMOS管的栅源电压差Vgsn。A further improvement of the present invention is that the first node is connected to the source of the input NMOS transistor, the source of the turn-on switch NMOS transistor and the positive pole of the second constant current source, and the first node is lower than the potential of the input terminal by one gate of the NMOS transistor Source voltage difference Vgsn.
本发明进一步的改进在于，当导通开关NMOS管处于导通状态时，输出端的电位等于第一节点的电位。A further improvement of the present invention lies in that, when the on-switch NMOS transistor is in the on-state, the potential of the output terminal is equal to the potential of the first node.
本发明进一步的改进在于，时钟控制NMOS管的漏极与导通开关NMOS管的栅极的连接位置作为第二节点；当时钟信号输入端从低电平切换到高电平时，第二节点的电位为0。A further improvement of the present invention is that the connection position of the drain of the clocked NMOS transistor and the gate of the NMOS transistor of the turn-on switch is used as the second node; when the clock signal input terminal is switched from low level to high level, the second node The potential is 0.
本发明进一步的改进在于，当时钟信号输入端为高电平时，导通开关NMOS管处于导通状态，第二恒流源上的电流通过时钟控制NMOS管流向地；第二节点的电位为0；导通开关NMOS管处于关闭状态；输出端处于高阻态。A further improvement of the present invention is that when the input terminal of the clock signal is at a high level, the turn-on switch NMOS tube is in a conducting state, and the current on the second constant current source flows to the ground through the clock control NMOS tube; the potential of the second node is 0 ; The conduction switch NMOS tube is in a closed state; the output terminal is in a high-impedance state.
本发明进一步的改进在于，当时钟信号输入端低电平时，时钟控制NMOS管处于关闭状态，第二节点比输入端的电位高出一个PMOS管的栅源电压差Vgsp，导通开关NMOS管的栅源电压差为Vgsn+Vgsp，其中，Vgsn为一个NMOS管的栅源电压差。A further improvement of the present invention is that when the input terminal of the clock signal is at a low level, the clock controls the NMOS transistor to be in an off state, the second node is higher than the potential of the input terminal by a gate-source voltage difference Vgsp of the PMOS transistor, and the gate of the NMOS transistor of the switch is turned on. The source voltage difference is Vgsn+Vgsp, wherein Vgsn is the gate-source voltage difference of an NMOS transistor.
与现有技术相比，本发明具有的有益效果：Compared with the prior art, the present invention has the following beneficial effects:
本发明的自举电路从高阻态切换到输入跟随状态时，PMOS源极跟随器可以快速驱动节点B，在极短的时间内开启NMOS管NM1。当自举电路从输入跟随状态切换到高阻态时，NMOS管NM2也可以快速地将第二节点B的电位下拉到地，在极短的时间内将NMOS管NM1关闭。本发明电路具有很高的工作状态切换速度。本发明的电路中没有使用电容器件，可以减小版图面积，并且可以在更先进的工艺下，使用更小的版图面积获得更好的性能。而且，电路中的源极跟随器可以隔离输入信号和自举开关，避免开关信号对输入信号的干扰。When the bootstrap circuit of the present invention switches from the high-impedance state to the input-following state, the PMOS source follower can rapidly drive the node B and turn on the NMOS transistor NM1 in a very short time. When the bootstrap circuit switches from the input following state to the high-impedance state, the NMOS transistor NM2 can also quickly pull down the potential of the second node B to the ground, turning off the NMOS transistor NM1 in a very short time. The circuit of the invention has a very high working state switching speed. No capacitor device is used in the circuit of the present invention, the layout area can be reduced, and better performance can be obtained by using a smaller layout area under a more advanced process. Moreover, the source follower in the circuit can isolate the input signal and the bootstrap switch to avoid the interference of the switching signal to the input signal.
附图说明Description of drawings
图1为本发明的内嵌输入缓冲器的超高速自举开关电路；1 is an ultra-high-speed bootstrap switch circuit with an embedded input buffer of the present invention;
图2为本发明自举开关电路的工作时序图。FIG. 2 is a working timing diagram of the bootstrap switch circuit of the present invention.
具体实施方式Detailed ways
下面结合附图对本发明作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。The present invention will be further described below in conjunction with the accompanying drawings. The following examples are only used to illustrate the technical solutions of the present invention more clearly, and cannot be used to limit the protection scope of the present invention.
本发明的电路结构如图1所示，包括一个输入NMOS管NM0、一个输入PMOS管PM0、一个导通开关NMOS管NM1、一个时钟控制NMOS管NM2、第一恒流源I0和第二恒流源I1、输入端vi以及输出端vo、时钟控制管NM2以及时钟信号输入端ck，第一节点A、第二节点B是电路的内部节点。The circuit structure of the present invention is shown in FIG. 1, including an input NMOS transistor NM0, an input PMOS transistor PM0, a turn-on switch NMOS transistor NM1, a clock control NMOS transistor NM2, a first constant current source I0 and a second constant current The source I1, the input end vi and the output end vo, the clock control tube NM2 and the clock signal input end ck, the first node A and the second node B are internal nodes of the circuit.
输入端vi与输入PMOS管PM0的栅极及输入NMOS管NM0的栅极相连；高压源经第一恒流源I1与输入PMOS管PM0的源极、导通开关NMOS管NM1的栅极以及时钟控制NMOS管的漏极相连接，时钟控制NMOS管NM2的栅极与时钟信号输入端ck相连接，输入PMOS管PM0的漏极及时钟控制NMOS管NM2的源极接地；The input end vi is connected to the gate of the input PMOS tube PM0 and the gate of the input NMOS tube NM0; the high-voltage source is connected to the source of the input PMOS tube PM0 through the first constant current source I1, the gate of the turn-on switch NMOS tube NM1 and the clock The drain of the control NMOS tube is connected, the gate of the clock control NMOS tube NM2 is connected to the clock signal input terminal ck, the drain of the input PMOS tube PM0 and the source of the clock control NMOS tube NM2 are grounded;
输入NMOS管NM0的漏极与高压源相连，第一节点A与输入NMOS管NM0的源极、导通开关NMOS管NM1的源极及第二恒流源I0的正极相连接，第二恒流源I0的负极接地，信号输出端vo与导通开关NMOS管NM1的漏极相连；The drain of the input NMOS transistor NM0 is connected to the high voltage source, the first node A is connected to the source of the input NMOS transistor NM0, the source of the turn-on switch NMOS transistor NM1 and the positive electrode of the second constant current source I0, the second constant current The negative pole of the source I0 is grounded, and the signal output terminal vo is connected to the drain of the on-switch NMOS transistor NM1;
时钟控制NMOS管NM2的漏极与导通开关NMOS管NM1的栅极的连接位置作为第二节点B。The connection position of the drain of the clocked NMOS transistor NM2 and the gate of the turn-on switch NMOS transistor NM1 is used as the second node B.
图2本发明电路的工作时序，时钟控制管ck用于控制电路的工作状态。当时钟信号输入端ck的时钟信号为高电平时，电路处于高阻状态。当时钟信号输入端ck的时钟信号为低电平时，电路处于输入跟随状态。Figure 2 shows the working sequence of the circuit of the present invention, and the clock control tube ck is used to control the working state of the circuit. When the clock signal at the clock signal input terminal ck is at a high level, the circuit is in a high-impedance state. When the clock signal at the clock signal input terminal ck is at a low level, the circuit is in an input following state.
图1中的NMOS管NM0和第一恒流源I0共同组成一个NMOS源极跟随器，直接驱动第一节点A即驱动导通开关NMOS管NM1的源极。无论电路处于何种状态，第一节点A都跟随输入端vi信号变化。并且第一节点A比输入端vi的电位低一个NMOS管的栅源电压差Vgsn。当导通开关NMOS管NM1处于导通状态时，输出端vo的电位等于第一节点A的电位。The NMOS transistor NM0 and the first constant current source I0 in FIG. 1 together form an NMOS source follower, which directly drives the first node A, that is, drives the source of the switch NMOS transistor NM1 . No matter what state the circuit is in, the first node A changes with the input terminal vi signal. And the potential of the first node A is lower than the potential of the input terminal vi by a gate-source voltage difference Vgsn of the NMOS transistor. When the on-switch NMOS transistor NM1 is in the on state, the potential of the output terminal vo is equal to the potential of the first node A.
图1中的PMOS管PM0和第一恒流源I1共同组成一个PMOS源极跟随器，直接驱动第二节点B，即驱动导通开关NMOS管NM1的栅极。当时钟信号输入端ck的时钟信号为低电平时，第二节点B跟随输入端vi信号变化。并且第二节点B比输入端vi的电位高出一个PMOS管的栅源电压差Vgsp。此时导通开关NMOS管NM1的栅源电压差为Vgsn+Vgsp。该电压差和输入信号的电压值无关。The PMOS transistor PM0 and the first constant current source I1 in FIG. 1 together form a PMOS source follower, which directly drives the second node B, that is, drives the gate of the switch NMOS transistor NM1. When the clock signal at the clock signal input terminal ck is at a low level, the second node B changes with the signal at the input terminal vi. And the second node B is higher than the potential of the input terminal vi by a gate-source voltage difference Vgsp of the PMOS transistor. At this time, the gate-source voltage difference of the switch NMOS transistor NM1 is Vgsn+Vgsp. This voltage difference is independent of the voltage value of the input signal.
从NM1的栅源电压差的表达式知道，可以通过调整第一恒流源I0、第一恒流源I1或者NMOS管NM0、PMOS管PM0的尺寸来改变NM1的栅源电压差的具体电压值。当时钟信号输入端ck为高电平时，NMOS管NM2处于开启状态，第二恒流源I1上的电流都通过NMOS管NM2流向地。第二节点B被下拉到地。NMOS管NM1处于关闭状态。输出端vo处于高阻态。From the expression of the gate-source voltage difference of NM1, it can be known that the specific voltage value of the gate-source voltage difference of NM1 can be changed by adjusting the size of the first constant current source I0, the first constant current source I1 or the NMOS transistor NM0 and the PMOS transistor PM0. . When the clock signal input terminal ck is at a high level, the NMOS transistor NM2 is in an on state, and the current on the second constant current source I1 flows to the ground through the NMOS transistor NM2. The second Node B is pulled down to ground. The NMOS transistor NM1 is in an off state. The output terminal vo is in a high-impedance state.
当自举开关电路的时钟信号输入端ck从低电平切换到高电平时，第二节点B被下拉到0。第二节点B的电位跳变，通过NMOS管NM1的栅源寄生电容耦合到第一节点A。对于传统的自举开关电路，只能任凭时钟干扰影响输入信号。而在被发明中，NMOS源极跟随器的低输出阻抗特性，可以吸收该时钟干扰，隔离输入端vi和自举开关的内部节点，尽可能地避免时钟干扰耦合到输入端。When the clock signal input terminal ck of the bootstrap switch circuit is switched from a low level to a high level, the second node B is pulled down to 0. The potential jump of the second node B is coupled to the first node A through the gate-source parasitic capacitance of the NMOS transistor NM1. For traditional bootstrap switching circuits, the input signal can only be affected by clock disturbances. In the invention, the low output impedance characteristics of the NMOS source follower can absorb the clock interference, isolate the input terminal vi and the internal node of the bootstrap switch, and avoid the clock interference coupling to the input terminal as much as possible.
当自举开关电路的时钟信号输入端ck从高电平切换到低电平时，第二节点B跟随输入端vi变化。NMOS管NM1从截断态切换到导通状态，第一节点A对输出端vo充放电。此时，NMOS源极跟随器可以为第一节点A提供充放电电流，避免对输入端vi的干扰。When the clock signal input terminal ck of the bootstrap switch circuit is switched from a high level to a low level, the second node B changes with the input terminal vi. The NMOS transistor NM1 is switched from the off state to the on state, and the first node A charges and discharges the output terminal vo. At this time, the NMOS source follower can provide charging and discharging current for the first node A to avoid interference to the input terminal vi.
本发明的自举电路从高阻态切换到输入跟随状态时，PMOS源极跟随器可以快速驱动节点B，在极短的时间内开启NMOS管NM1。当自举电路从输入跟随状态切换到高阻态时，NMOS管NM2也可以快速地将第二节点B的电位下拉到地，在极短的时间内将NMOS管NM1关闭。本发明电路具有很高的工作状态切换速度。When the bootstrap circuit of the present invention switches from the high-impedance state to the input-following state, the PMOS source follower can rapidly drive the node B and turn on the NMOS transistor NM1 in a very short time. When the bootstrap circuit switches from the input following state to the high-impedance state, the NMOS transistor NM2 can also quickly pull down the potential of the second node B to ground, and turn off the NMOS transistor NM1 in a very short time. The circuit of the invention has a very high working state switching speed.
NMOS管NM2用于控制自举开关电路的工作状态。当时钟信号输入端ck的时钟信号为低电平时，NMOS管NM2处于关闭状态，第二节点B跟随输入端vi，NMOS管NM1的栅源电压保持在Vgsn+Vgsp。当时钟信号输入端ck的时钟信号为高电平时，NMOS管NM2处于导通状态，第二恒流源I1的电流都经过NMOS管NM2流向地，第二节点B的电位为0，NMOS管NM1处于关闭状态。The NMOS transistor NM2 is used to control the working state of the bootstrap switch circuit. When the clock signal at the clock signal input terminal ck is at a low level, the NMOS transistor NM2 is in an off state, the second node B follows the input terminal vi, and the gate-source voltage of the NMOS transistor NM1 remains at Vgsn+Vgsp. When the clock signal of the clock signal input terminal ck is at a high level, the NMOS transistor NM2 is in a conducting state, the current of the second constant current source I1 flows to the ground through the NMOS transistor NM2, the potential of the second node B is 0, and the NMOS transistor NM1 is closed.
本发明提出的自举开关电路结构，不包含电容，而且结构简单。除了可以实现高速的工作状态切换外，也可以等比例缩小，使用更先进的小尺寸工艺上。The bootstrap switch circuit structure proposed by the present invention does not include capacitors and has a simple structure. In addition to realizing high-speed working state switching, it can also be scaled down and use more advanced small-scale technology.
当时钟信号ck为低电平时，导通开关NMOS管NM1处于导通状态，导通开关NMOS管NM1的栅极跟随输入变化，导通开关NMOS管NM1的栅源电压差保持不变。当时钟信号ck为高电平时，时钟控制NMOS管NM2将导通开关NMOS管NM1的栅极电压下拉到0，导通开关NMOS管NM1处于关闭状态。本发明利用NMOS源极跟随器和PMOS源极跟随器的直流电压差来实现自举开关的电压抬升，和传统的自举开关电路相比，省去了用于抬升开关电压的电容。另外，源极跟随器的工作速度快，时钟信号ck从高电平跳变到低电平时，节点B的电位可以快速跟随输入电压。当时钟信号ck从低电平跳变到高电平时，节点B的电位也可以被快速下拉到0。本发明不仅仅电路结构简单，而且具有高速的工作状态切换速度。When the clock signal ck is low level, the on-switch NMOS transistor NM1 is in an on state, the gate of the on-switch NMOS transistor NM1 changes with the input, and the gate-source voltage difference of the on-switch NMOS transistor NM1 remains unchanged. When the clock signal ck is at a high level, the clock controls the NMOS transistor NM2 to pull down the gate voltage of the turn-on switch NMOS tube NM1 to 0, and the turn-on switch NMOS tube NM1 is in an off state. The invention utilizes the DC voltage difference between the NMOS source follower and the PMOS source follower to realize the voltage boost of the bootstrap switch, and compared with the traditional bootstrap switch circuit, the capacitor for boosting the switch voltage is omitted. In addition, the working speed of the source follower is fast. When the clock signal ck transitions from a high level to a low level, the potential of the node B can quickly follow the input voltage. When the clock signal ck transitions from a low level to a high level, the potential of the node B can also be quickly pulled down to 0. The invention not only has a simple circuit structure, but also has a high-speed working state switching speed.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.
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